1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
28 def SDT_PPCvperm : SDTypeProfile<1, 3, [
29 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
32 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
33 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
36 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
37 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
40 def SDT_PPClbrx : SDTypeProfile<1, 3, [
41 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
44 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific DAG Nodes.
51 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
52 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
53 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
54 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
56 def PPCfsel : SDNode<"PPCISD::FSEL",
57 // Type constraint for fsel.
58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
59 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
61 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
62 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
63 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
64 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
66 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
68 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
69 // amounts. These nodes are generated by the multi-precision shift code.
70 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
71 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
72 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
74 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
75 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
79 [SDNPHasChain, SDNPOutFlag]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
81 [SDNPHasChain, SDNPOutFlag]>;
83 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
84 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
85 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
86 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
87 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
88 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
89 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
90 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
91 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
93 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
94 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
96 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
97 [SDNPHasChain, SDNPOptInFlag]>;
99 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
100 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
102 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
103 [SDNPHasChain, SDNPOptInFlag]>;
105 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
106 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
108 // Instructions to support dynamic alloca.
109 def SDTDynOp : SDTypeProfile<1, 2, []>;
110 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
112 //===----------------------------------------------------------------------===//
113 // PowerPC specific transformation functions and pattern fragments.
116 def SHL32 : SDNodeXForm<imm, [{
117 // Transformation function: 31 - imm
118 return getI32Imm(31 - N->getValue());
121 def SRL32 : SDNodeXForm<imm, [{
122 // Transformation function: 32 - imm
123 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
126 def LO16 : SDNodeXForm<imm, [{
127 // Transformation function: get the low 16 bits.
128 return getI32Imm((unsigned short)N->getValue());
131 def HI16 : SDNodeXForm<imm, [{
132 // Transformation function: shift the immediate value down into the low bits.
133 return getI32Imm((unsigned)N->getValue() >> 16);
136 def HA16 : SDNodeXForm<imm, [{
137 // Transformation function: shift the immediate value down into the low bits.
138 signed int Val = N->getValue();
139 return getI32Imm((Val - (signed short)Val) >> 16);
141 def MB : SDNodeXForm<imm, [{
142 // Transformation function: get the start bit of a mask
144 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
145 return getI32Imm(mb);
148 def ME : SDNodeXForm<imm, [{
149 // Transformation function: get the end bit of a mask
151 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
152 return getI32Imm(me);
154 def maskimm32 : PatLeaf<(imm), [{
155 // maskImm predicate - True if immediate is a run of ones.
157 if (N->getValueType(0) == MVT::i32)
158 return isRunOfOnes((unsigned)N->getValue(), mb, me);
163 def immSExt16 : PatLeaf<(imm), [{
164 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
165 // field. Used by instructions like 'addi'.
166 if (N->getValueType(0) == MVT::i32)
167 return (int32_t)N->getValue() == (short)N->getValue();
169 return (int64_t)N->getValue() == (short)N->getValue();
171 def immZExt16 : PatLeaf<(imm), [{
172 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
173 // field. Used by instructions like 'ori'.
174 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
177 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
178 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
179 // identical in 32-bit mode, but in 64-bit mode, they return true if the
180 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
182 def imm16ShiftedZExt : PatLeaf<(imm), [{
183 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
184 // immediate are set. Used by instructions like 'xoris'.
185 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
188 def imm16ShiftedSExt : PatLeaf<(imm), [{
189 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
190 // immediate are set. Used by instructions like 'addis'. Identical to
191 // imm16ShiftedZExt in 32-bit mode.
192 if (N->getValue() & 0xFFFF) return false;
193 if (N->getValueType(0) == MVT::i32)
195 // For 64-bit, make sure it is sext right.
196 return N->getValue() == (uint64_t)(int)N->getValue();
200 //===----------------------------------------------------------------------===//
201 // PowerPC Flag Definitions.
203 class isPPC64 { bit PPC64 = 1; }
205 list<Register> Defs = [CR0];
209 class RegConstraint<string C> {
210 string Constraints = C;
212 class NoEncode<string E> {
213 string DisableEncoding = E;
217 //===----------------------------------------------------------------------===//
218 // PowerPC Operand Definitions.
220 def s5imm : Operand<i32> {
221 let PrintMethod = "printS5ImmOperand";
223 def u5imm : Operand<i32> {
224 let PrintMethod = "printU5ImmOperand";
226 def u6imm : Operand<i32> {
227 let PrintMethod = "printU6ImmOperand";
229 def s16imm : Operand<i32> {
230 let PrintMethod = "printS16ImmOperand";
232 def u16imm : Operand<i32> {
233 let PrintMethod = "printU16ImmOperand";
235 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
236 let PrintMethod = "printS16X4ImmOperand";
238 def target : Operand<OtherVT> {
239 let PrintMethod = "printBranchOperand";
241 def calltarget : Operand<iPTR> {
242 let PrintMethod = "printCallOperand";
244 def aaddr : Operand<iPTR> {
245 let PrintMethod = "printAbsAddrOperand";
247 def piclabel: Operand<iPTR> {
248 let PrintMethod = "printPICLabel";
250 def symbolHi: Operand<i32> {
251 let PrintMethod = "printSymbolHi";
253 def symbolLo: Operand<i32> {
254 let PrintMethod = "printSymbolLo";
256 def crbitm: Operand<i8> {
257 let PrintMethod = "printcrbitm";
260 def memri : Operand<iPTR> {
261 let PrintMethod = "printMemRegImm";
262 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
264 def memrr : Operand<iPTR> {
265 let PrintMethod = "printMemRegReg";
266 let MIOperandInfo = (ops ptr_rc, ptr_rc);
268 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
269 let PrintMethod = "printMemRegImmShifted";
270 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
273 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
274 // that doesn't matter.
275 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
276 (ops (i32 20), CR0)> {
277 let PrintMethod = "printPredicateOperand";
280 // Define PowerPC specific addressing mode.
281 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
282 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
283 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
284 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
286 /// This is just the offset part of iaddr, used for preinc.
287 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
289 //===----------------------------------------------------------------------===//
290 // PowerPC Instruction Predicate Definitions.
291 def FPContractions : Predicate<"!NoExcessFPPrecision">;
294 //===----------------------------------------------------------------------===//
295 // PowerPC Instruction Definitions.
297 // Pseudo-instructions:
299 let hasCtrlDep = 1 in {
300 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
301 "${:comment} ADJCALLSTACKDOWN",
302 [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
303 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
304 "${:comment} ADJCALLSTACKUP",
305 [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
307 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
308 "UPDATE_VRSAVE $rD, $rS", []>;
311 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
312 "${:comment} DYNALLOC $result, $negsize, $fpsi",
314 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>,
317 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
318 "${:comment}IMPLICIT_DEF_GPRC $rD",
319 [(set GPRC:$rD, (undef))]>;
320 def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
321 "${:comment} IMPLICIT_DEF_F8 $rD",
322 [(set F8RC:$rD, (undef))]>;
323 def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
324 "${:comment} IMPLICIT_DEF_F4 $rD",
325 [(set F4RC:$rD, (undef))]>;
327 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
328 // scheduler into a branch sequence.
329 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
330 PPC970_Single = 1 in {
331 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
332 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
334 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
335 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
337 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
338 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
340 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
341 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
343 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
344 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
348 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
350 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
351 "b${p:cc}lr ${p:reg}", BrB,
353 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
359 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
362 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
363 let isBarrier = 1 in {
364 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
369 // BCC represents an arbitrary conditional branch on a predicate.
370 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
371 // a two-value operand where a dag node expects two operands. :(
372 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
373 "b${cond:cc} ${cond:reg}, $dst"
374 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
378 let isCall = 1, PPC970_Unit = 7,
379 // All calls clobber the non-callee saved registers...
380 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
381 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
382 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
384 CR0,CR1,CR5,CR6,CR7] in {
385 // Convenient aliases for call instructions
386 def BL_Macho : IForm<18, 0, 1,
387 (outs), (ins calltarget:$func, variable_ops),
388 "bl $func", BrB, []>; // See Pat patterns below.
389 def BLA_Macho : IForm<18, 1, 1,
390 (outs), (ins aaddr:$func, variable_ops),
391 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
392 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
393 (outs), (ins variable_ops),
399 let isCall = 1, PPC970_Unit = 7,
400 // All calls clobber the non-callee saved registers...
401 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
402 F0,F1,F2,F3,F4,F5,F6,F7,F8,
403 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
405 CR0,CR1,CR5,CR6,CR7] in {
406 // Convenient aliases for call instructions
407 def BL_ELF : IForm<18, 0, 1,
408 (outs), (ins calltarget:$func, variable_ops),
409 "bl $func", BrB, []>; // See Pat patterns below.
410 def BLA_ELF : IForm<18, 1, 1,
411 (outs), (ins aaddr:$func, variable_ops),
413 [(PPCcall_ELF (i32 imm:$func))]>;
414 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
415 (outs), (ins variable_ops),
420 // DCB* instructions.
421 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
422 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
423 PPC970_DGroup_Single;
424 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
425 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
426 PPC970_DGroup_Single;
427 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
428 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
429 PPC970_DGroup_Single;
430 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
431 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
432 PPC970_DGroup_Single;
433 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
434 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
435 PPC970_DGroup_Single;
436 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
437 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
438 PPC970_DGroup_Single;
439 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
440 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
441 PPC970_DGroup_Single;
442 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
443 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
444 PPC970_DGroup_Single;
446 //===----------------------------------------------------------------------===//
447 // PPC32 Load Instructions.
450 // Unindexed (r+i) Loads.
451 let isLoad = 1, PPC970_Unit = 2 in {
452 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
453 "lbz $rD, $src", LdStGeneral,
454 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
455 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
456 "lha $rD, $src", LdStLHA,
457 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
458 PPC970_DGroup_Cracked;
459 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
460 "lhz $rD, $src", LdStGeneral,
461 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
462 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
463 "lwz $rD, $src", LdStGeneral,
464 [(set GPRC:$rD, (load iaddr:$src))]>;
466 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
467 "lfs $rD, $src", LdStLFDU,
468 [(set F4RC:$rD, (load iaddr:$src))]>;
469 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
470 "lfd $rD, $src", LdStLFD,
471 [(set F8RC:$rD, (load iaddr:$src))]>;
474 // Unindexed (r+i) Loads with Update (preinc).
475 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
476 "lbzu $rD, $addr", LdStGeneral,
477 []>, RegConstraint<"$addr.reg = $ea_result">,
478 NoEncode<"$ea_result">;
480 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
481 "lhau $rD, $addr", LdStGeneral,
482 []>, RegConstraint<"$addr.reg = $ea_result">,
483 NoEncode<"$ea_result">;
485 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
486 "lhzu $rD, $addr", LdStGeneral,
487 []>, RegConstraint<"$addr.reg = $ea_result">,
488 NoEncode<"$ea_result">;
490 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
491 "lwzu $rD, $addr", LdStGeneral,
492 []>, RegConstraint<"$addr.reg = $ea_result">,
493 NoEncode<"$ea_result">;
495 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
496 "lfs $rD, $addr", LdStLFDU,
497 []>, RegConstraint<"$addr.reg = $ea_result">,
498 NoEncode<"$ea_result">;
500 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
501 "lfd $rD, $addr", LdStLFD,
502 []>, RegConstraint<"$addr.reg = $ea_result">,
503 NoEncode<"$ea_result">;
506 // Indexed (r+r) Loads.
508 let isLoad = 1, PPC970_Unit = 2 in {
509 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
510 "lbzx $rD, $src", LdStGeneral,
511 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
512 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
513 "lhax $rD, $src", LdStLHA,
514 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
515 PPC970_DGroup_Cracked;
516 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
517 "lhzx $rD, $src", LdStGeneral,
518 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
519 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
520 "lwzx $rD, $src", LdStGeneral,
521 [(set GPRC:$rD, (load xaddr:$src))]>;
524 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
525 "lhbrx $rD, $src", LdStGeneral,
526 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
527 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
528 "lwbrx $rD, $src", LdStGeneral,
529 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
531 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
532 "lfsx $frD, $src", LdStLFDU,
533 [(set F4RC:$frD, (load xaddr:$src))]>;
534 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
535 "lfdx $frD, $src", LdStLFDU,
536 [(set F8RC:$frD, (load xaddr:$src))]>;
539 //===----------------------------------------------------------------------===//
540 // PPC32 Store Instructions.
543 // Unindexed (r+i) Stores.
544 let isStore = 1, PPC970_Unit = 2 in {
545 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
546 "stb $rS, $src", LdStGeneral,
547 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
548 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
549 "sth $rS, $src", LdStGeneral,
550 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
551 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
552 "stw $rS, $src", LdStGeneral,
553 [(store GPRC:$rS, iaddr:$src)]>;
554 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
555 "stfs $rS, $dst", LdStUX,
556 [(store F4RC:$rS, iaddr:$dst)]>;
557 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
558 "stfd $rS, $dst", LdStUX,
559 [(store F8RC:$rS, iaddr:$dst)]>;
562 // Unindexed (r+i) Stores with Update (preinc).
563 let isStore = 1, PPC970_Unit = 2 in {
564 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
565 symbolLo:$ptroff, ptr_rc:$ptrreg),
566 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
567 [(set ptr_rc:$ea_res,
568 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
569 iaddroff:$ptroff))]>,
570 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
571 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
572 symbolLo:$ptroff, ptr_rc:$ptrreg),
573 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
574 [(set ptr_rc:$ea_res,
575 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
576 iaddroff:$ptroff))]>,
577 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
578 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
579 symbolLo:$ptroff, ptr_rc:$ptrreg),
580 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
581 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
582 iaddroff:$ptroff))]>,
583 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
584 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
585 symbolLo:$ptroff, ptr_rc:$ptrreg),
586 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
587 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
588 iaddroff:$ptroff))]>,
589 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
590 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
591 symbolLo:$ptroff, ptr_rc:$ptrreg),
592 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
593 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
594 iaddroff:$ptroff))]>,
595 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
599 // Indexed (r+r) Stores.
601 let isStore = 1, PPC970_Unit = 2 in {
602 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
603 "stbx $rS, $dst", LdStGeneral,
604 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
605 PPC970_DGroup_Cracked;
606 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
607 "sthx $rS, $dst", LdStGeneral,
608 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
609 PPC970_DGroup_Cracked;
610 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
611 "stwx $rS, $dst", LdStGeneral,
612 [(store GPRC:$rS, xaddr:$dst)]>,
613 PPC970_DGroup_Cracked;
614 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
615 "stwux $rS, $rA, $rB", LdStGeneral,
617 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
618 "sthbrx $rS, $dst", LdStGeneral,
619 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
620 PPC970_DGroup_Cracked;
621 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
622 "stwbrx $rS, $dst", LdStGeneral,
623 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
624 PPC970_DGroup_Cracked;
626 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
627 "stfiwx $frS, $dst", LdStUX,
628 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
629 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
630 "stfsx $frS, $dst", LdStUX,
631 [(store F4RC:$frS, xaddr:$dst)]>;
632 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
633 "stfdx $frS, $dst", LdStUX,
634 [(store F8RC:$frS, xaddr:$dst)]>;
638 //===----------------------------------------------------------------------===//
639 // PPC32 Arithmetic Instructions.
642 let PPC970_Unit = 1 in { // FXU Operations.
643 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
644 "addi $rD, $rA, $imm", IntGeneral,
645 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
646 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
647 "addic $rD, $rA, $imm", IntGeneral,
648 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
649 PPC970_DGroup_Cracked;
650 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
651 "addic. $rD, $rA, $imm", IntGeneral,
653 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
654 "addis $rD, $rA, $imm", IntGeneral,
655 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
656 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
657 "la $rD, $sym($rA)", IntGeneral,
658 [(set GPRC:$rD, (add GPRC:$rA,
659 (PPClo tglobaladdr:$sym, 0)))]>;
660 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
661 "mulli $rD, $rA, $imm", IntMulLI,
662 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
663 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
664 "subfic $rD, $rA, $imm", IntGeneral,
665 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
666 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
667 "li $rD, $imm", IntGeneral,
668 [(set GPRC:$rD, immSExt16:$imm)]>;
669 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
670 "lis $rD, $imm", IntGeneral,
671 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
674 let PPC970_Unit = 1 in { // FXU Operations.
675 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
676 "andi. $dst, $src1, $src2", IntGeneral,
677 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
679 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
680 "andis. $dst, $src1, $src2", IntGeneral,
681 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
683 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
684 "ori $dst, $src1, $src2", IntGeneral,
685 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
686 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
687 "oris $dst, $src1, $src2", IntGeneral,
688 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
689 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
690 "xori $dst, $src1, $src2", IntGeneral,
691 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
692 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
693 "xoris $dst, $src1, $src2", IntGeneral,
694 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
695 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
697 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
698 "cmpwi $crD, $rA, $imm", IntCompare>;
699 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
700 "cmplwi $dst, $src1, $src2", IntCompare>;
704 let PPC970_Unit = 1 in { // FXU Operations.
705 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
706 "nand $rA, $rS, $rB", IntGeneral,
707 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
708 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
709 "and $rA, $rS, $rB", IntGeneral,
710 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
711 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
712 "andc $rA, $rS, $rB", IntGeneral,
713 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
714 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
715 "or $rA, $rS, $rB", IntGeneral,
716 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
717 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
718 "nor $rA, $rS, $rB", IntGeneral,
719 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
720 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
721 "orc $rA, $rS, $rB", IntGeneral,
722 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
723 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
724 "eqv $rA, $rS, $rB", IntGeneral,
725 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
726 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
727 "xor $rA, $rS, $rB", IntGeneral,
728 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
729 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
730 "slw $rA, $rS, $rB", IntGeneral,
731 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
732 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
733 "srw $rA, $rS, $rB", IntGeneral,
734 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
735 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
736 "sraw $rA, $rS, $rB", IntShift,
737 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
740 let PPC970_Unit = 1 in { // FXU Operations.
741 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
742 "srawi $rA, $rS, $SH", IntShift,
743 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
744 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
745 "cntlzw $rA, $rS", IntGeneral,
746 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
747 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
748 "extsb $rA, $rS", IntGeneral,
749 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
750 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
751 "extsh $rA, $rS", IntGeneral,
752 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
754 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
755 "cmpw $crD, $rA, $rB", IntCompare>;
756 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
757 "cmplw $crD, $rA, $rB", IntCompare>;
759 let PPC970_Unit = 3 in { // FPU Operations.
760 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
761 // "fcmpo $crD, $fA, $fB", FPCompare>;
762 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
763 "fcmpu $crD, $fA, $fB", FPCompare>;
764 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
765 "fcmpu $crD, $fA, $fB", FPCompare>;
767 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
768 "fctiwz $frD, $frB", FPGeneral,
769 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
770 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
771 "frsp $frD, $frB", FPGeneral,
772 [(set F4RC:$frD, (fround F8RC:$frB))]>;
773 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
774 "fsqrt $frD, $frB", FPSqrt,
775 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
776 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
777 "fsqrts $frD, $frB", FPSqrt,
778 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
781 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
783 /// Note that these are defined as pseudo-ops on the PPC970 because they are
784 /// often coalesced away and we don't want the dispatch group builder to think
785 /// that they will fill slots (which could cause the load of a LSU reject to
786 /// sneak into a d-group with a store).
787 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
788 "fmr $frD, $frB", FPGeneral,
789 []>, // (set F4RC:$frD, F4RC:$frB)
791 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
792 "fmr $frD, $frB", FPGeneral,
793 []>, // (set F8RC:$frD, F8RC:$frB)
795 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
796 "fmr $frD, $frB", FPGeneral,
797 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
800 let PPC970_Unit = 3 in { // FPU Operations.
801 // These are artificially split into two different forms, for 4/8 byte FP.
802 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
803 "fabs $frD, $frB", FPGeneral,
804 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
805 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
806 "fabs $frD, $frB", FPGeneral,
807 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
808 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
809 "fnabs $frD, $frB", FPGeneral,
810 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
811 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
812 "fnabs $frD, $frB", FPGeneral,
813 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
814 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
815 "fneg $frD, $frB", FPGeneral,
816 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
817 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
818 "fneg $frD, $frB", FPGeneral,
819 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
823 // XL-Form instructions. condition register logical ops.
825 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
826 "mcrf $BF, $BFA", BrMCR>,
827 PPC970_DGroup_First, PPC970_Unit_CRU;
829 def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB),
830 "creqv $CRD, $CRA, $CRB", BrCR,
833 def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins),
834 "creqv $dst, $dst, $dst", BrCR,
837 // XFX-Form instructions. Instructions that deal with SPRs.
839 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
840 "mfctr $rT", SprMFSPR>,
841 PPC970_DGroup_First, PPC970_Unit_FXU;
842 let Pattern = [(PPCmtctr GPRC:$rS)] in {
843 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
844 "mtctr $rS", SprMTSPR>,
845 PPC970_DGroup_First, PPC970_Unit_FXU;
848 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
849 "mtlr $rS", SprMTSPR>,
850 PPC970_DGroup_First, PPC970_Unit_FXU;
851 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
852 "mflr $rT", SprMFSPR>,
853 PPC970_DGroup_First, PPC970_Unit_FXU;
855 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
856 // a GPR on the PPC970. As such, copies in and out have the same performance
857 // characteristics as an OR instruction.
858 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
859 "mtspr 256, $rS", IntGeneral>,
860 PPC970_DGroup_Single, PPC970_Unit_FXU;
861 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
862 "mfspr $rT, 256", IntGeneral>,
863 PPC970_DGroup_First, PPC970_Unit_FXU;
865 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
866 "mtcrf $FXM, $rS", BrMCRX>,
867 PPC970_MicroCode, PPC970_Unit_CRU;
868 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
869 PPC970_MicroCode, PPC970_Unit_CRU;
870 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
871 "mfcr $rT, $FXM", SprMFCR>,
872 PPC970_DGroup_First, PPC970_Unit_CRU;
874 let PPC970_Unit = 1 in { // FXU Operations.
876 // XO-Form instructions. Arithmetic instructions that can set overflow bit
878 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
879 "add $rT, $rA, $rB", IntGeneral,
880 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
881 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
882 "addc $rT, $rA, $rB", IntGeneral,
883 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
884 PPC970_DGroup_Cracked;
885 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
886 "adde $rT, $rA, $rB", IntGeneral,
887 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
888 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
889 "divw $rT, $rA, $rB", IntDivW,
890 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
891 PPC970_DGroup_First, PPC970_DGroup_Cracked;
892 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
893 "divwu $rT, $rA, $rB", IntDivW,
894 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
895 PPC970_DGroup_First, PPC970_DGroup_Cracked;
896 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
897 "mulhw $rT, $rA, $rB", IntMulHW,
898 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
899 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
900 "mulhwu $rT, $rA, $rB", IntMulHWU,
901 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
902 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
903 "mullw $rT, $rA, $rB", IntMulHW,
904 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
905 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
906 "subf $rT, $rA, $rB", IntGeneral,
907 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
908 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
909 "subfc $rT, $rA, $rB", IntGeneral,
910 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
911 PPC970_DGroup_Cracked;
912 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
913 "subfe $rT, $rA, $rB", IntGeneral,
914 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
915 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
916 "addme $rT, $rA", IntGeneral,
917 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
918 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
919 "addze $rT, $rA", IntGeneral,
920 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
921 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
922 "neg $rT, $rA", IntGeneral,
923 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
924 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
925 "subfme $rT, $rA", IntGeneral,
926 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
927 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
928 "subfze $rT, $rA", IntGeneral,
929 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
932 // A-Form instructions. Most of the instructions executed in the FPU are of
935 let PPC970_Unit = 3 in { // FPU Operations.
936 def FMADD : AForm_1<63, 29,
937 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
938 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
939 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
941 Requires<[FPContractions]>;
942 def FMADDS : AForm_1<59, 29,
943 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
944 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
945 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
947 Requires<[FPContractions]>;
948 def FMSUB : AForm_1<63, 28,
949 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
950 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
951 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
953 Requires<[FPContractions]>;
954 def FMSUBS : AForm_1<59, 28,
955 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
956 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
957 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
959 Requires<[FPContractions]>;
960 def FNMADD : AForm_1<63, 31,
961 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
962 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
963 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
965 Requires<[FPContractions]>;
966 def FNMADDS : AForm_1<59, 31,
967 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
968 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
969 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
971 Requires<[FPContractions]>;
972 def FNMSUB : AForm_1<63, 30,
973 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
974 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
975 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
977 Requires<[FPContractions]>;
978 def FNMSUBS : AForm_1<59, 30,
979 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
980 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
981 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
983 Requires<[FPContractions]>;
984 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
985 // having 4 of these, force the comparison to always be an 8-byte double (code
986 // should use an FMRSD if the input comparison value really wants to be a float)
987 // and 4/8 byte forms for the result and operand type..
988 def FSELD : AForm_1<63, 23,
989 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
990 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
991 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
992 def FSELS : AForm_1<63, 23,
993 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
994 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
995 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
996 def FADD : AForm_2<63, 21,
997 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
998 "fadd $FRT, $FRA, $FRB", FPGeneral,
999 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1000 def FADDS : AForm_2<59, 21,
1001 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1002 "fadds $FRT, $FRA, $FRB", FPGeneral,
1003 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1004 def FDIV : AForm_2<63, 18,
1005 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1006 "fdiv $FRT, $FRA, $FRB", FPDivD,
1007 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1008 def FDIVS : AForm_2<59, 18,
1009 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1010 "fdivs $FRT, $FRA, $FRB", FPDivS,
1011 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1012 def FMUL : AForm_3<63, 25,
1013 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1014 "fmul $FRT, $FRA, $FRB", FPFused,
1015 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1016 def FMULS : AForm_3<59, 25,
1017 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1018 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1019 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1020 def FSUB : AForm_2<63, 20,
1021 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1022 "fsub $FRT, $FRA, $FRB", FPGeneral,
1023 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1024 def FSUBS : AForm_2<59, 20,
1025 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1026 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1027 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1030 let PPC970_Unit = 1 in { // FXU Operations.
1031 // M-Form instructions. rotate and mask instructions.
1033 let isCommutable = 1 in {
1034 // RLWIMI can be commuted if the rotate amount is zero.
1035 def RLWIMI : MForm_2<20,
1036 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1037 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1038 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1041 def RLWINM : MForm_2<21,
1042 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1043 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1045 def RLWINMo : MForm_2<21,
1046 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1047 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1048 []>, isDOT, PPC970_DGroup_Cracked;
1049 def RLWNM : MForm_2<23,
1050 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1051 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1056 //===----------------------------------------------------------------------===//
1057 // DWARF Pseudo Instructions
1060 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1061 "${:comment} .loc $file, $line, $col",
1062 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1065 //===----------------------------------------------------------------------===//
1066 // PowerPC Instruction Patterns
1069 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1070 def : Pat<(i32 imm:$imm),
1071 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1073 // Implement the 'not' operation with the NOR instruction.
1074 def NOT : Pat<(not GPRC:$in),
1075 (NOR GPRC:$in, GPRC:$in)>;
1077 // ADD an arbitrary immediate.
1078 def : Pat<(add GPRC:$in, imm:$imm),
1079 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1080 // OR an arbitrary immediate.
1081 def : Pat<(or GPRC:$in, imm:$imm),
1082 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1083 // XOR an arbitrary immediate.
1084 def : Pat<(xor GPRC:$in, imm:$imm),
1085 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1087 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1088 (SUBFIC GPRC:$in, imm:$imm)>;
1091 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1092 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1093 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1094 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1097 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1098 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1099 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1100 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1103 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1104 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1107 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1108 (BL_Macho tglobaladdr:$dst)>;
1109 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1110 (BL_Macho texternalsym:$dst)>;
1111 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1112 (BL_ELF tglobaladdr:$dst)>;
1113 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1114 (BL_ELF texternalsym:$dst)>;
1116 // Hi and Lo for Darwin Global Addresses.
1117 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1118 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1119 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1120 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1121 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1122 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1123 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1124 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1125 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1126 (ADDIS GPRC:$in, tconstpool:$g)>;
1127 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1128 (ADDIS GPRC:$in, tjumptable:$g)>;
1130 // Fused negative multiply subtract, alternate pattern
1131 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1132 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1133 Requires<[FPContractions]>;
1134 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1135 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1136 Requires<[FPContractions]>;
1138 // Standard shifts. These are represented separately from the real shifts above
1139 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1141 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1142 (SRAW GPRC:$rS, GPRC:$rB)>;
1143 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1144 (SRW GPRC:$rS, GPRC:$rB)>;
1145 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1146 (SLW GPRC:$rS, GPRC:$rB)>;
1148 def : Pat<(zextloadi1 iaddr:$src),
1150 def : Pat<(zextloadi1 xaddr:$src),
1152 def : Pat<(extloadi1 iaddr:$src),
1154 def : Pat<(extloadi1 xaddr:$src),
1156 def : Pat<(extloadi8 iaddr:$src),
1158 def : Pat<(extloadi8 xaddr:$src),
1160 def : Pat<(extloadi16 iaddr:$src),
1162 def : Pat<(extloadi16 xaddr:$src),
1164 def : Pat<(extloadf32 iaddr:$src),
1165 (FMRSD (LFS iaddr:$src))>;
1166 def : Pat<(extloadf32 xaddr:$src),
1167 (FMRSD (LFSX xaddr:$src))>;
1169 include "PPCInstrAltivec.td"
1170 include "PPCInstr64Bit.td"