1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInFlag, SDNPOutFlag]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInFlag, SDNPOutFlag]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInFlag, SDNPOutFlag]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutFlag]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
115 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
116 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
117 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInFlag, SDNPOutFlag]>;
118 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
119 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
120 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
121 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
122 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
123 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
124 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
126 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
129 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
130 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
132 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
133 [SDNPHasChain, SDNPOptInFlag]>;
135 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
136 [SDNPHasChain, SDNPOptInFlag]>;
138 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
139 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
141 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
142 [SDNPHasChain, SDNPOptInFlag]>;
144 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
145 [SDNPHasChain, SDNPMayLoad]>;
146 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
147 [SDNPHasChain, SDNPMayStore]>;
149 // Instructions to support atomic operations
150 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
151 [SDNPHasChain, SDNPMayLoad]>;
152 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
153 [SDNPHasChain, SDNPMayStore]>;
155 // Instructions to support dynamic alloca.
156 def SDTDynOp : SDTypeProfile<1, 2, []>;
157 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
159 //===----------------------------------------------------------------------===//
160 // PowerPC specific transformation functions and pattern fragments.
163 def SHL32 : SDNodeXForm<imm, [{
164 // Transformation function: 31 - imm
165 return getI32Imm(31 - N->getZExtValue());
168 def SRL32 : SDNodeXForm<imm, [{
169 // Transformation function: 32 - imm
170 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
173 def LO16 : SDNodeXForm<imm, [{
174 // Transformation function: get the low 16 bits.
175 return getI32Imm((unsigned short)N->getZExtValue());
178 def HI16 : SDNodeXForm<imm, [{
179 // Transformation function: shift the immediate value down into the low bits.
180 return getI32Imm((unsigned)N->getZExtValue() >> 16);
183 def HA16 : SDNodeXForm<imm, [{
184 // Transformation function: shift the immediate value down into the low bits.
185 signed int Val = N->getZExtValue();
186 return getI32Imm((Val - (signed short)Val) >> 16);
188 def MB : SDNodeXForm<imm, [{
189 // Transformation function: get the start bit of a mask
191 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
192 return getI32Imm(mb);
195 def ME : SDNodeXForm<imm, [{
196 // Transformation function: get the end bit of a mask
198 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
199 return getI32Imm(me);
201 def maskimm32 : PatLeaf<(imm), [{
202 // maskImm predicate - True if immediate is a run of ones.
204 if (N->getValueType(0) == MVT::i32)
205 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
210 def immSExt16 : PatLeaf<(imm), [{
211 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
212 // field. Used by instructions like 'addi'.
213 if (N->getValueType(0) == MVT::i32)
214 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
216 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
218 def immZExt16 : PatLeaf<(imm), [{
219 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
220 // field. Used by instructions like 'ori'.
221 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
224 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
225 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
226 // identical in 32-bit mode, but in 64-bit mode, they return true if the
227 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
229 def imm16ShiftedZExt : PatLeaf<(imm), [{
230 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
231 // immediate are set. Used by instructions like 'xoris'.
232 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
235 def imm16ShiftedSExt : PatLeaf<(imm), [{
236 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
237 // immediate are set. Used by instructions like 'addis'. Identical to
238 // imm16ShiftedZExt in 32-bit mode.
239 if (N->getZExtValue() & 0xFFFF) return false;
240 if (N->getValueType(0) == MVT::i32)
242 // For 64-bit, make sure it is sext right.
243 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
247 //===----------------------------------------------------------------------===//
248 // PowerPC Flag Definitions.
250 class isPPC64 { bit PPC64 = 1; }
252 list<Register> Defs = [CR0];
256 class RegConstraint<string C> {
257 string Constraints = C;
259 class NoEncode<string E> {
260 string DisableEncoding = E;
264 //===----------------------------------------------------------------------===//
265 // PowerPC Operand Definitions.
267 def s5imm : Operand<i32> {
268 let PrintMethod = "printS5ImmOperand";
270 def u5imm : Operand<i32> {
271 let PrintMethod = "printU5ImmOperand";
273 def u6imm : Operand<i32> {
274 let PrintMethod = "printU6ImmOperand";
276 def s16imm : Operand<i32> {
277 let PrintMethod = "printS16ImmOperand";
279 def u16imm : Operand<i32> {
280 let PrintMethod = "printU16ImmOperand";
282 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
283 let PrintMethod = "printS16X4ImmOperand";
285 def target : Operand<OtherVT> {
286 let PrintMethod = "printBranchOperand";
288 def calltarget : Operand<iPTR> {
289 let PrintMethod = "printCallOperand";
291 def aaddr : Operand<iPTR> {
292 let PrintMethod = "printAbsAddrOperand";
294 def piclabel: Operand<iPTR> {
295 let PrintMethod = "printPICLabel";
297 def symbolHi: Operand<i32> {
298 let PrintMethod = "printSymbolHi";
300 def symbolLo: Operand<i32> {
301 let PrintMethod = "printSymbolLo";
303 def crbitm: Operand<i8> {
304 let PrintMethod = "printcrbitm";
307 def memri : Operand<iPTR> {
308 let PrintMethod = "printMemRegImm";
309 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
311 def memrr : Operand<iPTR> {
312 let PrintMethod = "printMemRegReg";
313 let MIOperandInfo = (ops ptr_rc, ptr_rc);
315 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
316 let PrintMethod = "printMemRegImmShifted";
317 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
319 def tocentry : Operand<iPTR> {
320 let PrintMethod = "printTOCEntryLabel";
321 let MIOperandInfo = (ops i32imm:$imm);
324 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
325 // that doesn't matter.
326 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
327 (ops (i32 20), (i32 zero_reg))> {
328 let PrintMethod = "printPredicateOperand";
331 // Define PowerPC specific addressing mode.
332 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
333 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
334 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
335 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
337 /// This is just the offset part of iaddr, used for preinc.
338 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
340 //===----------------------------------------------------------------------===//
341 // PowerPC Instruction Predicate Definitions.
342 def FPContractions : Predicate<"!NoExcessFPPrecision">;
343 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
344 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
347 //===----------------------------------------------------------------------===//
348 // PowerPC Instruction Definitions.
350 // Pseudo-instructions:
352 let hasCtrlDep = 1 in {
353 let Defs = [R1], Uses = [R1] in {
354 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
355 "${:comment} ADJCALLSTACKDOWN",
356 [(callseq_start timm:$amt)]>;
357 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
358 "${:comment} ADJCALLSTACKUP",
359 [(callseq_end timm:$amt1, timm:$amt2)]>;
362 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
363 "UPDATE_VRSAVE $rD, $rS", []>;
366 let Defs = [R1], Uses = [R1] in
367 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
368 "${:comment} DYNALLOC $result, $negsize, $fpsi",
370 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
372 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
373 // instruction selection into a branch sequence.
374 let usesCustomInserter = 1, // Expanded after instruction selection.
375 PPC970_Single = 1 in {
376 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
377 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
379 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
380 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
382 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
383 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
385 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
386 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
388 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
389 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
393 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
394 // scavenge a register for it.
395 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
396 "${:comment} SPILL_CR $cond $F", []>;
398 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
399 let isReturn = 1, Uses = [LR, RM] in
400 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
401 "b${p:cc}lr ${p:reg}", BrB,
403 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
404 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
408 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
411 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
412 let isBarrier = 1 in {
413 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
418 // BCC represents an arbitrary conditional branch on a predicate.
419 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
420 // a two-value operand where a dag node expects two operands. :(
421 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
422 "b${cond:cc} ${cond:reg}, $dst"
423 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
427 let isCall = 1, PPC970_Unit = 7,
428 // All calls clobber the non-callee saved registers...
429 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
430 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
431 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
434 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
435 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in {
436 // Convenient aliases for call instructions
438 def BL_Darwin : IForm<18, 0, 1,
439 (outs), (ins calltarget:$func, variable_ops),
440 "bl $func", BrB, []>; // See Pat patterns below.
441 def BLA_Darwin : IForm<18, 1, 1,
442 (outs), (ins aaddr:$func, variable_ops),
443 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
445 let Uses = [CTR, RM] in {
446 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
447 (outs), (ins variable_ops),
449 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
454 let isCall = 1, PPC970_Unit = 7,
455 // All calls clobber the non-callee saved registers...
456 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
457 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
458 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
461 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
462 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN,CARRY] in {
463 // Convenient aliases for call instructions
465 def BL_SVR4 : IForm<18, 0, 1,
466 (outs), (ins calltarget:$func, variable_ops),
467 "bl $func", BrB, []>; // See Pat patterns below.
468 def BLA_SVR4 : IForm<18, 1, 1,
469 (outs), (ins aaddr:$func, variable_ops),
471 [(PPCcall_SVR4 (i32 imm:$func))]>;
473 let Uses = [CTR, RM] in {
474 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
475 (outs), (ins variable_ops),
477 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
482 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
483 def TCRETURNdi :Pseudo< (outs),
484 (ins calltarget:$dst, i32imm:$offset, variable_ops),
485 "#TC_RETURNd $dst $offset",
489 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
490 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
491 "#TC_RETURNa $func $offset",
492 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
494 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
495 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops),
496 "#TC_RETURNr $dst $offset",
500 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
501 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
502 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
503 Requires<[In32BitMode]>;
507 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
508 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
509 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
514 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
515 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
516 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
521 // DCB* instructions.
522 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
523 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
524 PPC970_DGroup_Single;
525 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
526 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
527 PPC970_DGroup_Single;
528 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
529 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
530 PPC970_DGroup_Single;
531 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
532 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
533 PPC970_DGroup_Single;
534 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
535 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
536 PPC970_DGroup_Single;
537 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
538 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
539 PPC970_DGroup_Single;
540 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
541 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
542 PPC970_DGroup_Single;
543 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
544 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
545 PPC970_DGroup_Single;
548 let usesCustomInserter = 1 in {
549 let Uses = [CR0] in {
550 def ATOMIC_LOAD_ADD_I8 : Pseudo<
551 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
552 "${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
553 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
554 def ATOMIC_LOAD_SUB_I8 : Pseudo<
555 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
556 "${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
557 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
558 def ATOMIC_LOAD_AND_I8 : Pseudo<
559 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
560 "${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
561 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
562 def ATOMIC_LOAD_OR_I8 : Pseudo<
563 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
564 "${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
565 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
566 def ATOMIC_LOAD_XOR_I8 : Pseudo<
567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
568 "${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
569 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
570 def ATOMIC_LOAD_NAND_I8 : Pseudo<
571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
572 "${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
573 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
574 def ATOMIC_LOAD_ADD_I16 : Pseudo<
575 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
576 "${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
577 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
578 def ATOMIC_LOAD_SUB_I16 : Pseudo<
579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
580 "${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
581 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_AND_I16 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
584 "${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
585 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
586 def ATOMIC_LOAD_OR_I16 : Pseudo<
587 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
588 "${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
589 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
590 def ATOMIC_LOAD_XOR_I16 : Pseudo<
591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
592 "${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
593 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_NAND_I16 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
596 "${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
597 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
598 def ATOMIC_LOAD_ADD_I32 : Pseudo<
599 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
600 "${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
601 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
602 def ATOMIC_LOAD_SUB_I32 : Pseudo<
603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
604 "${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
605 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_LOAD_AND_I32 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
608 "${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
609 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
610 def ATOMIC_LOAD_OR_I32 : Pseudo<
611 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
612 "${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
613 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
614 def ATOMIC_LOAD_XOR_I32 : Pseudo<
615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
616 "${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
617 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
618 def ATOMIC_LOAD_NAND_I32 : Pseudo<
619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr),
620 "${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
621 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
623 def ATOMIC_CMP_SWAP_I8 : Pseudo<
624 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
625 "${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
627 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
628 def ATOMIC_CMP_SWAP_I16 : Pseudo<
629 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
630 "${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
632 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
633 def ATOMIC_CMP_SWAP_I32 : Pseudo<
634 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new),
635 "${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
637 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
639 def ATOMIC_SWAP_I8 : Pseudo<
640 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
641 "${:comment} ATOMIC_SWAP_I8 PSEUDO!",
642 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
643 def ATOMIC_SWAP_I16 : Pseudo<
644 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
645 "${:comment} ATOMIC_SWAP_I16 PSEUDO!",
646 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
647 def ATOMIC_SWAP_I32 : Pseudo<
648 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new),
649 "${:comment} ATOMIC_SWAP_I32 PSEUDO!",
650 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
654 // Instructions to support atomic operations
655 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
656 "lwarx $rD, $src", LdStLWARX,
657 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
660 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
661 "stwcx. $rS, $dst", LdStSTWCX,
662 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
665 let isBarrier = 1, hasCtrlDep = 1 in
666 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>;
668 //===----------------------------------------------------------------------===//
669 // PPC32 Load Instructions.
672 // Unindexed (r+i) Loads.
673 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
674 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
675 "lbz $rD, $src", LdStGeneral,
676 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
677 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
678 "lha $rD, $src", LdStLHA,
679 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
680 PPC970_DGroup_Cracked;
681 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
682 "lhz $rD, $src", LdStGeneral,
683 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
684 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
685 "lwz $rD, $src", LdStGeneral,
686 [(set GPRC:$rD, (load iaddr:$src))]>;
688 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
689 "lfs $rD, $src", LdStLFDU,
690 [(set F4RC:$rD, (load iaddr:$src))]>;
691 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
692 "lfd $rD, $src", LdStLFD,
693 [(set F8RC:$rD, (load iaddr:$src))]>;
696 // Unindexed (r+i) Loads with Update (preinc).
698 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
699 "lbzu $rD, $addr", LdStGeneral,
700 []>, RegConstraint<"$addr.reg = $ea_result">,
701 NoEncode<"$ea_result">;
703 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
704 "lhau $rD, $addr", LdStGeneral,
705 []>, RegConstraint<"$addr.reg = $ea_result">,
706 NoEncode<"$ea_result">;
708 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
709 "lhzu $rD, $addr", LdStGeneral,
710 []>, RegConstraint<"$addr.reg = $ea_result">,
711 NoEncode<"$ea_result">;
713 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
714 "lwzu $rD, $addr", LdStGeneral,
715 []>, RegConstraint<"$addr.reg = $ea_result">,
716 NoEncode<"$ea_result">;
718 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
719 "lfs $rD, $addr", LdStLFDU,
720 []>, RegConstraint<"$addr.reg = $ea_result">,
721 NoEncode<"$ea_result">;
723 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
724 "lfd $rD, $addr", LdStLFD,
725 []>, RegConstraint<"$addr.reg = $ea_result">,
726 NoEncode<"$ea_result">;
730 // Indexed (r+r) Loads.
732 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
733 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
734 "lbzx $rD, $src", LdStGeneral,
735 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
736 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
737 "lhax $rD, $src", LdStLHA,
738 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
739 PPC970_DGroup_Cracked;
740 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
741 "lhzx $rD, $src", LdStGeneral,
742 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
743 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
744 "lwzx $rD, $src", LdStGeneral,
745 [(set GPRC:$rD, (load xaddr:$src))]>;
748 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
749 "lhbrx $rD, $src", LdStGeneral,
750 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
751 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
752 "lwbrx $rD, $src", LdStGeneral,
753 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
755 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
756 "lfsx $frD, $src", LdStLFDU,
757 [(set F4RC:$frD, (load xaddr:$src))]>;
758 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
759 "lfdx $frD, $src", LdStLFDU,
760 [(set F8RC:$frD, (load xaddr:$src))]>;
763 //===----------------------------------------------------------------------===//
764 // PPC32 Store Instructions.
767 // Unindexed (r+i) Stores.
768 let PPC970_Unit = 2 in {
769 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
770 "stb $rS, $src", LdStGeneral,
771 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
772 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
773 "sth $rS, $src", LdStGeneral,
774 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
775 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
776 "stw $rS, $src", LdStGeneral,
777 [(store GPRC:$rS, iaddr:$src)]>;
778 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
779 "stfs $rS, $dst", LdStUX,
780 [(store F4RC:$rS, iaddr:$dst)]>;
781 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
782 "stfd $rS, $dst", LdStUX,
783 [(store F8RC:$rS, iaddr:$dst)]>;
786 // Unindexed (r+i) Stores with Update (preinc).
787 let PPC970_Unit = 2 in {
788 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
789 symbolLo:$ptroff, ptr_rc:$ptrreg),
790 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
791 [(set ptr_rc:$ea_res,
792 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
793 iaddroff:$ptroff))]>,
794 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
795 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
796 symbolLo:$ptroff, ptr_rc:$ptrreg),
797 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
798 [(set ptr_rc:$ea_res,
799 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
800 iaddroff:$ptroff))]>,
801 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
802 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
803 symbolLo:$ptroff, ptr_rc:$ptrreg),
804 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
805 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
806 iaddroff:$ptroff))]>,
807 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
808 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
809 symbolLo:$ptroff, ptr_rc:$ptrreg),
810 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
811 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
812 iaddroff:$ptroff))]>,
813 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
814 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
815 symbolLo:$ptroff, ptr_rc:$ptrreg),
816 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
817 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
818 iaddroff:$ptroff))]>,
819 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
823 // Indexed (r+r) Stores.
825 let PPC970_Unit = 2 in {
826 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
827 "stbx $rS, $dst", LdStGeneral,
828 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
829 PPC970_DGroup_Cracked;
830 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
831 "sthx $rS, $dst", LdStGeneral,
832 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
833 PPC970_DGroup_Cracked;
834 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
835 "stwx $rS, $dst", LdStGeneral,
836 [(store GPRC:$rS, xaddr:$dst)]>,
837 PPC970_DGroup_Cracked;
839 let mayStore = 1 in {
840 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
841 "stwux $rS, $rA, $rB", LdStGeneral,
844 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
845 "sthbrx $rS, $dst", LdStGeneral,
846 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
847 PPC970_DGroup_Cracked;
848 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
849 "stwbrx $rS, $dst", LdStGeneral,
850 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
851 PPC970_DGroup_Cracked;
853 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
854 "stfiwx $frS, $dst", LdStUX,
855 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
857 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
858 "stfsx $frS, $dst", LdStUX,
859 [(store F4RC:$frS, xaddr:$dst)]>;
860 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
861 "stfdx $frS, $dst", LdStUX,
862 [(store F8RC:$frS, xaddr:$dst)]>;
866 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
870 //===----------------------------------------------------------------------===//
871 // PPC32 Arithmetic Instructions.
874 let PPC970_Unit = 1 in { // FXU Operations.
875 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
876 "addi $rD, $rA, $imm", IntGeneral,
877 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
878 let Defs = [CARRY] in {
879 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
880 "addic $rD, $rA, $imm", IntGeneral,
881 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
882 PPC970_DGroup_Cracked;
883 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
884 "addic. $rD, $rA, $imm", IntGeneral,
887 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
888 "addis $rD, $rA, $imm", IntGeneral,
889 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
890 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
891 "la $rD, $sym($rA)", IntGeneral,
892 [(set GPRC:$rD, (add GPRC:$rA,
893 (PPClo tglobaladdr:$sym, 0)))]>;
894 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
895 "mulli $rD, $rA, $imm", IntMulLI,
896 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
897 let Defs = [CARRY] in {
898 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
899 "subfic $rD, $rA, $imm", IntGeneral,
900 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
903 let isReMaterializable = 1 in {
904 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
905 "li $rD, $imm", IntGeneral,
906 [(set GPRC:$rD, immSExt16:$imm)]>;
907 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
908 "lis $rD, $imm", IntGeneral,
909 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
913 let PPC970_Unit = 1 in { // FXU Operations.
914 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
915 "andi. $dst, $src1, $src2", IntGeneral,
916 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
918 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
919 "andis. $dst, $src1, $src2", IntGeneral,
920 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
922 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
923 "ori $dst, $src1, $src2", IntGeneral,
924 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
925 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
926 "oris $dst, $src1, $src2", IntGeneral,
927 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
928 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
929 "xori $dst, $src1, $src2", IntGeneral,
930 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
931 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
932 "xoris $dst, $src1, $src2", IntGeneral,
933 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
934 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
936 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
937 "cmpwi $crD, $rA, $imm", IntCompare>;
938 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
939 "cmplwi $dst, $src1, $src2", IntCompare>;
943 let PPC970_Unit = 1 in { // FXU Operations.
944 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
945 "nand $rA, $rS, $rB", IntGeneral,
946 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
947 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
948 "and $rA, $rS, $rB", IntGeneral,
949 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
950 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
951 "andc $rA, $rS, $rB", IntGeneral,
952 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
953 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
954 "or $rA, $rS, $rB", IntGeneral,
955 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
956 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
957 "nor $rA, $rS, $rB", IntGeneral,
958 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
959 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
960 "orc $rA, $rS, $rB", IntGeneral,
961 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
962 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
963 "eqv $rA, $rS, $rB", IntGeneral,
964 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
965 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
966 "xor $rA, $rS, $rB", IntGeneral,
967 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
968 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
969 "slw $rA, $rS, $rB", IntGeneral,
970 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
971 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
972 "srw $rA, $rS, $rB", IntGeneral,
973 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
974 let Defs = [CARRY] in {
975 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
976 "sraw $rA, $rS, $rB", IntShift,
977 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
981 let PPC970_Unit = 1 in { // FXU Operations.
982 let Defs = [CARRY] in {
983 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
984 "srawi $rA, $rS, $SH", IntShift,
985 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
987 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
988 "cntlzw $rA, $rS", IntGeneral,
989 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
990 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
991 "extsb $rA, $rS", IntGeneral,
992 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
993 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
994 "extsh $rA, $rS", IntGeneral,
995 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
997 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
998 "cmpw $crD, $rA, $rB", IntCompare>;
999 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1000 "cmplw $crD, $rA, $rB", IntCompare>;
1002 let PPC970_Unit = 3 in { // FPU Operations.
1003 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1004 // "fcmpo $crD, $fA, $fB", FPCompare>;
1005 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1006 "fcmpu $crD, $fA, $fB", FPCompare>;
1007 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1008 "fcmpu $crD, $fA, $fB", FPCompare>;
1010 let Uses = [RM] in {
1011 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1012 "fctiwz $frD, $frB", FPGeneral,
1013 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1014 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1015 "frsp $frD, $frB", FPGeneral,
1016 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1017 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1018 "fsqrt $frD, $frB", FPSqrt,
1019 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1020 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1021 "fsqrts $frD, $frB", FPSqrt,
1022 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1026 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
1028 /// Note that these are defined as pseudo-ops on the PPC970 because they are
1029 /// often coalesced away and we don't want the dispatch group builder to think
1030 /// that they will fill slots (which could cause the load of a LSU reject to
1031 /// sneak into a d-group with a store).
1032 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1033 "fmr $frD, $frB", FPGeneral,
1034 []>, // (set F4RC:$frD, F4RC:$frB)
1036 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
1037 "fmr $frD, $frB", FPGeneral,
1038 []>, // (set F8RC:$frD, F8RC:$frB)
1040 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
1041 "fmr $frD, $frB", FPGeneral,
1042 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
1045 let PPC970_Unit = 3 in { // FPU Operations.
1046 // These are artificially split into two different forms, for 4/8 byte FP.
1047 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1048 "fabs $frD, $frB", FPGeneral,
1049 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1050 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1051 "fabs $frD, $frB", FPGeneral,
1052 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1053 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1054 "fnabs $frD, $frB", FPGeneral,
1055 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1056 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1057 "fnabs $frD, $frB", FPGeneral,
1058 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1059 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1060 "fneg $frD, $frB", FPGeneral,
1061 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1062 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1063 "fneg $frD, $frB", FPGeneral,
1064 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1068 // XL-Form instructions. condition register logical ops.
1070 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1071 "mcrf $BF, $BFA", BrMCR>,
1072 PPC970_DGroup_First, PPC970_Unit_CRU;
1074 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1075 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1076 "creqv $CRD, $CRA, $CRB", BrCR,
1079 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1080 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1081 "cror $CRD, $CRA, $CRB", BrCR,
1084 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1085 "creqv $dst, $dst, $dst", BrCR,
1088 // XFX-Form instructions. Instructions that deal with SPRs.
1090 let Uses = [CTR] in {
1091 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1092 "mfctr $rT", SprMFSPR>,
1093 PPC970_DGroup_First, PPC970_Unit_FXU;
1095 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1096 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1097 "mtctr $rS", SprMTSPR>,
1098 PPC970_DGroup_First, PPC970_Unit_FXU;
1101 let Defs = [LR] in {
1102 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1103 "mtlr $rS", SprMTSPR>,
1104 PPC970_DGroup_First, PPC970_Unit_FXU;
1106 let Uses = [LR] in {
1107 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1108 "mflr $rT", SprMFSPR>,
1109 PPC970_DGroup_First, PPC970_Unit_FXU;
1112 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1113 // a GPR on the PPC970. As such, copies in and out have the same performance
1114 // characteristics as an OR instruction.
1115 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1116 "mtspr 256, $rS", IntGeneral>,
1117 PPC970_DGroup_Single, PPC970_Unit_FXU;
1118 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1119 "mfspr $rT, 256", IntGeneral>,
1120 PPC970_DGroup_First, PPC970_Unit_FXU;
1122 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
1123 "mtcrf $FXM, $rS", BrMCRX>,
1124 PPC970_MicroCode, PPC970_Unit_CRU;
1125 // FIXME: this Uses all the CR registers. Marking it as such is
1126 // necessary for DeadMachineInstructionElim to do the right thing.
1127 // However, marking it also exposes PR 2964, and causes crashes in
1128 // the Local RA because it doesn't like this sequence:
1130 // MFCR <kill of whatever preg got assigned to vreg>
1131 // For now DeadMachineInstructionElim is turned off, so don't do the marking.
1132 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
1133 PPC970_MicroCode, PPC970_Unit_CRU;
1134 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1135 "mfcr $rT, $FXM", SprMFCR>,
1136 PPC970_DGroup_First, PPC970_Unit_CRU;
1138 // Instructions to manipulate FPSCR. Only long double handling uses these.
1139 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1141 let Uses = [RM], Defs = [RM] in {
1142 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1143 "mtfsb0 $FM", IntMTFSB0,
1144 [(PPCmtfsb0 (i32 imm:$FM))]>,
1145 PPC970_DGroup_Single, PPC970_Unit_FPU;
1146 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1147 "mtfsb1 $FM", IntMTFSB0,
1148 [(PPCmtfsb1 (i32 imm:$FM))]>,
1149 PPC970_DGroup_Single, PPC970_Unit_FPU;
1150 // MTFSF does not actually produce an FP result. We pretend it copies
1151 // input reg B to the output. If we didn't do this it would look like the
1152 // instruction had no outputs (because we aren't modelling the FPSCR) and
1153 // it would be deleted.
1154 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1155 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1156 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1157 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1158 F8RC:$rT, F8RC:$FRB))]>,
1159 PPC970_DGroup_Single, PPC970_Unit_FPU;
1161 let Uses = [RM] in {
1162 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1163 "mffs $rT", IntMFFS,
1164 [(set F8RC:$rT, (PPCmffs))]>,
1165 PPC970_DGroup_Single, PPC970_Unit_FPU;
1166 def FADDrtz: AForm_2<63, 21,
1167 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1168 "fadd $FRT, $FRA, $FRB", FPGeneral,
1169 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1170 PPC970_DGroup_Single, PPC970_Unit_FPU;
1174 let PPC970_Unit = 1 in { // FXU Operations.
1176 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1178 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1179 "add $rT, $rA, $rB", IntGeneral,
1180 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1181 let Defs = [CARRY] in {
1182 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1183 "addc $rT, $rA, $rB", IntGeneral,
1184 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1185 PPC970_DGroup_Cracked;
1187 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1188 "divw $rT, $rA, $rB", IntDivW,
1189 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1190 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1191 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1192 "divwu $rT, $rA, $rB", IntDivW,
1193 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1194 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1195 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1196 "mulhw $rT, $rA, $rB", IntMulHW,
1197 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1198 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1199 "mulhwu $rT, $rA, $rB", IntMulHWU,
1200 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1201 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1202 "mullw $rT, $rA, $rB", IntMulHW,
1203 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1204 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1205 "subf $rT, $rA, $rB", IntGeneral,
1206 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1207 let Defs = [CARRY] in {
1208 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1209 "subfc $rT, $rA, $rB", IntGeneral,
1210 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1211 PPC970_DGroup_Cracked;
1213 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1214 "neg $rT, $rA", IntGeneral,
1215 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1216 let Uses = [CARRY], Defs = [CARRY] in {
1217 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1218 "adde $rT, $rA, $rB", IntGeneral,
1219 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1220 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1221 "addme $rT, $rA", IntGeneral,
1222 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
1223 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1224 "addze $rT, $rA", IntGeneral,
1225 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1226 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1227 "subfe $rT, $rA, $rB", IntGeneral,
1228 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1229 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1230 "subfme $rT, $rA", IntGeneral,
1231 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
1232 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1233 "subfze $rT, $rA", IntGeneral,
1234 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1238 // A-Form instructions. Most of the instructions executed in the FPU are of
1241 let PPC970_Unit = 3 in { // FPU Operations.
1242 let Uses = [RM] in {
1243 def FMADD : AForm_1<63, 29,
1244 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1245 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1246 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1248 Requires<[FPContractions]>;
1249 def FMADDS : AForm_1<59, 29,
1250 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1251 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1252 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1254 Requires<[FPContractions]>;
1255 def FMSUB : AForm_1<63, 28,
1256 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1257 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1258 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1260 Requires<[FPContractions]>;
1261 def FMSUBS : AForm_1<59, 28,
1262 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1263 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1264 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1266 Requires<[FPContractions]>;
1267 def FNMADD : AForm_1<63, 31,
1268 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1269 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1270 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1272 Requires<[FPContractions]>;
1273 def FNMADDS : AForm_1<59, 31,
1274 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1275 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1276 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1278 Requires<[FPContractions]>;
1279 def FNMSUB : AForm_1<63, 30,
1280 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1281 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1282 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1284 Requires<[FPContractions]>;
1285 def FNMSUBS : AForm_1<59, 30,
1286 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1287 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1288 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1290 Requires<[FPContractions]>;
1292 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1293 // having 4 of these, force the comparison to always be an 8-byte double (code
1294 // should use an FMRSD if the input comparison value really wants to be a float)
1295 // and 4/8 byte forms for the result and operand type..
1296 def FSELD : AForm_1<63, 23,
1297 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1298 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1299 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1300 def FSELS : AForm_1<63, 23,
1301 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1302 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1303 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1304 let Uses = [RM] in {
1305 def FADD : AForm_2<63, 21,
1306 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1307 "fadd $FRT, $FRA, $FRB", FPGeneral,
1308 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1309 def FADDS : AForm_2<59, 21,
1310 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1311 "fadds $FRT, $FRA, $FRB", FPGeneral,
1312 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1313 def FDIV : AForm_2<63, 18,
1314 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1315 "fdiv $FRT, $FRA, $FRB", FPDivD,
1316 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1317 def FDIVS : AForm_2<59, 18,
1318 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1319 "fdivs $FRT, $FRA, $FRB", FPDivS,
1320 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1321 def FMUL : AForm_3<63, 25,
1322 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1323 "fmul $FRT, $FRA, $FRB", FPFused,
1324 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1325 def FMULS : AForm_3<59, 25,
1326 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1327 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1328 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1329 def FSUB : AForm_2<63, 20,
1330 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1331 "fsub $FRT, $FRA, $FRB", FPGeneral,
1332 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1333 def FSUBS : AForm_2<59, 20,
1334 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1335 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1336 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1340 let PPC970_Unit = 1 in { // FXU Operations.
1341 // M-Form instructions. rotate and mask instructions.
1343 let isCommutable = 1 in {
1344 // RLWIMI can be commuted if the rotate amount is zero.
1345 def RLWIMI : MForm_2<20,
1346 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1347 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1348 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1351 def RLWINM : MForm_2<21,
1352 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1353 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1355 def RLWINMo : MForm_2<21,
1356 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1357 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1358 []>, isDOT, PPC970_DGroup_Cracked;
1359 def RLWNM : MForm_2<23,
1360 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1361 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1366 //===----------------------------------------------------------------------===//
1367 // PowerPC Instruction Patterns
1370 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1371 def : Pat<(i32 imm:$imm),
1372 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1374 // Implement the 'not' operation with the NOR instruction.
1375 def NOT : Pat<(not GPRC:$in),
1376 (NOR GPRC:$in, GPRC:$in)>;
1378 // ADD an arbitrary immediate.
1379 def : Pat<(add GPRC:$in, imm:$imm),
1380 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1381 // OR an arbitrary immediate.
1382 def : Pat<(or GPRC:$in, imm:$imm),
1383 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1384 // XOR an arbitrary immediate.
1385 def : Pat<(xor GPRC:$in, imm:$imm),
1386 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1388 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1389 (SUBFIC GPRC:$in, imm:$imm)>;
1392 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1393 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1394 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1395 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1398 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1399 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1400 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1401 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1404 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1405 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1408 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1409 (BL_Darwin tglobaladdr:$dst)>;
1410 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1411 (BL_Darwin texternalsym:$dst)>;
1412 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1413 (BL_SVR4 tglobaladdr:$dst)>;
1414 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1415 (BL_SVR4 texternalsym:$dst)>;
1418 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1419 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1421 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1422 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1424 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1425 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1429 // Hi and Lo for Darwin Global Addresses.
1430 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1431 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1432 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1433 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1434 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1435 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1436 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1437 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1438 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1439 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1440 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1441 (ADDIS GPRC:$in, tconstpool:$g)>;
1442 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1443 (ADDIS GPRC:$in, tjumptable:$g)>;
1444 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1445 (ADDIS GPRC:$in, tblockaddress:$g)>;
1447 // Fused negative multiply subtract, alternate pattern
1448 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1449 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1450 Requires<[FPContractions]>;
1451 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1452 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1453 Requires<[FPContractions]>;
1455 // Standard shifts. These are represented separately from the real shifts above
1456 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1458 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1459 (SRAW GPRC:$rS, GPRC:$rB)>;
1460 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1461 (SRW GPRC:$rS, GPRC:$rB)>;
1462 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1463 (SLW GPRC:$rS, GPRC:$rB)>;
1465 def : Pat<(zextloadi1 iaddr:$src),
1467 def : Pat<(zextloadi1 xaddr:$src),
1469 def : Pat<(extloadi1 iaddr:$src),
1471 def : Pat<(extloadi1 xaddr:$src),
1473 def : Pat<(extloadi8 iaddr:$src),
1475 def : Pat<(extloadi8 xaddr:$src),
1477 def : Pat<(extloadi16 iaddr:$src),
1479 def : Pat<(extloadi16 xaddr:$src),
1481 def : Pat<(extloadf32 iaddr:$src),
1482 (FMRSD (LFS iaddr:$src))>;
1483 def : Pat<(extloadf32 xaddr:$src),
1484 (FMRSD (LFSX xaddr:$src))>;
1487 def : Pat<(membarrier (i32 imm:$ll),
1494 include "PPCInstrAltivec.td"
1495 include "PPCInstr64Bit.td"