1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
50 SDTCisPtrTy<0>, SDTCisVT<1, i32>
53 def tocentry32 : Operand<iPTR> {
54 let MIOperandInfo = (ops i32imm:$imm);
57 def SDT_PPCqvfperm : SDTypeProfile<1, 3, [
58 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3>
60 def SDT_PPCqvgpci : SDTypeProfile<1, 1, [
61 SDTCisVec<0>, SDTCisInt<1>
63 def SDT_PPCqvaligni : SDTypeProfile<1, 3, [
64 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3>
66 def SDT_PPCqvesplati : SDTypeProfile<1, 2, [
67 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
70 def SDT_PPCqbflt : SDTypeProfile<1, 1, [
71 SDTCisVec<0>, SDTCisVec<1>
74 def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [
75 SDTCisVec<0>, SDTCisPtrTy<1>
78 //===----------------------------------------------------------------------===//
79 // PowerPC specific DAG Nodes.
82 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
83 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
85 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
86 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
87 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
88 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
89 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
90 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
91 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
92 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
93 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
94 [SDNPHasChain, SDNPMayStore]>;
95 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
96 [SDNPHasChain, SDNPMayLoad]>;
97 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
98 [SDNPHasChain, SDNPMayLoad]>;
100 // Extract FPSCR (not modeled at the DAG level).
101 def PPCmffs : SDNode<"PPCISD::MFFS",
102 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
104 // Perform FADD in round-to-zero mode.
105 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
108 def PPCfsel : SDNode<"PPCISD::FSEL",
109 // Type constraint for fsel.
110 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
111 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
113 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
114 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
115 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp,
116 [SDNPMayLoad, SDNPMemOperand]>;
117 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
118 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
120 def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>;
122 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
123 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
125 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
126 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
127 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
128 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
129 def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR",
130 SDTypeProfile<1, 3, [
131 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
132 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
133 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
134 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
135 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
136 def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
137 SDTypeProfile<1, 3, [
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
139 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
140 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
141 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
143 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
145 def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
146 def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
147 def PPCqvaligni : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
148 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;
150 def PPCqbflt : SDNode<"PPCISD::QBFLT", SDT_PPCqbflt, []>;
152 def PPCqvlfsb : SDNode<"PPCISD::QVLFSb", SDT_PPCqvlfsb,
153 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>;
157 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
158 // amounts. These nodes are generated by the multi-precision shift code.
159 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
160 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
161 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
163 // These are target-independent nodes, but have target-specific formats.
164 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
165 [SDNPHasChain, SDNPOutGlue]>;
166 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
169 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
170 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
171 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
173 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
176 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
177 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
178 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
179 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
181 def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC",
182 SDTypeProfile<0, 1, []>,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
186 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
189 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
190 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
192 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
193 SDTypeProfile<1, 1, [SDTCisInt<0>,
195 [SDNPHasChain, SDNPSideEffect]>;
196 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
197 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
198 [SDNPHasChain, SDNPSideEffect]>;
200 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
201 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
202 [SDNPHasChain, SDNPSideEffect]>;
204 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
205 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
207 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
208 [SDNPHasChain, SDNPOptInGlue]>;
210 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
211 [SDNPHasChain, SDNPMayLoad]>;
212 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
213 [SDNPHasChain, SDNPMayStore]>;
215 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
216 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
218 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
219 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
221 // Instructions to support dynamic alloca.
222 def SDTDynOp : SDTypeProfile<1, 2, []>;
223 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
225 //===----------------------------------------------------------------------===//
226 // PowerPC specific transformation functions and pattern fragments.
229 def SHL32 : SDNodeXForm<imm, [{
230 // Transformation function: 31 - imm
231 return getI32Imm(31 - N->getZExtValue());
234 def SRL32 : SDNodeXForm<imm, [{
235 // Transformation function: 32 - imm
236 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
239 def LO16 : SDNodeXForm<imm, [{
240 // Transformation function: get the low 16 bits.
241 return getI32Imm((unsigned short)N->getZExtValue());
244 def HI16 : SDNodeXForm<imm, [{
245 // Transformation function: shift the immediate value down into the low bits.
246 return getI32Imm((unsigned)N->getZExtValue() >> 16);
249 def HA16 : SDNodeXForm<imm, [{
250 // Transformation function: shift the immediate value down into the low bits.
251 signed int Val = N->getZExtValue();
252 return getI32Imm((Val - (signed short)Val) >> 16);
254 def MB : SDNodeXForm<imm, [{
255 // Transformation function: get the start bit of a mask
257 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
258 return getI32Imm(mb);
261 def ME : SDNodeXForm<imm, [{
262 // Transformation function: get the end bit of a mask
264 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
265 return getI32Imm(me);
267 def maskimm32 : PatLeaf<(imm), [{
268 // maskImm predicate - True if immediate is a run of ones.
270 if (N->getValueType(0) == MVT::i32)
271 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
276 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{
277 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit
278 // sign extended field. Used by instructions like 'addi'.
279 return (int32_t)Imm == (short)Imm;
281 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{
282 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit
283 // sign extended field. Used by instructions like 'addi'.
284 return (int64_t)Imm == (short)Imm;
286 def immZExt16 : PatLeaf<(imm), [{
287 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
288 // field. Used by instructions like 'ori'.
289 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
292 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
293 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
294 // identical in 32-bit mode, but in 64-bit mode, they return true if the
295 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
297 def imm16ShiftedZExt : PatLeaf<(imm), [{
298 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
299 // immediate are set. Used by instructions like 'xoris'.
300 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
303 def imm16ShiftedSExt : PatLeaf<(imm), [{
304 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
305 // immediate are set. Used by instructions like 'addis'. Identical to
306 // imm16ShiftedZExt in 32-bit mode.
307 if (N->getZExtValue() & 0xFFFF) return false;
308 if (N->getValueType(0) == MVT::i32)
310 // For 64-bit, make sure it is sext right.
311 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
314 def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{
315 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit
316 // zero extended field.
317 return isUInt<32>(Imm);
320 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
321 // restricted memrix (4-aligned) constants are alignment sensitive. If these
322 // offsets are hidden behind TOC entries than the values of the lower-order
323 // bits cannot be checked directly. As a result, we need to also incorporate
324 // an alignment check into the relevant patterns.
326 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
327 return cast<LoadSDNode>(N)->getAlignment() >= 4;
329 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
330 (store node:$val, node:$ptr), [{
331 return cast<StoreSDNode>(N)->getAlignment() >= 4;
333 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
334 return cast<LoadSDNode>(N)->getAlignment() >= 4;
336 def aligned4pre_store : PatFrag<
337 (ops node:$val, node:$base, node:$offset),
338 (pre_store node:$val, node:$base, node:$offset), [{
339 return cast<StoreSDNode>(N)->getAlignment() >= 4;
342 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
343 return cast<LoadSDNode>(N)->getAlignment() < 4;
345 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
346 (store node:$val, node:$ptr), [{
347 return cast<StoreSDNode>(N)->getAlignment() < 4;
349 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
350 return cast<LoadSDNode>(N)->getAlignment() < 4;
353 //===----------------------------------------------------------------------===//
354 // PowerPC Flag Definitions.
356 class isPPC64 { bit PPC64 = 1; }
357 class isDOT { bit RC = 1; }
359 class RegConstraint<string C> {
360 string Constraints = C;
362 class NoEncode<string E> {
363 string DisableEncoding = E;
367 //===----------------------------------------------------------------------===//
368 // PowerPC Operand Definitions.
370 // In the default PowerPC assembler syntax, registers are specified simply
371 // by number, so they cannot be distinguished from immediate values (without
372 // looking at the opcode). This means that the default operand matching logic
373 // for the asm parser does not work, and we need to specify custom matchers.
374 // Since those can only be specified with RegisterOperand classes and not
375 // directly on the RegisterClass, all instructions patterns used by the asm
376 // parser need to use a RegisterOperand (instead of a RegisterClass) for
377 // all their register operands.
378 // For this purpose, we define one RegisterOperand for each RegisterClass,
379 // using the same name as the class, just in lower case.
381 def PPCRegGPRCAsmOperand : AsmOperandClass {
382 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
384 def gprc : RegisterOperand<GPRC> {
385 let ParserMatchClass = PPCRegGPRCAsmOperand;
387 def PPCRegG8RCAsmOperand : AsmOperandClass {
388 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
390 def g8rc : RegisterOperand<G8RC> {
391 let ParserMatchClass = PPCRegG8RCAsmOperand;
393 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
394 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
396 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
397 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
399 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
400 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
402 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
403 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
405 def PPCRegF8RCAsmOperand : AsmOperandClass {
406 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
408 def f8rc : RegisterOperand<F8RC> {
409 let ParserMatchClass = PPCRegF8RCAsmOperand;
411 def PPCRegF4RCAsmOperand : AsmOperandClass {
412 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
414 def f4rc : RegisterOperand<F4RC> {
415 let ParserMatchClass = PPCRegF4RCAsmOperand;
417 def PPCRegVRRCAsmOperand : AsmOperandClass {
418 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
420 def vrrc : RegisterOperand<VRRC> {
421 let ParserMatchClass = PPCRegVRRCAsmOperand;
423 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
424 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
426 def crbitrc : RegisterOperand<CRBITRC> {
427 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
429 def PPCRegCRRCAsmOperand : AsmOperandClass {
430 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
432 def crrc : RegisterOperand<CRRC> {
433 let ParserMatchClass = PPCRegCRRCAsmOperand;
435 def crrc0 : RegisterOperand<CRRC0> {
436 let ParserMatchClass = PPCRegCRRCAsmOperand;
439 def PPCU1ImmAsmOperand : AsmOperandClass {
440 let Name = "U1Imm"; let PredicateMethod = "isU1Imm";
441 let RenderMethod = "addImmOperands";
443 def u1imm : Operand<i32> {
444 let PrintMethod = "printU1ImmOperand";
445 let ParserMatchClass = PPCU1ImmAsmOperand;
448 def PPCU2ImmAsmOperand : AsmOperandClass {
449 let Name = "U2Imm"; let PredicateMethod = "isU2Imm";
450 let RenderMethod = "addImmOperands";
452 def u2imm : Operand<i32> {
453 let PrintMethod = "printU2ImmOperand";
454 let ParserMatchClass = PPCU2ImmAsmOperand;
457 def PPCU3ImmAsmOperand : AsmOperandClass {
458 let Name = "U3Imm"; let PredicateMethod = "isU3Imm";
459 let RenderMethod = "addImmOperands";
461 def u3imm : Operand<i32> {
462 let PrintMethod = "printU3ImmOperand";
463 let ParserMatchClass = PPCU3ImmAsmOperand;
466 def PPCU4ImmAsmOperand : AsmOperandClass {
467 let Name = "U4Imm"; let PredicateMethod = "isU4Imm";
468 let RenderMethod = "addImmOperands";
470 def u4imm : Operand<i32> {
471 let PrintMethod = "printU4ImmOperand";
472 let ParserMatchClass = PPCU4ImmAsmOperand;
474 def PPCS5ImmAsmOperand : AsmOperandClass {
475 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
476 let RenderMethod = "addImmOperands";
478 def s5imm : Operand<i32> {
479 let PrintMethod = "printS5ImmOperand";
480 let ParserMatchClass = PPCS5ImmAsmOperand;
481 let DecoderMethod = "decodeSImmOperand<5>";
483 def PPCU5ImmAsmOperand : AsmOperandClass {
484 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
485 let RenderMethod = "addImmOperands";
487 def u5imm : Operand<i32> {
488 let PrintMethod = "printU5ImmOperand";
489 let ParserMatchClass = PPCU5ImmAsmOperand;
490 let DecoderMethod = "decodeUImmOperand<5>";
492 def PPCU6ImmAsmOperand : AsmOperandClass {
493 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
494 let RenderMethod = "addImmOperands";
496 def u6imm : Operand<i32> {
497 let PrintMethod = "printU6ImmOperand";
498 let ParserMatchClass = PPCU6ImmAsmOperand;
499 let DecoderMethod = "decodeUImmOperand<6>";
501 def PPCU12ImmAsmOperand : AsmOperandClass {
502 let Name = "U12Imm"; let PredicateMethod = "isU12Imm";
503 let RenderMethod = "addImmOperands";
505 def u12imm : Operand<i32> {
506 let PrintMethod = "printU12ImmOperand";
507 let ParserMatchClass = PPCU12ImmAsmOperand;
508 let DecoderMethod = "decodeUImmOperand<12>";
510 def PPCS16ImmAsmOperand : AsmOperandClass {
511 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
512 let RenderMethod = "addS16ImmOperands";
514 def s16imm : Operand<i32> {
515 let PrintMethod = "printS16ImmOperand";
516 let EncoderMethod = "getImm16Encoding";
517 let ParserMatchClass = PPCS16ImmAsmOperand;
518 let DecoderMethod = "decodeSImmOperand<16>";
520 def PPCU16ImmAsmOperand : AsmOperandClass {
521 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
522 let RenderMethod = "addU16ImmOperands";
524 def u16imm : Operand<i32> {
525 let PrintMethod = "printU16ImmOperand";
526 let EncoderMethod = "getImm16Encoding";
527 let ParserMatchClass = PPCU16ImmAsmOperand;
528 let DecoderMethod = "decodeUImmOperand<16>";
530 def PPCS17ImmAsmOperand : AsmOperandClass {
531 let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
532 let RenderMethod = "addS16ImmOperands";
534 def s17imm : Operand<i32> {
535 // This operand type is used for addis/lis to allow the assembler parser
536 // to accept immediates in the range -65536..65535 for compatibility with
537 // the GNU assembler. The operand is treated as 16-bit otherwise.
538 let PrintMethod = "printS16ImmOperand";
539 let EncoderMethod = "getImm16Encoding";
540 let ParserMatchClass = PPCS17ImmAsmOperand;
541 let DecoderMethod = "decodeSImmOperand<16>";
543 def PPCDirectBrAsmOperand : AsmOperandClass {
544 let Name = "DirectBr"; let PredicateMethod = "isDirectBr";
545 let RenderMethod = "addBranchTargetOperands";
547 def directbrtarget : Operand<OtherVT> {
548 let PrintMethod = "printBranchOperand";
549 let EncoderMethod = "getDirectBrEncoding";
550 let ParserMatchClass = PPCDirectBrAsmOperand;
552 def absdirectbrtarget : Operand<OtherVT> {
553 let PrintMethod = "printAbsBranchOperand";
554 let EncoderMethod = "getAbsDirectBrEncoding";
555 let ParserMatchClass = PPCDirectBrAsmOperand;
557 def PPCCondBrAsmOperand : AsmOperandClass {
558 let Name = "CondBr"; let PredicateMethod = "isCondBr";
559 let RenderMethod = "addBranchTargetOperands";
561 def condbrtarget : Operand<OtherVT> {
562 let PrintMethod = "printBranchOperand";
563 let EncoderMethod = "getCondBrEncoding";
564 let ParserMatchClass = PPCCondBrAsmOperand;
566 def abscondbrtarget : Operand<OtherVT> {
567 let PrintMethod = "printAbsBranchOperand";
568 let EncoderMethod = "getAbsCondBrEncoding";
569 let ParserMatchClass = PPCCondBrAsmOperand;
571 def calltarget : Operand<iPTR> {
572 let PrintMethod = "printBranchOperand";
573 let EncoderMethod = "getDirectBrEncoding";
574 let ParserMatchClass = PPCDirectBrAsmOperand;
576 def abscalltarget : Operand<iPTR> {
577 let PrintMethod = "printAbsBranchOperand";
578 let EncoderMethod = "getAbsDirectBrEncoding";
579 let ParserMatchClass = PPCDirectBrAsmOperand;
581 def PPCCRBitMaskOperand : AsmOperandClass {
582 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
584 def crbitm: Operand<i8> {
585 let PrintMethod = "printcrbitm";
586 let EncoderMethod = "get_crbitm_encoding";
587 let DecoderMethod = "decodeCRBitMOperand";
588 let ParserMatchClass = PPCCRBitMaskOperand;
591 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
592 def PPCRegGxRCNoR0Operand : AsmOperandClass {
593 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
595 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
596 let ParserMatchClass = PPCRegGxRCNoR0Operand;
598 // A version of ptr_rc usable with the asm parser.
599 def PPCRegGxRCOperand : AsmOperandClass {
600 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
602 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
603 let ParserMatchClass = PPCRegGxRCOperand;
606 def PPCDispRIOperand : AsmOperandClass {
607 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
608 let RenderMethod = "addS16ImmOperands";
610 def dispRI : Operand<iPTR> {
611 let ParserMatchClass = PPCDispRIOperand;
613 def PPCDispRIXOperand : AsmOperandClass {
614 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
615 let RenderMethod = "addImmOperands";
617 def dispRIX : Operand<iPTR> {
618 let ParserMatchClass = PPCDispRIXOperand;
620 def PPCDispSPE8Operand : AsmOperandClass {
621 let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
622 let RenderMethod = "addImmOperands";
624 def dispSPE8 : Operand<iPTR> {
625 let ParserMatchClass = PPCDispSPE8Operand;
627 def PPCDispSPE4Operand : AsmOperandClass {
628 let Name = "DispSPE4"; let PredicateMethod = "isU7ImmX4";
629 let RenderMethod = "addImmOperands";
631 def dispSPE4 : Operand<iPTR> {
632 let ParserMatchClass = PPCDispSPE4Operand;
634 def PPCDispSPE2Operand : AsmOperandClass {
635 let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
636 let RenderMethod = "addImmOperands";
638 def dispSPE2 : Operand<iPTR> {
639 let ParserMatchClass = PPCDispSPE2Operand;
642 def memri : Operand<iPTR> {
643 let PrintMethod = "printMemRegImm";
644 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
645 let EncoderMethod = "getMemRIEncoding";
646 let DecoderMethod = "decodeMemRIOperands";
648 def memrr : Operand<iPTR> {
649 let PrintMethod = "printMemRegReg";
650 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
652 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
653 let PrintMethod = "printMemRegImm";
654 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
655 let EncoderMethod = "getMemRIXEncoding";
656 let DecoderMethod = "decodeMemRIXOperands";
658 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
659 let PrintMethod = "printMemRegImm";
660 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
661 let EncoderMethod = "getSPE8DisEncoding";
663 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
664 let PrintMethod = "printMemRegImm";
665 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg);
666 let EncoderMethod = "getSPE4DisEncoding";
668 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
669 let PrintMethod = "printMemRegImm";
670 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
671 let EncoderMethod = "getSPE2DisEncoding";
674 // A single-register address. This is used with the SjLj
675 // pseudo-instructions.
676 def memr : Operand<iPTR> {
677 let MIOperandInfo = (ops ptr_rc:$ptrreg);
679 def PPCTLSRegOperand : AsmOperandClass {
680 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
681 let RenderMethod = "addTLSRegOperands";
683 def tlsreg32 : Operand<i32> {
684 let EncoderMethod = "getTLSRegEncoding";
685 let ParserMatchClass = PPCTLSRegOperand;
687 def tlsgd32 : Operand<i32> {}
688 def tlscall32 : Operand<i32> {
689 let PrintMethod = "printTLSCall";
690 let MIOperandInfo = (ops calltarget:$func, tlsgd32:$sym);
691 let EncoderMethod = "getTLSCallEncoding";
694 // PowerPC Predicate operand.
695 def pred : Operand<OtherVT> {
696 let PrintMethod = "printPredicateOperand";
697 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
700 // Define PowerPC specific addressing mode.
701 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
702 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
703 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
704 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std"
706 // The address in a single register. This is used with the SjLj
707 // pseudo-instructions.
708 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
710 /// This is just the offset part of iaddr, used for preinc.
711 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
713 //===----------------------------------------------------------------------===//
714 // PowerPC Instruction Predicate Definitions.
715 def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
716 def In64BitMode : Predicate<"PPCSubTarget->isPPC64()">;
717 def IsBookE : Predicate<"PPCSubTarget->isBookE()">;
718 def IsNotBookE : Predicate<"!PPCSubTarget->isBookE()">;
719 def HasOnlyMSYNC : Predicate<"PPCSubTarget->hasOnlyMSYNC()">;
720 def HasSYNC : Predicate<"!PPCSubTarget->hasOnlyMSYNC()">;
721 def IsPPC4xx : Predicate<"PPCSubTarget->isPPC4xx()">;
722 def IsPPC6xx : Predicate<"PPCSubTarget->isPPC6xx()">;
723 def IsE500 : Predicate<"PPCSubTarget->isE500()">;
724 def HasSPE : Predicate<"PPCSubTarget->HasSPE()">;
725 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
726 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
727 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
728 def NaNsFPMath : Predicate<"!TM.Options.NoNaNsFPMath">;
729 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
730 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
732 //===----------------------------------------------------------------------===//
733 // PowerPC Multiclass Definitions.
735 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
736 string asmbase, string asmstr, InstrItinClass itin,
738 let BaseName = asmbase in {
739 def NAME : XForm_6<opcode, xo, OOL, IOL,
740 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
741 pattern>, RecFormRel;
743 def o : XForm_6<opcode, xo, OOL, IOL,
744 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
745 []>, isDOT, RecFormRel;
749 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
750 string asmbase, string asmstr, InstrItinClass itin,
752 let BaseName = asmbase in {
753 let Defs = [CARRY] in
754 def NAME : XForm_6<opcode, xo, OOL, IOL,
755 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
756 pattern>, RecFormRel;
757 let Defs = [CARRY, CR0] in
758 def o : XForm_6<opcode, xo, OOL, IOL,
759 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
760 []>, isDOT, RecFormRel;
764 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
765 string asmbase, string asmstr, InstrItinClass itin,
767 let BaseName = asmbase in {
768 let Defs = [CARRY] in
769 def NAME : XForm_10<opcode, xo, OOL, IOL,
770 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
771 pattern>, RecFormRel;
772 let Defs = [CARRY, CR0] in
773 def o : XForm_10<opcode, xo, OOL, IOL,
774 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
775 []>, isDOT, RecFormRel;
779 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
780 string asmbase, string asmstr, InstrItinClass itin,
782 let BaseName = asmbase in {
783 def NAME : XForm_11<opcode, xo, OOL, IOL,
784 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
785 pattern>, RecFormRel;
787 def o : XForm_11<opcode, xo, OOL, IOL,
788 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
789 []>, isDOT, RecFormRel;
793 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
794 string asmbase, string asmstr, InstrItinClass itin,
796 let BaseName = asmbase in {
797 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
798 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
799 pattern>, RecFormRel;
801 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
802 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
803 []>, isDOT, RecFormRel;
807 // Multiclass for instructions for which the non record form is not cracked
808 // and the record form is cracked (i.e. divw, mullw, etc.)
809 multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
810 string asmbase, string asmstr, InstrItinClass itin,
812 let BaseName = asmbase in {
813 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
814 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
815 pattern>, RecFormRel;
817 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
818 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
819 []>, isDOT, RecFormRel, PPC970_DGroup_First,
820 PPC970_DGroup_Cracked;
824 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
825 string asmbase, string asmstr, InstrItinClass itin,
827 let BaseName = asmbase in {
828 let Defs = [CARRY] in
829 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
830 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
831 pattern>, RecFormRel;
832 let Defs = [CARRY, CR0] in
833 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
834 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
835 []>, isDOT, RecFormRel;
839 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
840 string asmbase, string asmstr, InstrItinClass itin,
842 let BaseName = asmbase in {
843 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
844 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
845 pattern>, RecFormRel;
847 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
848 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
849 []>, isDOT, RecFormRel;
853 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
854 string asmbase, string asmstr, InstrItinClass itin,
856 let BaseName = asmbase in {
857 let Defs = [CARRY] in
858 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
859 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
860 pattern>, RecFormRel;
861 let Defs = [CARRY, CR0] in
862 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
863 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
864 []>, isDOT, RecFormRel;
868 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
869 string asmbase, string asmstr, InstrItinClass itin,
871 let BaseName = asmbase in {
872 def NAME : MForm_2<opcode, OOL, IOL,
873 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
874 pattern>, RecFormRel;
876 def o : MForm_2<opcode, OOL, IOL,
877 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
878 []>, isDOT, RecFormRel;
882 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
883 string asmbase, string asmstr, InstrItinClass itin,
885 let BaseName = asmbase in {
886 def NAME : MDForm_1<opcode, xo, OOL, IOL,
887 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
888 pattern>, RecFormRel;
890 def o : MDForm_1<opcode, xo, OOL, IOL,
891 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
892 []>, isDOT, RecFormRel;
896 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
897 string asmbase, string asmstr, InstrItinClass itin,
899 let BaseName = asmbase in {
900 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
901 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
902 pattern>, RecFormRel;
904 def o : MDSForm_1<opcode, xo, OOL, IOL,
905 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
906 []>, isDOT, RecFormRel;
910 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
911 string asmbase, string asmstr, InstrItinClass itin,
913 let BaseName = asmbase in {
914 let Defs = [CARRY] in
915 def NAME : XSForm_1<opcode, xo, OOL, IOL,
916 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
917 pattern>, RecFormRel;
918 let Defs = [CARRY, CR0] in
919 def o : XSForm_1<opcode, xo, OOL, IOL,
920 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
921 []>, isDOT, RecFormRel;
925 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
926 string asmbase, string asmstr, InstrItinClass itin,
928 let BaseName = asmbase in {
929 def NAME : XForm_26<opcode, xo, OOL, IOL,
930 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
931 pattern>, RecFormRel;
933 def o : XForm_26<opcode, xo, OOL, IOL,
934 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
935 []>, isDOT, RecFormRel;
939 multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
940 string asmbase, string asmstr, InstrItinClass itin,
942 let BaseName = asmbase in {
943 def NAME : XForm_28<opcode, xo, OOL, IOL,
944 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
945 pattern>, RecFormRel;
947 def o : XForm_28<opcode, xo, OOL, IOL,
948 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
949 []>, isDOT, RecFormRel;
953 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
954 string asmbase, string asmstr, InstrItinClass itin,
956 let BaseName = asmbase in {
957 def NAME : AForm_1<opcode, xo, OOL, IOL,
958 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
959 pattern>, RecFormRel;
961 def o : AForm_1<opcode, xo, OOL, IOL,
962 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
963 []>, isDOT, RecFormRel;
967 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
968 string asmbase, string asmstr, InstrItinClass itin,
970 let BaseName = asmbase in {
971 def NAME : AForm_2<opcode, xo, OOL, IOL,
972 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
973 pattern>, RecFormRel;
975 def o : AForm_2<opcode, xo, OOL, IOL,
976 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
977 []>, isDOT, RecFormRel;
981 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
982 string asmbase, string asmstr, InstrItinClass itin,
984 let BaseName = asmbase in {
985 def NAME : AForm_3<opcode, xo, OOL, IOL,
986 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
987 pattern>, RecFormRel;
989 def o : AForm_3<opcode, xo, OOL, IOL,
990 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
991 []>, isDOT, RecFormRel;
995 //===----------------------------------------------------------------------===//
996 // PowerPC Instruction Definitions.
998 // Pseudo-instructions:
1000 let hasCtrlDep = 1 in {
1001 let Defs = [R1], Uses = [R1] in {
1002 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1003 [(callseq_start timm:$amt)]>;
1004 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
1005 [(callseq_end timm:$amt1, timm:$amt2)]>;
1008 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1009 "UPDATE_VRSAVE $rD, $rS", []>;
1012 let Defs = [R1], Uses = [R1] in
1013 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1015 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
1017 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
1018 // instruction selection into a branch sequence.
1019 let usesCustomInserter = 1, // Expanded after instruction selection.
1020 PPC970_Single = 1 in {
1021 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
1022 // because either operand might become the first operand in an isel, and
1023 // that operand cannot be r0.
1024 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1025 gprc_nor0:$T, gprc_nor0:$F,
1026 i32imm:$BROPC), "#SELECT_CC_I4",
1028 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1029 g8rc_nox0:$T, g8rc_nox0:$F,
1030 i32imm:$BROPC), "#SELECT_CC_I8",
1032 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1033 i32imm:$BROPC), "#SELECT_CC_F4",
1035 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1036 i32imm:$BROPC), "#SELECT_CC_F8",
1038 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
1039 i32imm:$BROPC), "#SELECT_CC_VRRC",
1042 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition
1043 // register bit directly.
1044 def SELECT_I4 : Pseudo<(outs gprc:$dst), (ins crbitrc:$cond,
1045 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4",
1046 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>;
1047 def SELECT_I8 : Pseudo<(outs g8rc:$dst), (ins crbitrc:$cond,
1048 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8",
1049 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>;
1050 def SELECT_F4 : Pseudo<(outs f4rc:$dst), (ins crbitrc:$cond,
1051 f4rc:$T, f4rc:$F), "#SELECT_F4",
1052 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>;
1053 def SELECT_F8 : Pseudo<(outs f8rc:$dst), (ins crbitrc:$cond,
1054 f8rc:$T, f8rc:$F), "#SELECT_F8",
1055 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>;
1056 def SELECT_VRRC: Pseudo<(outs vrrc:$dst), (ins crbitrc:$cond,
1057 vrrc:$T, vrrc:$F), "#SELECT_VRRC",
1059 (select i1:$cond, v4i32:$T, v4i32:$F))]>;
1062 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
1063 // scavenge a register for it.
1064 let mayStore = 1 in {
1065 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
1067 def SPILL_CRBIT : Pseudo<(outs), (ins crbitrc:$cond, memri:$F),
1068 "#SPILL_CRBIT", []>;
1071 // RESTORE_CR - Indicate that we're restoring the CR register (previously
1072 // spilled), so we'll need to scavenge a register for it.
1073 let mayLoad = 1 in {
1074 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
1076 def RESTORE_CRBIT : Pseudo<(outs crbitrc:$cond), (ins memri:$F),
1077 "#RESTORE_CRBIT", []>;
1080 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
1081 let isReturn = 1, Uses = [LR, RM] in
1082 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
1083 [(retflag)]>, Requires<[In32BitMode]>;
1084 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
1085 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1088 let isCodeGenOnly = 1 in {
1089 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
1090 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
1093 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
1094 "bcctr 12, $bi, 0", IIC_BrB, []>;
1095 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
1096 "bcctr 4, $bi, 0", IIC_BrB, []>;
1102 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1105 def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,
1108 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
1109 let isBarrier = 1 in {
1110 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
1113 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst),
1114 "ba $dst", IIC_BrB, []>;
1117 // BCC represents an arbitrary conditional branch on a predicate.
1118 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
1119 // a two-value operand where a dag node expects two operands. :(
1120 let isCodeGenOnly = 1 in {
1121 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
1122 "b${cond:cc}${cond:pm} ${cond:reg}, $dst"
1123 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
1124 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1125 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">;
1127 let isReturn = 1, Uses = [LR, RM] in
1128 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
1129 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>;
1132 let isCodeGenOnly = 1 in {
1133 let Pattern = [(brcond i1:$bi, bb:$dst)] in
1134 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1135 "bc 12, $bi, $dst">;
1137 let Pattern = [(brcond (not i1:$bi), bb:$dst)] in
1138 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst),
1141 let isReturn = 1, Uses = [LR, RM] in
1142 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi),
1143 "bclr 12, $bi, 0", IIC_BrB, []>;
1144 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi),
1145 "bclr 4, $bi, 0", IIC_BrB, []>;
1148 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1149 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
1150 "bdzlr", IIC_BrB, []>;
1151 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
1152 "bdnzlr", IIC_BrB, []>;
1153 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins),
1154 "bdzlr+", IIC_BrB, []>;
1155 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins),
1156 "bdnzlr+", IIC_BrB, []>;
1157 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins),
1158 "bdzlr-", IIC_BrB, []>;
1159 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins),
1160 "bdnzlr-", IIC_BrB, []>;
1163 let Defs = [CTR], Uses = [CTR] in {
1164 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
1166 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
1168 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst),
1170 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst),
1172 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst),
1174 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst),
1176 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst),
1178 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst),
1180 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst),
1182 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst),
1184 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst),
1186 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst),
1191 // The unconditional BCL used by the SjLj setjmp code.
1192 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
1193 let Defs = [LR], Uses = [RM] in {
1194 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
1195 "bcl 20, 31, $dst">;
1199 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
1200 // Convenient aliases for call instructions
1201 let Uses = [RM] in {
1202 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
1203 "bl $func", IIC_BrB, []>; // See Pat patterns below.
1204 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
1205 "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>;
1207 let isCodeGenOnly = 1 in {
1208 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func),
1209 "bl $func", IIC_BrB, []>;
1210 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst),
1211 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">;
1212 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst),
1213 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">;
1215 def BCL : BForm_4<16, 12, 0, 1, (outs),
1216 (ins crbitrc:$bi, condbrtarget:$dst),
1217 "bcl 12, $bi, $dst">;
1218 def BCLn : BForm_4<16, 4, 0, 1, (outs),
1219 (ins crbitrc:$bi, condbrtarget:$dst),
1220 "bcl 4, $bi, $dst">;
1223 let Uses = [CTR, RM] in {
1224 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
1225 "bctrl", IIC_BrB, [(PPCbctrl)]>,
1226 Requires<[In32BitMode]>;
1228 let isCodeGenOnly = 1 in {
1229 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
1230 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
1233 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
1234 "bcctrl 12, $bi, 0", IIC_BrB, []>;
1235 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
1236 "bcctrl 4, $bi, 0", IIC_BrB, []>;
1239 let Uses = [LR, RM] in {
1240 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins),
1241 "blrl", IIC_BrB, []>;
1243 let isCodeGenOnly = 1 in {
1244 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
1245 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB,
1248 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi),
1249 "bclrl 12, $bi, 0", IIC_BrB, []>;
1250 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi),
1251 "bclrl 4, $bi, 0", IIC_BrB, []>;
1254 let Defs = [CTR], Uses = [CTR, RM] in {
1255 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
1257 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
1259 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst),
1261 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst),
1263 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst),
1265 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst),
1267 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst),
1269 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst),
1271 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst),
1273 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst),
1275 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst),
1277 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst),
1280 let Defs = [CTR], Uses = [CTR, LR, RM] in {
1281 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
1282 "bdzlrl", IIC_BrB, []>;
1283 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
1284 "bdnzlrl", IIC_BrB, []>;
1285 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins),
1286 "bdzlrl+", IIC_BrB, []>;
1287 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins),
1288 "bdnzlrl+", IIC_BrB, []>;
1289 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins),
1290 "bdzlrl-", IIC_BrB, []>;
1291 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins),
1292 "bdnzlrl-", IIC_BrB, []>;
1296 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1297 def TCRETURNdi :Pseudo< (outs),
1298 (ins calltarget:$dst, i32imm:$offset),
1299 "#TC_RETURNd $dst $offset",
1303 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1304 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1305 "#TC_RETURNa $func $offset",
1306 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
1308 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
1309 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1310 "#TC_RETURNr $dst $offset",
1314 let isCodeGenOnly = 1 in {
1316 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
1317 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
1318 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
1319 []>, Requires<[In32BitMode]>;
1321 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1322 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1323 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
1327 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
1328 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
1329 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
1335 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
1337 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1338 "#EH_SJLJ_SETJMP32",
1339 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
1340 Requires<[In32BitMode]>;
1341 let isTerminator = 1 in
1342 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1343 "#EH_SJLJ_LONGJMP32",
1344 [(PPCeh_sjlj_longjmp addr:$buf)]>,
1345 Requires<[In32BitMode]>;
1348 let isBranch = 1, isTerminator = 1 in {
1349 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1350 "#EH_SjLj_Setup\t$dst", []>;
1354 let PPC970_Unit = 7 in {
1355 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
1356 "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>;
1359 // DCB* instructions.
1360 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
1361 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1362 PPC970_DGroup_Single;
1363 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst",
1364 IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1365 PPC970_DGroup_Single;
1366 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
1367 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1368 PPC970_DGroup_Single;
1369 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
1370 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1371 PPC970_DGroup_Single;
1372 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), "dcbt $dst",
1373 IIC_LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1374 PPC970_DGroup_Single;
1375 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), "dcbtst $dst",
1376 IIC_LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1377 PPC970_DGroup_Single;
1378 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
1379 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1380 PPC970_DGroup_Single;
1381 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
1382 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1383 PPC970_DGroup_Single;
1385 def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src),
1386 "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
1388 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1389 (DCBT xoaddr:$dst)>; // data prefetch for loads
1390 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
1391 (DCBTST xoaddr:$dst)>; // data prefetch for stores
1392 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
1393 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
1395 // Atomic operations
1396 let usesCustomInserter = 1 in {
1397 let Defs = [CR0] in {
1398 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1399 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1400 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1401 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1402 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1403 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1404 def ATOMIC_LOAD_AND_I8 : Pseudo<
1405 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1406 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1407 def ATOMIC_LOAD_OR_I8 : Pseudo<
1408 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1409 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1410 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1411 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1412 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1413 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1414 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1415 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1416 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1417 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1418 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1419 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1420 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1421 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1422 def ATOMIC_LOAD_AND_I16 : Pseudo<
1423 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1424 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1425 def ATOMIC_LOAD_OR_I16 : Pseudo<
1426 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1427 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1428 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1429 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1430 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1431 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1432 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1433 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1434 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1435 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1436 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1437 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1438 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1439 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1440 def ATOMIC_LOAD_AND_I32 : Pseudo<
1441 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1442 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1443 def ATOMIC_LOAD_OR_I32 : Pseudo<
1444 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1445 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1446 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1447 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1448 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1449 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1450 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1451 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1453 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1454 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1455 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1456 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1457 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1458 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1459 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1460 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1461 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1463 def ATOMIC_SWAP_I8 : Pseudo<
1464 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1465 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1466 def ATOMIC_SWAP_I16 : Pseudo<
1467 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1468 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1469 def ATOMIC_SWAP_I32 : Pseudo<
1470 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1471 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1475 // Instructions to support atomic operations
1476 let mayLoad = 1, hasSideEffects = 0 in {
1477 def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1478 "lbarx $rD, $src", IIC_LdStLWARX, []>,
1479 Requires<[HasPartwordAtomics]>;
1481 def LHARX : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1482 "lharx $rD, $src", IIC_LdStLWARX, []>,
1483 Requires<[HasPartwordAtomics]>;
1485 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1486 "lwarx $rD, $src", IIC_LdStLWARX, []>;
1488 // Instructions to support lock versions of atomics
1489 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
1490 def LBARXL : XForm_1<31, 52, (outs gprc:$rD), (ins memrr:$src),
1491 "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1492 Requires<[HasPartwordAtomics]>;
1494 def LHARXL : XForm_1<31, 116, (outs gprc:$rD), (ins memrr:$src),
1495 "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
1496 Requires<[HasPartwordAtomics]>;
1498 def LWARXL : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1499 "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
1502 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
1503 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
1504 "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
1505 isDOT, Requires<[HasPartwordAtomics]>;
1507 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
1508 "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
1509 isDOT, Requires<[HasPartwordAtomics]>;
1511 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1512 "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
1515 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1516 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
1518 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
1519 "twi $to, $rA, $imm", IIC_IntTrapW, []>;
1520 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
1521 "tw $to, $rA, $rB", IIC_IntTrapW, []>;
1522 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
1523 "tdi $to, $rA, $imm", IIC_IntTrapD, []>;
1524 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB),
1525 "td $to, $rA, $rB", IIC_IntTrapD, []>;
1527 //===----------------------------------------------------------------------===//
1528 // PPC32 Load Instructions.
1531 // Unindexed (r+i) Loads.
1532 let PPC970_Unit = 2 in {
1533 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1534 "lbz $rD, $src", IIC_LdStLoad,
1535 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1536 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1537 "lha $rD, $src", IIC_LdStLHA,
1538 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1539 PPC970_DGroup_Cracked;
1540 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1541 "lhz $rD, $src", IIC_LdStLoad,
1542 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1543 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1544 "lwz $rD, $src", IIC_LdStLoad,
1545 [(set i32:$rD, (load iaddr:$src))]>;
1547 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1548 "lfs $rD, $src", IIC_LdStLFD,
1549 [(set f32:$rD, (load iaddr:$src))]>;
1550 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1551 "lfd $rD, $src", IIC_LdStLFD,
1552 [(set f64:$rD, (load iaddr:$src))]>;
1555 // Unindexed (r+i) Loads with Update (preinc).
1556 let mayLoad = 1, hasSideEffects = 0 in {
1557 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1558 "lbzu $rD, $addr", IIC_LdStLoadUpd,
1559 []>, RegConstraint<"$addr.reg = $ea_result">,
1560 NoEncode<"$ea_result">;
1562 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1563 "lhau $rD, $addr", IIC_LdStLHAU,
1564 []>, RegConstraint<"$addr.reg = $ea_result">,
1565 NoEncode<"$ea_result">;
1567 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1568 "lhzu $rD, $addr", IIC_LdStLoadUpd,
1569 []>, RegConstraint<"$addr.reg = $ea_result">,
1570 NoEncode<"$ea_result">;
1572 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1573 "lwzu $rD, $addr", IIC_LdStLoadUpd,
1574 []>, RegConstraint<"$addr.reg = $ea_result">,
1575 NoEncode<"$ea_result">;
1577 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1578 "lfsu $rD, $addr", IIC_LdStLFDU,
1579 []>, RegConstraint<"$addr.reg = $ea_result">,
1580 NoEncode<"$ea_result">;
1582 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1583 "lfdu $rD, $addr", IIC_LdStLFDU,
1584 []>, RegConstraint<"$addr.reg = $ea_result">,
1585 NoEncode<"$ea_result">;
1588 // Indexed (r+r) Loads with Update (preinc).
1589 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1591 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
1592 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1593 NoEncode<"$ea_result">;
1595 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1597 "lhaux $rD, $addr", IIC_LdStLHAUX,
1598 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1599 NoEncode<"$ea_result">;
1601 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1603 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
1604 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1605 NoEncode<"$ea_result">;
1607 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1609 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
1610 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1611 NoEncode<"$ea_result">;
1613 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1615 "lfsux $rD, $addr", IIC_LdStLFDUX,
1616 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1617 NoEncode<"$ea_result">;
1619 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1621 "lfdux $rD, $addr", IIC_LdStLFDUX,
1622 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1623 NoEncode<"$ea_result">;
1627 // Indexed (r+r) Loads.
1629 let PPC970_Unit = 2 in {
1630 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1631 "lbzx $rD, $src", IIC_LdStLoad,
1632 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1633 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1634 "lhax $rD, $src", IIC_LdStLHA,
1635 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1636 PPC970_DGroup_Cracked;
1637 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1638 "lhzx $rD, $src", IIC_LdStLoad,
1639 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1640 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1641 "lwzx $rD, $src", IIC_LdStLoad,
1642 [(set i32:$rD, (load xaddr:$src))]>;
1645 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1646 "lhbrx $rD, $src", IIC_LdStLoad,
1647 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1648 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1649 "lwbrx $rD, $src", IIC_LdStLoad,
1650 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1652 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1653 "lfsx $frD, $src", IIC_LdStLFD,
1654 [(set f32:$frD, (load xaddr:$src))]>;
1655 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1656 "lfdx $frD, $src", IIC_LdStLFD,
1657 [(set f64:$frD, (load xaddr:$src))]>;
1659 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1660 "lfiwax $frD, $src", IIC_LdStLFD,
1661 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1662 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1663 "lfiwzx $frD, $src", IIC_LdStLFD,
1664 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1668 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src),
1669 "lmw $rD, $src", IIC_LdStLMW, []>;
1671 //===----------------------------------------------------------------------===//
1672 // PPC32 Store Instructions.
1675 // Unindexed (r+i) Stores.
1676 let PPC970_Unit = 2 in {
1677 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1678 "stb $rS, $src", IIC_LdStStore,
1679 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1680 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1681 "sth $rS, $src", IIC_LdStStore,
1682 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1683 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1684 "stw $rS, $src", IIC_LdStStore,
1685 [(store i32:$rS, iaddr:$src)]>;
1686 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1687 "stfs $rS, $dst", IIC_LdStSTFD,
1688 [(store f32:$rS, iaddr:$dst)]>;
1689 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1690 "stfd $rS, $dst", IIC_LdStSTFD,
1691 [(store f64:$rS, iaddr:$dst)]>;
1694 // Unindexed (r+i) Stores with Update (preinc).
1695 let PPC970_Unit = 2, mayStore = 1 in {
1696 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1697 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
1698 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1699 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1700 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
1701 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1702 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1703 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
1704 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1705 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1706 "stfsu $rS, $dst", IIC_LdStSTFDU, []>,
1707 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1708 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1709 "stfdu $rS, $dst", IIC_LdStSTFDU, []>,
1710 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1713 // Patterns to match the pre-inc stores. We can't put the patterns on
1714 // the instruction definitions directly as ISel wants the address base
1715 // and offset to be separate operands, not a single complex operand.
1716 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1717 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1718 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1719 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1720 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1721 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1722 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1723 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1724 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1725 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1727 // Indexed (r+r) Stores.
1728 let PPC970_Unit = 2 in {
1729 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1730 "stbx $rS, $dst", IIC_LdStStore,
1731 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1732 PPC970_DGroup_Cracked;
1733 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1734 "sthx $rS, $dst", IIC_LdStStore,
1735 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1736 PPC970_DGroup_Cracked;
1737 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1738 "stwx $rS, $dst", IIC_LdStStore,
1739 [(store i32:$rS, xaddr:$dst)]>,
1740 PPC970_DGroup_Cracked;
1742 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1743 "sthbrx $rS, $dst", IIC_LdStStore,
1744 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1745 PPC970_DGroup_Cracked;
1746 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1747 "stwbrx $rS, $dst", IIC_LdStStore,
1748 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1749 PPC970_DGroup_Cracked;
1751 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1752 "stfiwx $frS, $dst", IIC_LdStSTFD,
1753 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1755 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1756 "stfsx $frS, $dst", IIC_LdStSTFD,
1757 [(store f32:$frS, xaddr:$dst)]>;
1758 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1759 "stfdx $frS, $dst", IIC_LdStSTFD,
1760 [(store f64:$frS, xaddr:$dst)]>;
1763 // Indexed (r+r) Stores with Update (preinc).
1764 let PPC970_Unit = 2, mayStore = 1 in {
1765 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1766 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
1767 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1768 PPC970_DGroup_Cracked;
1769 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1770 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
1771 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1772 PPC970_DGroup_Cracked;
1773 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1774 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
1775 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1776 PPC970_DGroup_Cracked;
1777 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1778 "stfsux $rS, $dst", IIC_LdStSTFDU, []>,
1779 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1780 PPC970_DGroup_Cracked;
1781 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1782 "stfdux $rS, $dst", IIC_LdStSTFDU, []>,
1783 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1784 PPC970_DGroup_Cracked;
1787 // Patterns to match the pre-inc stores. We can't put the patterns on
1788 // the instruction definitions directly as ISel wants the address base
1789 // and offset to be separate operands, not a single complex operand.
1790 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1791 (STBUX $rS, $ptrreg, $ptroff)>;
1792 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1793 (STHUX $rS, $ptrreg, $ptroff)>;
1794 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1795 (STWUX $rS, $ptrreg, $ptroff)>;
1796 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1797 (STFSUX $rS, $ptrreg, $ptroff)>;
1798 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1799 (STFDUX $rS, $ptrreg, $ptroff)>;
1802 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
1803 "stmw $rS, $dst", IIC_LdStLMW, []>;
1805 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1806 "sync $L", IIC_LdStSync, []>;
1808 let isCodeGenOnly = 1 in {
1809 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1810 "msync", IIC_LdStSync, []> {
1815 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>;
1816 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
1817 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1818 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
1820 //===----------------------------------------------------------------------===//
1821 // PPC32 Arithmetic Instructions.
1824 let PPC970_Unit = 1 in { // FXU Operations.
1825 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
1826 "addi $rD, $rA, $imm", IIC_IntSimple,
1827 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
1828 let BaseName = "addic" in {
1829 let Defs = [CARRY] in
1830 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1831 "addic $rD, $rA, $imm", IIC_IntGeneral,
1832 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
1833 RecFormRel, PPC970_DGroup_Cracked;
1834 let Defs = [CARRY, CR0] in
1835 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1836 "addic. $rD, $rA, $imm", IIC_IntGeneral,
1837 []>, isDOT, RecFormRel;
1839 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm),
1840 "addis $rD, $rA, $imm", IIC_IntSimple,
1841 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1842 let isCodeGenOnly = 1 in
1843 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
1844 "la $rD, $sym($rA)", IIC_IntGeneral,
1845 [(set i32:$rD, (add i32:$rA,
1846 (PPClo tglobaladdr:$sym, 0)))]>;
1847 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1848 "mulli $rD, $rA, $imm", IIC_IntMulLI,
1849 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>;
1850 let Defs = [CARRY] in
1851 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1852 "subfic $rD, $rA, $imm", IIC_IntGeneral,
1853 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
1855 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1856 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
1857 "li $rD, $imm", IIC_IntSimple,
1858 [(set i32:$rD, imm32SExt16:$imm)]>;
1859 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
1860 "lis $rD, $imm", IIC_IntSimple,
1861 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1865 let PPC970_Unit = 1 in { // FXU Operations.
1866 let Defs = [CR0] in {
1867 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1868 "andi. $dst, $src1, $src2", IIC_IntGeneral,
1869 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1871 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1872 "andis. $dst, $src1, $src2", IIC_IntGeneral,
1873 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1876 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1877 "ori $dst, $src1, $src2", IIC_IntSimple,
1878 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1879 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1880 "oris $dst, $src1, $src2", IIC_IntSimple,
1881 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1882 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1883 "xori $dst, $src1, $src2", IIC_IntSimple,
1884 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1885 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1886 "xoris $dst, $src1, $src2", IIC_IntSimple,
1887 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1889 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple,
1891 let isCodeGenOnly = 1 in {
1892 // The POWER6 and POWER7 have special group-terminating nops.
1893 def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins),
1894 "ori 1, 1, 0", IIC_IntSimple, []>;
1895 def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins),
1896 "ori 2, 2, 0", IIC_IntSimple, []>;
1899 let isCompare = 1, hasSideEffects = 0 in {
1900 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1901 "cmpwi $crD, $rA, $imm", IIC_IntCompare>;
1902 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1903 "cmplwi $dst, $src1, $src2", IIC_IntCompare>;
1907 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
1908 let isCommutable = 1 in {
1909 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1910 "nand", "$rA, $rS, $rB", IIC_IntSimple,
1911 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1912 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1913 "and", "$rA, $rS, $rB", IIC_IntSimple,
1914 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1916 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1917 "andc", "$rA, $rS, $rB", IIC_IntSimple,
1918 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1919 let isCommutable = 1 in {
1920 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1921 "or", "$rA, $rS, $rB", IIC_IntSimple,
1922 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1923 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1924 "nor", "$rA, $rS, $rB", IIC_IntSimple,
1925 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1927 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1928 "orc", "$rA, $rS, $rB", IIC_IntSimple,
1929 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1930 let isCommutable = 1 in {
1931 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1932 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
1933 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1934 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1935 "xor", "$rA, $rS, $rB", IIC_IntSimple,
1936 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1938 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1939 "slw", "$rA, $rS, $rB", IIC_IntGeneral,
1940 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1941 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1942 "srw", "$rA, $rS, $rB", IIC_IntGeneral,
1943 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1944 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1945 "sraw", "$rA, $rS, $rB", IIC_IntShift,
1946 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1949 let PPC970_Unit = 1 in { // FXU Operations.
1950 let hasSideEffects = 0 in {
1951 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1952 "srawi", "$rA, $rS, $SH", IIC_IntShift,
1953 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1954 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1955 "cntlzw", "$rA, $rS", IIC_IntGeneral,
1956 [(set i32:$rA, (ctlz i32:$rS))]>;
1957 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1958 "extsb", "$rA, $rS", IIC_IntSimple,
1959 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1960 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1961 "extsh", "$rA, $rS", IIC_IntSimple,
1962 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1964 let isCommutable = 1 in
1965 def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1966 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
1967 [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>;
1969 let isCompare = 1, hasSideEffects = 0 in {
1970 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1971 "cmpw $crD, $rA, $rB", IIC_IntCompare>;
1972 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1973 "cmplw $crD, $rA, $rB", IIC_IntCompare>;
1976 let PPC970_Unit = 3 in { // FPU Operations.
1977 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1978 // "fcmpo $crD, $fA, $fB", IIC_FPCompare>;
1979 let isCompare = 1, hasSideEffects = 0 in {
1980 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1981 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1982 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
1983 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1984 "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
1987 let Uses = [RM] in {
1988 let hasSideEffects = 0 in {
1989 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
1990 "fctiw", "$frD, $frB", IIC_FPGeneral,
1992 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1993 "fctiwz", "$frD, $frB", IIC_FPGeneral,
1994 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1996 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1997 "frsp", "$frD, $frB", IIC_FPGeneral,
1998 [(set f32:$frD, (fround f64:$frB))]>;
2000 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2001 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
2002 "frin", "$frD, $frB", IIC_FPGeneral,
2003 [(set f64:$frD, (frnd f64:$frB))]>;
2004 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
2005 "frin", "$frD, $frB", IIC_FPGeneral,
2006 [(set f32:$frD, (frnd f32:$frB))]>;
2009 let hasSideEffects = 0 in {
2010 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2011 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
2012 "frip", "$frD, $frB", IIC_FPGeneral,
2013 [(set f64:$frD, (fceil f64:$frB))]>;
2014 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
2015 "frip", "$frD, $frB", IIC_FPGeneral,
2016 [(set f32:$frD, (fceil f32:$frB))]>;
2017 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2018 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
2019 "friz", "$frD, $frB", IIC_FPGeneral,
2020 [(set f64:$frD, (ftrunc f64:$frB))]>;
2021 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
2022 "friz", "$frD, $frB", IIC_FPGeneral,
2023 [(set f32:$frD, (ftrunc f32:$frB))]>;
2024 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2025 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
2026 "frim", "$frD, $frB", IIC_FPGeneral,
2027 [(set f64:$frD, (ffloor f64:$frB))]>;
2028 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
2029 "frim", "$frD, $frB", IIC_FPGeneral,
2030 [(set f32:$frD, (ffloor f32:$frB))]>;
2032 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
2033 "fsqrt", "$frD, $frB", IIC_FPSqrtD,
2034 [(set f64:$frD, (fsqrt f64:$frB))]>;
2035 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
2036 "fsqrts", "$frD, $frB", IIC_FPSqrtS,
2037 [(set f32:$frD, (fsqrt f32:$frB))]>;
2042 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
2043 /// often coalesced away and we don't want the dispatch group builder to think
2044 /// that they will fill slots (which could cause the load of a LSU reject to
2045 /// sneak into a d-group with a store).
2046 let hasSideEffects = 0 in
2047 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
2048 "fmr", "$frD, $frB", IIC_FPGeneral,
2049 []>, // (set f32:$frD, f32:$frB)
2052 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2053 // These are artificially split into two different forms, for 4/8 byte FP.
2054 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
2055 "fabs", "$frD, $frB", IIC_FPGeneral,
2056 [(set f32:$frD, (fabs f32:$frB))]>;
2057 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2058 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
2059 "fabs", "$frD, $frB", IIC_FPGeneral,
2060 [(set f64:$frD, (fabs f64:$frB))]>;
2061 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
2062 "fnabs", "$frD, $frB", IIC_FPGeneral,
2063 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
2064 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2065 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
2066 "fnabs", "$frD, $frB", IIC_FPGeneral,
2067 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
2068 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
2069 "fneg", "$frD, $frB", IIC_FPGeneral,
2070 [(set f32:$frD, (fneg f32:$frB))]>;
2071 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2072 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
2073 "fneg", "$frD, $frB", IIC_FPGeneral,
2074 [(set f64:$frD, (fneg f64:$frB))]>;
2076 defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB),
2077 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2078 [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>;
2079 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2080 defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB),
2081 "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral,
2082 [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>;
2084 // Reciprocal estimates.
2085 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
2086 "fre", "$frD, $frB", IIC_FPGeneral,
2087 [(set f64:$frD, (PPCfre f64:$frB))]>;
2088 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
2089 "fres", "$frD, $frB", IIC_FPGeneral,
2090 [(set f32:$frD, (PPCfre f32:$frB))]>;
2091 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
2092 "frsqrte", "$frD, $frB", IIC_FPGeneral,
2093 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
2094 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
2095 "frsqrtes", "$frD, $frB", IIC_FPGeneral,
2096 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
2099 // XL-Form instructions. condition register logical ops.
2101 let hasSideEffects = 0 in
2102 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
2103 "mcrf $BF, $BFA", IIC_BrMCR>,
2104 PPC970_DGroup_First, PPC970_Unit_CRU;
2106 // FIXME: According to the ISA (section 2.5.1 of version 2.06), the
2107 // condition-register logical instructions have preferred forms. Specifically,
2108 // it is preferred that the bit specified by the BT field be in the same
2109 // condition register as that specified by the bit BB. We might want to account
2110 // for this via hinting the register allocator and anti-dep breakers, or we
2111 // could constrain the register class to force this constraint and then loosen
2112 // it during register allocation via convertToThreeAddress or some similar
2115 let isCommutable = 1 in {
2116 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD),
2117 (ins crbitrc:$CRA, crbitrc:$CRB),
2118 "crand $CRD, $CRA, $CRB", IIC_BrCR,
2119 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>;
2121 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD),
2122 (ins crbitrc:$CRA, crbitrc:$CRB),
2123 "crnand $CRD, $CRA, $CRB", IIC_BrCR,
2124 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>;
2126 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
2127 (ins crbitrc:$CRA, crbitrc:$CRB),
2128 "cror $CRD, $CRA, $CRB", IIC_BrCR,
2129 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>;
2131 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD),
2132 (ins crbitrc:$CRA, crbitrc:$CRB),
2133 "crxor $CRD, $CRA, $CRB", IIC_BrCR,
2134 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>;
2136 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD),
2137 (ins crbitrc:$CRA, crbitrc:$CRB),
2138 "crnor $CRD, $CRA, $CRB", IIC_BrCR,
2139 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>;
2141 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
2142 (ins crbitrc:$CRA, crbitrc:$CRB),
2143 "creqv $CRD, $CRA, $CRB", IIC_BrCR,
2144 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>;
2147 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD),
2148 (ins crbitrc:$CRA, crbitrc:$CRB),
2149 "crandc $CRD, $CRA, $CRB", IIC_BrCR,
2150 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>;
2152 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD),
2153 (ins crbitrc:$CRA, crbitrc:$CRB),
2154 "crorc $CRD, $CRA, $CRB", IIC_BrCR,
2155 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>;
2157 let isCodeGenOnly = 1 in {
2158 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
2159 "creqv $dst, $dst, $dst", IIC_BrCR,
2160 [(set i1:$dst, 1)]>;
2162 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
2163 "crxor $dst, $dst, $dst", IIC_BrCR,
2164 [(set i1:$dst, 0)]>;
2166 let Defs = [CR1EQ], CRD = 6 in {
2167 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
2168 "creqv 6, 6, 6", IIC_BrCR,
2171 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
2172 "crxor 6, 6, 6", IIC_BrCR,
2177 // XFX-Form instructions. Instructions that deal with SPRs.
2180 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2181 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2182 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2183 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2185 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2186 "mftb $RT, $SPR", IIC_SprMFTB>, Deprecated<DeprecatedMFTB>;
2188 // A pseudo-instruction used to implement the read of the 64-bit cycle counter
2189 // on a 32-bit target.
2190 let hasSideEffects = 1, usesCustomInserter = 1 in
2191 def ReadTB : Pseudo<(outs gprc:$lo, gprc:$hi), (ins),
2194 let Uses = [CTR] in {
2195 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
2196 "mfctr $rT", IIC_SprMFSPR>,
2197 PPC970_DGroup_First, PPC970_Unit_FXU;
2199 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
2200 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2201 "mtctr $rS", IIC_SprMTSPR>,
2202 PPC970_DGroup_First, PPC970_Unit_FXU;
2204 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
2205 let Pattern = [(int_ppc_mtctr i32:$rS)] in
2206 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
2207 "mtctr $rS", IIC_SprMTSPR>,
2208 PPC970_DGroup_First, PPC970_Unit_FXU;
2211 let Defs = [LR] in {
2212 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
2213 "mtlr $rS", IIC_SprMTSPR>,
2214 PPC970_DGroup_First, PPC970_Unit_FXU;
2216 let Uses = [LR] in {
2217 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
2218 "mflr $rT", IIC_SprMFSPR>,
2219 PPC970_DGroup_First, PPC970_Unit_FXU;
2222 let isCodeGenOnly = 1 in {
2223 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
2224 // like a GPR on the PPC970. As such, copies in and out have the same
2225 // performance characteristics as an OR instruction.
2226 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
2227 "mtspr 256, $rS", IIC_IntGeneral>,
2228 PPC970_DGroup_Single, PPC970_Unit_FXU;
2229 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
2230 "mfspr $rT, 256", IIC_IntGeneral>,
2231 PPC970_DGroup_First, PPC970_Unit_FXU;
2233 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
2234 (outs VRSAVERC:$reg), (ins gprc:$rS),
2235 "mtspr 256, $rS", IIC_IntGeneral>,
2236 PPC970_DGroup_Single, PPC970_Unit_FXU;
2237 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
2238 (ins VRSAVERC:$reg),
2239 "mfspr $rT, 256", IIC_IntGeneral>,
2240 PPC970_DGroup_First, PPC970_Unit_FXU;
2243 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
2244 // so we'll need to scavenge a register for it.
2246 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
2247 "#SPILL_VRSAVE", []>;
2249 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
2250 // spilled), so we'll need to scavenge a register for it.
2252 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
2253 "#RESTORE_VRSAVE", []>;
2255 let hasSideEffects = 0 in {
2256 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST),
2257 "mtocrf $FXM, $ST", IIC_BrMCRX>,
2258 PPC970_DGroup_First, PPC970_Unit_CRU;
2260 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
2261 "mtcrf $FXM, $rS", IIC_BrMCRX>,
2262 PPC970_MicroCode, PPC970_Unit_CRU;
2264 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
2265 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
2266 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
2267 PPC970_DGroup_First, PPC970_Unit_CRU;
2269 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
2270 "mfcr $rT", IIC_SprMFCR>,
2271 PPC970_MicroCode, PPC970_Unit_CRU;
2272 } // hasSideEffects = 0
2274 // Pseudo instruction to perform FADD in round-to-zero mode.
2275 let usesCustomInserter = 1, Uses = [RM] in {
2276 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
2277 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
2280 // The above pseudo gets expanded to make use of the following instructions
2281 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
2282 let Uses = [RM], Defs = [RM] in {
2283 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
2284 "mtfsb0 $FM", IIC_IntMTFSB0, []>,
2285 PPC970_DGroup_Single, PPC970_Unit_FPU;
2286 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
2287 "mtfsb1 $FM", IIC_IntMTFSB0, []>,
2288 PPC970_DGroup_Single, PPC970_Unit_FPU;
2289 let isCodeGenOnly = 1 in
2290 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
2291 "mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
2292 PPC970_DGroup_Single, PPC970_Unit_FPU;
2294 let Uses = [RM] in {
2295 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2296 "mffs $rT", IIC_IntMFFS,
2297 [(set f64:$rT, (PPCmffs))]>,
2298 PPC970_DGroup_Single, PPC970_Unit_FPU;
2301 def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
2302 "mffs. $rT", IIC_IntMFFS, []>, isDOT;
2306 let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations.
2307 // XO-Form instructions. Arithmetic instructions that can set overflow bit
2308 let isCommutable = 1 in
2309 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2310 "add", "$rT, $rA, $rB", IIC_IntSimple,
2311 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
2312 let isCodeGenOnly = 1 in
2313 def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
2314 "add $rT, $rA, $rB", IIC_IntSimple,
2315 [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
2316 let isCommutable = 1 in
2317 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2318 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
2319 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
2320 PPC970_DGroup_Cracked;
2322 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2323 "divw", "$rT, $rA, $rB", IIC_IntDivW,
2324 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
2325 defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2326 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
2327 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
2328 def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2329 "divwe $rT, $rA, $rB", IIC_IntDivW,
2330 [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
2331 Requires<[HasExtDiv]>;
2333 def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2334 "divwe. $rT, $rA, $rB", IIC_IntDivW,
2335 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2336 Requires<[HasExtDiv]>;
2337 def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2338 "divweu $rT, $rA, $rB", IIC_IntDivW,
2339 [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
2340 Requires<[HasExtDiv]>;
2342 def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2343 "divweu. $rT, $rA, $rB", IIC_IntDivW,
2344 []>, isDOT, PPC970_DGroup_Cracked, PPC970_DGroup_First,
2345 Requires<[HasExtDiv]>;
2346 let isCommutable = 1 in {
2347 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2348 "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
2349 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
2350 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2351 "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
2352 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
2353 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2354 "mullw", "$rT, $rA, $rB", IIC_IntMulHW,
2355 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
2357 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2358 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
2359 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
2360 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2361 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
2362 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
2363 PPC970_DGroup_Cracked;
2364 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
2365 "neg", "$rT, $rA", IIC_IntSimple,
2366 [(set i32:$rT, (ineg i32:$rA))]>;
2367 let Uses = [CARRY] in {
2368 let isCommutable = 1 in
2369 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2370 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
2371 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
2372 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
2373 "addme", "$rT, $rA", IIC_IntGeneral,
2374 [(set i32:$rT, (adde i32:$rA, -1))]>;
2375 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
2376 "addze", "$rT, $rA", IIC_IntGeneral,
2377 [(set i32:$rT, (adde i32:$rA, 0))]>;
2378 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
2379 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
2380 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
2381 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
2382 "subfme", "$rT, $rA", IIC_IntGeneral,
2383 [(set i32:$rT, (sube -1, i32:$rA))]>;
2384 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
2385 "subfze", "$rT, $rA", IIC_IntGeneral,
2386 [(set i32:$rT, (sube 0, i32:$rA))]>;
2390 // A-Form instructions. Most of the instructions executed in the FPU are of
2393 let PPC970_Unit = 3, hasSideEffects = 0 in { // FPU Operations.
2394 let Uses = [RM] in {
2395 let isCommutable = 1 in {
2396 defm FMADD : AForm_1r<63, 29,
2397 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2398 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2399 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2400 defm FMADDS : AForm_1r<59, 29,
2401 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2402 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2403 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2404 defm FMSUB : AForm_1r<63, 28,
2405 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2406 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2408 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2409 defm FMSUBS : AForm_1r<59, 28,
2410 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2411 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2413 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
2414 defm FNMADD : AForm_1r<63, 31,
2415 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2416 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2418 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
2419 defm FNMADDS : AForm_1r<59, 31,
2420 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2421 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2423 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
2424 defm FNMSUB : AForm_1r<63, 30,
2425 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2426 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2427 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
2428 (fneg f64:$FRB))))]>;
2429 defm FNMSUBS : AForm_1r<59, 30,
2430 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2431 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2432 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
2433 (fneg f32:$FRB))))]>;
2436 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
2437 // having 4 of these, force the comparison to always be an 8-byte double (code
2438 // should use an FMRSD if the input comparison value really wants to be a float)
2439 // and 4/8 byte forms for the result and operand type..
2440 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
2441 defm FSELD : AForm_1r<63, 23,
2442 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2443 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2444 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
2445 defm FSELS : AForm_1r<63, 23,
2446 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2447 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2448 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
2449 let Uses = [RM] in {
2450 let isCommutable = 1 in {
2451 defm FADD : AForm_2r<63, 21,
2452 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2453 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2454 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
2455 defm FADDS : AForm_2r<59, 21,
2456 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2457 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2458 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
2460 defm FDIV : AForm_2r<63, 18,
2461 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2462 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD,
2463 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
2464 defm FDIVS : AForm_2r<59, 18,
2465 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2466 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS,
2467 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
2468 let isCommutable = 1 in {
2469 defm FMUL : AForm_3r<63, 25,
2470 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2471 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2472 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
2473 defm FMULS : AForm_3r<59, 25,
2474 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2475 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
2476 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
2478 defm FSUB : AForm_2r<63, 20,
2479 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
2480 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub,
2481 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
2482 defm FSUBS : AForm_2r<59, 20,
2483 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
2484 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral,
2485 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
2489 let hasSideEffects = 0 in {
2490 let PPC970_Unit = 1 in { // FXU Operations.
2492 def ISEL : AForm_4<31, 15,
2493 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
2494 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
2498 let PPC970_Unit = 1 in { // FXU Operations.
2499 // M-Form instructions. rotate and mask instructions.
2501 let isCommutable = 1 in {
2502 // RLWIMI can be commuted if the rotate amount is zero.
2503 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
2504 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
2505 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
2506 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
2507 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
2509 let BaseName = "rlwinm" in {
2510 def RLWINM : MForm_2<21,
2511 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2512 "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2515 def RLWINMo : MForm_2<21,
2516 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
2517 "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
2518 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
2520 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
2521 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
2522 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
2525 } // hasSideEffects = 0
2527 //===----------------------------------------------------------------------===//
2528 // PowerPC Instruction Patterns
2531 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2532 def : Pat<(i32 imm:$imm),
2533 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2535 // Implement the 'not' operation with the NOR instruction.
2536 def i32not : OutPatFrag<(ops node:$in),
2538 def : Pat<(not i32:$in),
2541 // ADD an arbitrary immediate.
2542 def : Pat<(add i32:$in, imm:$imm),
2543 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2544 // OR an arbitrary immediate.
2545 def : Pat<(or i32:$in, imm:$imm),
2546 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2547 // XOR an arbitrary immediate.
2548 def : Pat<(xor i32:$in, imm:$imm),
2549 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2551 def : Pat<(sub imm32SExt16:$imm, i32:$in),
2552 (SUBFIC $in, imm:$imm)>;
2555 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2556 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2557 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2558 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2561 def : Pat<(rotl i32:$in, i32:$sh),
2562 (RLWNM $in, $sh, 0, 31)>;
2563 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2564 (RLWINM $in, imm:$imm, 0, 31)>;
2567 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2568 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2571 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2572 (BL tglobaladdr:$dst)>;
2573 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2574 (BL texternalsym:$dst)>;
2576 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2577 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2579 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2580 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2582 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2583 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2587 // Hi and Lo for Darwin Global Addresses.
2588 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2589 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2590 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2591 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2592 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2593 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2594 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2595 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2596 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2597 (ADDIS $in, tglobaltlsaddr:$g)>;
2598 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2599 (ADDI $in, tglobaltlsaddr:$g)>;
2600 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2601 (ADDIS $in, tglobaladdr:$g)>;
2602 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2603 (ADDIS $in, tconstpool:$g)>;
2604 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2605 (ADDIS $in, tjumptable:$g)>;
2606 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2607 (ADDIS $in, tblockaddress:$g)>;
2609 // Support for thread-local storage.
2610 def PPC32GOT: Pseudo<(outs gprc:$rD), (ins), "#PPC32GOT",
2611 [(set i32:$rD, (PPCppc32GOT))]>;
2613 // Get the _GLOBAL_OFFSET_TABLE_ in PIC mode.
2614 // This uses two output registers, the first as the real output, the second as a
2615 // temporary register, used internally in code generation.
2616 def PPC32PICGOT: Pseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT",
2617 []>, NoEncode<"$rT">;
2619 def LDgotTprelL32: Pseudo<(outs gprc:$rD), (ins s16imm:$disp, gprc_nor0:$reg),
2622 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>;
2623 def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g),
2624 (ADD4TLS $in, tglobaltlsaddr:$g)>;
2626 def ADDItlsgdL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2629 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>;
2630 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2631 // explicitly defined when this op is created, so not mentioned here.
2632 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2633 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2634 def GETtlsADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2637 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>;
2638 // Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR
2639 // are true defines while the rest of the Defs are clobbers.
2640 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2641 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2642 def ADDItlsgdLADDR32 : Pseudo<(outs gprc:$rD),
2643 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2644 "#ADDItlsgdLADDR32",
2646 (PPCaddiTlsgdLAddr i32:$reg,
2647 tglobaltlsaddr:$disp,
2648 tglobaltlsaddr:$sym))]>;
2649 def ADDItlsldL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2652 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>;
2653 // LR is a true define, while the rest of the Defs are clobbers. R3 is
2654 // explicitly defined when this op is created, so not mentioned here.
2655 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2656 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2657 def GETtlsldADDR32 : Pseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym),
2660 (PPCgetTlsldAddr i32:$reg,
2661 tglobaltlsaddr:$sym))]>;
2662 // Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR
2663 // are true defines while the rest of the Defs are clobbers.
2664 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2665 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in
2666 def ADDItlsldLADDR32 : Pseudo<(outs gprc:$rD),
2667 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym),
2668 "#ADDItlsldLADDR32",
2670 (PPCaddiTlsldLAddr i32:$reg,
2671 tglobaltlsaddr:$disp,
2672 tglobaltlsaddr:$sym))]>;
2673 def ADDIdtprelL32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2676 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>;
2677 def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
2680 (PPCaddisDtprelHA i32:$reg,
2681 tglobaltlsaddr:$disp))]>;
2683 // Support for Position-independent code
2684 def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
2687 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
2688 // Get Global (GOT) Base Register offset, from the word immediately preceding
2689 // the function label.
2690 def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
2693 // Standard shifts. These are represented separately from the real shifts above
2694 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2696 def : Pat<(sra i32:$rS, i32:$rB),
2698 def : Pat<(srl i32:$rS, i32:$rB),
2700 def : Pat<(shl i32:$rS, i32:$rB),
2703 def : Pat<(zextloadi1 iaddr:$src),
2705 def : Pat<(zextloadi1 xaddr:$src),
2707 def : Pat<(extloadi1 iaddr:$src),
2709 def : Pat<(extloadi1 xaddr:$src),
2711 def : Pat<(extloadi8 iaddr:$src),
2713 def : Pat<(extloadi8 xaddr:$src),
2715 def : Pat<(extloadi16 iaddr:$src),
2717 def : Pat<(extloadi16 xaddr:$src),
2719 def : Pat<(f64 (extloadf32 iaddr:$src)),
2720 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2721 def : Pat<(f64 (extloadf32 xaddr:$src)),
2722 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2724 def : Pat<(f64 (fextend f32:$src)),
2725 (COPY_TO_REGCLASS $src, F8RC)>;
2727 // Only seq_cst fences require the heavyweight sync (SYNC 0).
2728 // All others can use the lightweight sync (SYNC 1).
2729 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
2730 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
2731 // versions of Power.
2732 def : Pat<(atomic_fence (i64 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2733 def : Pat<(atomic_fence (i32 7), (imm)), (SYNC 0)>, Requires<[HasSYNC]>;
2734 def : Pat<(atomic_fence (imm), (imm)), (SYNC 1)>, Requires<[HasSYNC]>;
2735 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
2737 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2738 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2739 (FNMSUB $A, $C, $B)>;
2740 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2741 (FNMSUB $A, $C, $B)>;
2742 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2743 (FNMSUBS $A, $C, $B)>;
2744 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2745 (FNMSUBS $A, $C, $B)>;
2747 // FCOPYSIGN's operand types need not agree.
2748 def : Pat<(fcopysign f64:$frB, f32:$frA),
2749 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
2750 def : Pat<(fcopysign f32:$frB, f64:$frA),
2751 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
2753 include "PPCInstrAltivec.td"
2754 include "PPCInstrSPE.td"
2755 include "PPCInstr64Bit.td"
2756 include "PPCInstrVSX.td"
2757 include "PPCInstrQPX.td"
2758 include "PPCInstrHTM.td"
2760 def crnot : OutPatFrag<(ops node:$in),
2762 def : Pat<(not i1:$in),
2765 // Patterns for arithmetic i1 operations.
2766 def : Pat<(add i1:$a, i1:$b),
2768 def : Pat<(sub i1:$a, i1:$b),
2770 def : Pat<(mul i1:$a, i1:$b),
2773 // We're sometimes asked to materialize i1 -1, which is just 1 in this case
2774 // (-1 is used to mean all bits set).
2775 def : Pat<(i1 -1), (CRSET)>;
2777 // i1 extensions, implemented in terms of isel.
2778 def : Pat<(i32 (zext i1:$in)),
2779 (SELECT_I4 $in, (LI 1), (LI 0))>;
2780 def : Pat<(i32 (sext i1:$in)),
2781 (SELECT_I4 $in, (LI -1), (LI 0))>;
2783 def : Pat<(i64 (zext i1:$in)),
2784 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2785 def : Pat<(i64 (sext i1:$in)),
2786 (SELECT_I8 $in, (LI8 -1), (LI8 0))>;
2788 // FIXME: We should choose either a zext or a sext based on other constants
2790 def : Pat<(i32 (anyext i1:$in)),
2791 (SELECT_I4 $in, (LI 1), (LI 0))>;
2792 def : Pat<(i64 (anyext i1:$in)),
2793 (SELECT_I8 $in, (LI8 1), (LI8 0))>;
2795 // match setcc on i1 variables.
2796 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
2798 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
2800 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
2802 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
2804 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
2806 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
2808 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
2810 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
2812 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
2814 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
2817 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
2818 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
2819 // floating-point types.
2821 multiclass CRNotPat<dag pattern, dag result> {
2822 def : Pat<pattern, (crnot result)>;
2823 def : Pat<(not pattern), result>;
2825 // We can also fold the crnot into an extension:
2826 def : Pat<(i32 (zext pattern)),
2827 (SELECT_I4 result, (LI 0), (LI 1))>;
2828 def : Pat<(i32 (sext pattern)),
2829 (SELECT_I4 result, (LI 0), (LI -1))>;
2831 // We can also fold the crnot into an extension:
2832 def : Pat<(i64 (zext pattern)),
2833 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2834 def : Pat<(i64 (sext pattern)),
2835 (SELECT_I8 result, (LI8 0), (LI8 -1))>;
2837 // FIXME: We should choose either a zext or a sext based on other constants
2839 def : Pat<(i32 (anyext pattern)),
2840 (SELECT_I4 result, (LI 0), (LI 1))>;
2842 def : Pat<(i64 (anyext pattern)),
2843 (SELECT_I8 result, (LI8 0), (LI8 1))>;
2846 // FIXME: Because of what seems like a bug in TableGen's type-inference code,
2847 // we need to write imm:$imm in the output patterns below, not just $imm, or
2848 // else the resulting matcher will not correctly add the immediate operand
2849 // (making it a register operand instead).
2852 multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag,
2853 OutPatFrag rfrag, OutPatFrag rfrag8> {
2854 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))),
2856 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))),
2858 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))),
2859 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2860 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))),
2861 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2863 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))),
2865 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))),
2867 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))),
2868 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>;
2869 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))),
2870 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
2873 // Note that we do all inversions below with i(32|64)not, instead of using
2874 // (xori x, 1) because on the A2 nor has single-cycle latency while xori
2875 // has 2-cycle latency.
2877 defm : ExtSetCCPat<SETEQ,
2878 PatFrag<(ops node:$in, node:$cc),
2879 (setcc $in, 0, $cc)>,
2880 OutPatFrag<(ops node:$in),
2881 (RLWINM (CNTLZW $in), 27, 31, 31)>,
2882 OutPatFrag<(ops node:$in),
2883 (RLDICL (CNTLZD $in), 58, 63)> >;
2885 defm : ExtSetCCPat<SETNE,
2886 PatFrag<(ops node:$in, node:$cc),
2887 (setcc $in, 0, $cc)>,
2888 OutPatFrag<(ops node:$in),
2889 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>,
2890 OutPatFrag<(ops node:$in),
2891 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >;
2893 defm : ExtSetCCPat<SETLT,
2894 PatFrag<(ops node:$in, node:$cc),
2895 (setcc $in, 0, $cc)>,
2896 OutPatFrag<(ops node:$in),
2897 (RLWINM $in, 1, 31, 31)>,
2898 OutPatFrag<(ops node:$in),
2899 (RLDICL $in, 1, 63)> >;
2901 defm : ExtSetCCPat<SETGE,
2902 PatFrag<(ops node:$in, node:$cc),
2903 (setcc $in, 0, $cc)>,
2904 OutPatFrag<(ops node:$in),
2905 (RLWINM (i32not $in), 1, 31, 31)>,
2906 OutPatFrag<(ops node:$in),
2907 (RLDICL (i64not $in), 1, 63)> >;
2909 defm : ExtSetCCPat<SETGT,
2910 PatFrag<(ops node:$in, node:$cc),
2911 (setcc $in, 0, $cc)>,
2912 OutPatFrag<(ops node:$in),
2913 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>,
2914 OutPatFrag<(ops node:$in),
2915 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >;
2917 defm : ExtSetCCPat<SETLE,
2918 PatFrag<(ops node:$in, node:$cc),
2919 (setcc $in, 0, $cc)>,
2920 OutPatFrag<(ops node:$in),
2921 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>,
2922 OutPatFrag<(ops node:$in),
2923 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >;
2925 defm : ExtSetCCPat<SETLT,
2926 PatFrag<(ops node:$in, node:$cc),
2927 (setcc $in, -1, $cc)>,
2928 OutPatFrag<(ops node:$in),
2929 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>,
2930 OutPatFrag<(ops node:$in),
2931 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2933 defm : ExtSetCCPat<SETGE,
2934 PatFrag<(ops node:$in, node:$cc),
2935 (setcc $in, -1, $cc)>,
2936 OutPatFrag<(ops node:$in),
2937 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>,
2938 OutPatFrag<(ops node:$in),
2939 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >;
2941 defm : ExtSetCCPat<SETGT,
2942 PatFrag<(ops node:$in, node:$cc),
2943 (setcc $in, -1, $cc)>,
2944 OutPatFrag<(ops node:$in),
2945 (RLWINM (i32not $in), 1, 31, 31)>,
2946 OutPatFrag<(ops node:$in),
2947 (RLDICL (i64not $in), 1, 63)> >;
2949 defm : ExtSetCCPat<SETLE,
2950 PatFrag<(ops node:$in, node:$cc),
2951 (setcc $in, -1, $cc)>,
2952 OutPatFrag<(ops node:$in),
2953 (RLWINM $in, 1, 31, 31)>,
2954 OutPatFrag<(ops node:$in),
2955 (RLDICL $in, 1, 63)> >;
2958 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
2959 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2960 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)),
2961 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2962 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
2963 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2964 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)),
2965 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2966 def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)),
2967 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2968 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)),
2969 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2971 // For non-equality comparisons, the default code would materialize the
2972 // constant, then compare against it, like this:
2974 // ori r2, r2, 22136
2977 // Since we are just comparing for equality, we can emit this instead:
2978 // xoris r0,r3,0x1234
2979 // cmplwi cr0,r0,0x5678
2982 def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)),
2983 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
2984 (LO16 imm:$imm)), sub_eq)>;
2986 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
2987 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
2988 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)),
2989 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
2990 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
2991 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
2992 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)),
2993 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
2994 defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)),
2995 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
2996 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)),
2997 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
2999 defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
3000 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3001 (LO16 imm:$imm)), sub_eq)>;
3003 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3004 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3005 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)),
3006 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3007 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3008 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3009 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)),
3010 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3011 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)),
3012 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3014 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3015 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>;
3016 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)),
3017 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>;
3018 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3019 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>;
3020 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)),
3021 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>;
3022 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)),
3023 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>;
3026 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3027 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3028 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)),
3029 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3030 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3031 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3032 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)),
3033 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3034 def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)),
3035 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3036 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)),
3037 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3039 // For non-equality comparisons, the default code would materialize the
3040 // constant, then compare against it, like this:
3042 // ori r2, r2, 22136
3045 // Since we are just comparing for equality, we can emit this instead:
3046 // xoris r0,r3,0x1234
3047 // cmpldi cr0,r0,0x5678
3050 def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)),
3051 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3052 (LO16 imm:$imm)), sub_eq)>;
3054 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3055 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>;
3056 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)),
3057 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>;
3058 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3059 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>;
3060 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)),
3061 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>;
3062 defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)),
3063 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>;
3064 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)),
3065 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>;
3067 defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
3068 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)),
3069 (LO16 imm:$imm)), sub_eq)>;
3071 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3072 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3073 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)),
3074 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3075 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3076 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3077 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)),
3078 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3079 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)),
3080 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3082 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3083 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>;
3084 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)),
3085 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>;
3086 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3087 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>;
3088 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)),
3089 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>;
3090 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)),
3091 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>;
3094 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOLT)),
3095 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3096 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETLT)),
3097 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3098 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOGT)),
3099 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3100 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
3101 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3102 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
3103 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3104 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
3105 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3106 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
3107 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3109 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
3110 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3111 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
3112 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
3113 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
3114 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3115 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),
3116 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
3117 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUNE)),
3118 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3119 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETNE)),
3120 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
3121 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETO)),
3122 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
3125 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOLT)),
3126 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3127 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETLT)),
3128 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3129 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOGT)),
3130 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3131 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
3132 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3133 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
3134 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3135 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
3136 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3137 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
3138 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3140 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
3141 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3142 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
3143 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
3144 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
3145 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3146 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),
3147 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
3148 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUNE)),
3149 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3150 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETNE)),
3151 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
3152 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETO)),
3153 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
3155 // match select on i1 variables:
3156 def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)),
3157 (CROR (CRAND $cond , $tval),
3158 (CRAND (crnot $cond), $fval))>;
3160 // match selectcc on i1 variables:
3161 // select (lhs == rhs), tval, fval is:
3162 // ((lhs == rhs) & tval) | (!(lhs == rhs) & fval)
3163 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)),
3164 (CROR (CRAND (CRANDC $rhs, $lhs), $tval),
3165 (CRAND (CRORC $lhs, $rhs), $fval))>;
3166 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)),
3167 (CROR (CRAND (CRORC $rhs, $lhs), $tval),
3168 (CRAND (CRANDC $lhs, $rhs), $fval))>;
3169 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)),
3170 (CROR (CRAND (CREQV $lhs, $rhs), $tval),
3171 (CRAND (CRXOR $lhs, $rhs), $fval))>;
3172 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)),
3173 (CROR (CRAND (CRORC $lhs, $rhs), $tval),
3174 (CRAND (CRANDC $rhs, $lhs), $fval))>;
3175 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)),
3176 (CROR (CRAND (CRANDC $lhs, $rhs), $tval),
3177 (CRAND (CRORC $rhs, $lhs), $fval))>;
3178 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)),
3179 (CROR (CRAND (CREQV $lhs, $rhs), $fval),
3180 (CRAND (CRXOR $lhs, $rhs), $tval))>;
3182 // match selectcc on i1 variables with non-i1 output.
3183 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)),
3184 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3185 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)),
3186 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>;
3187 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)),
3188 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>;
3189 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)),
3190 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>;
3191 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)),
3192 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3193 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)),
3194 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3196 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)),
3197 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3198 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)),
3199 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>;
3200 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)),
3201 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>;
3202 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)),
3203 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>;
3204 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)),
3205 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3206 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)),
3207 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3209 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)),
3210 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>;
3211 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)),
3212 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>;
3213 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)),
3214 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>;
3215 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)),
3216 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>;
3217 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)),
3218 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>;
3219 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)),
3220 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>;
3222 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)),
3223 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>;
3224 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)),
3225 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>;
3226 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)),
3227 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>;
3228 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)),
3229 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>;
3230 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)),
3231 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>;
3232 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
3233 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>;
3235 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)),
3236 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>;
3237 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)),
3238 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>;
3239 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)),
3240 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>;
3241 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)),
3242 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>;
3243 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)),
3244 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>;
3245 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
3246 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
3248 let usesCustomInserter = 1 in {
3249 def ANDIo_1_EQ_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3251 [(set i1:$dst, (trunc (not i32:$in)))]>;
3252 def ANDIo_1_GT_BIT : Pseudo<(outs crbitrc:$dst), (ins gprc:$in),
3254 [(set i1:$dst, (trunc i32:$in))]>;
3256 def ANDIo_1_EQ_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3258 [(set i1:$dst, (trunc (not i64:$in)))]>;
3259 def ANDIo_1_GT_BIT8 : Pseudo<(outs crbitrc:$dst), (ins g8rc:$in),
3261 [(set i1:$dst, (trunc i64:$in))]>;
3264 def : Pat<(i1 (not (trunc i32:$in))),
3265 (ANDIo_1_EQ_BIT $in)>;
3266 def : Pat<(i1 (not (trunc i64:$in))),
3267 (ANDIo_1_EQ_BIT8 $in)>;
3269 //===----------------------------------------------------------------------===//
3270 // PowerPC Instructions used for assembler/disassembler only
3273 // FIXME: For B=0 or B > 8, the registers following RT are used.
3274 // WARNING: Do not add patterns for this instruction without fixing this.
3275 def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
3276 "lswi $RT, $A, $B", IIC_LdStLoad, []>;
3278 // FIXME: For B=0 or B > 8, the registers following RT are used.
3279 // WARNING: Do not add patterns for this instruction without fixing this.
3280 def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
3281 "stswi $RT, $A, $B", IIC_LdStLoad, []>;
3283 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
3284 "isync", IIC_SprISYNC, []>;
3286 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
3287 "icbi $src", IIC_LdStICBI, []>;
3289 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
3290 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
3291 "eieio", IIC_LdStLoad, []>;
3293 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L),
3294 "wait $L", IIC_LdStLoad, []>;
3296 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
3297 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
3299 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
3300 "mtsr $SR, $RS", IIC_SprMTSR>;
3302 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
3303 "mfsr $RS, $SR", IIC_SprMFSR>;
3305 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
3306 "mtsrin $RS, $RB", IIC_SprMTSR>;
3308 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
3309 "mfsrin $RS, $RB", IIC_SprMFSR>;
3311 def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
3312 "mtmsr $RS, $L", IIC_SprMTMSR>;
3314 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
3315 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
3319 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,
3320 Requires<[IsBookE]> {
3324 let Inst{21-30} = 163;
3327 def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B),
3328 "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3329 def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B),
3330 "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>;
3332 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3333 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
3334 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3335 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
3337 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
3338 "mfmsr $RT", IIC_SprMFMSR, []>;
3340 def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
3341 "mtmsrd $RS, $L", IIC_SprMTMSRD>;
3343 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
3344 "mcrfs $BF, $BFA", IIC_BrMCR>;
3346 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3347 "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
3349 def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
3350 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
3352 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
3353 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
3355 def MTFSF : XFLForm_1<63, 711, (outs),
3356 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3357 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
3358 def MTFSFo : XFLForm_1<63, 711, (outs),
3359 (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
3360 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
3362 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3363 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
3365 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
3366 "slbie $RB", IIC_SprSLBIE, []>;
3368 def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB),
3369 "slbmte $RS, $RB", IIC_SprSLBMTE, []>;
3371 def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB),
3372 "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>;
3374 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
3376 def TLBIA : XForm_0<31, 370, (outs), (ins),
3377 "tlbia", IIC_SprTLBIA, []>;
3379 def TLBSYNC : XForm_0<31, 566, (outs), (ins),
3380 "tlbsync", IIC_SprTLBSYNC, []>;
3382 def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB),
3383 "tlbiel $RB", IIC_SprTLBIEL, []>;
3385 def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB),
3386 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3387 def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB),
3388 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>;
3390 def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB),
3391 "tlbie $RB,$RS", IIC_SprTLBIE, []>;
3393 def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B",
3394 IIC_LdStLoad>, Requires<[IsBookE]>;
3396 def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B",
3397 IIC_LdStLoad>, Requires<[IsBookE]>;
3399 def TLBRE : XForm_24_eieio<31, 946, (outs), (ins),
3400 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3402 def TLBWE : XForm_24_eieio<31, 978, (outs), (ins),
3403 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>;
3405 def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS),
3406 "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3408 def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS),
3409 "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>;
3411 def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3412 "tlbsx $RST, $A, $B", IIC_LdStLoad, []>,
3413 Requires<[IsPPC4xx]>;
3414 def TLBSX2D : XForm_base_r3xo<31, 914, (outs),
3415 (ins gprc:$RST, gprc:$A, gprc:$B),
3416 "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>,
3417 Requires<[IsPPC4xx]>, isDOT;
3419 def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>;
3421 def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>,
3422 Requires<[IsBookE]>;
3423 def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>,
3424 Requires<[IsBookE]>;
3426 def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>,
3428 def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>,
3431 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3432 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3433 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
3434 "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>;
3436 def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>;
3438 def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3439 "lbzcix $RST, $A, $B", IIC_LdStLoad, []>;
3440 def LHZCIX : XForm_base_r3xo<31, 821, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3441 "lhzcix $RST, $A, $B", IIC_LdStLoad, []>;
3442 def LWZCIX : XForm_base_r3xo<31, 789, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3443 "lwzcix $RST, $A, $B", IIC_LdStLoad, []>;
3444 def LDCIX : XForm_base_r3xo<31, 885, (outs gprc:$RST), (ins gprc:$A, gprc:$B),
3445 "ldcix $RST, $A, $B", IIC_LdStLoad, []>;
3447 def STBCIX : XForm_base_r3xo<31, 981, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3448 "stbcix $RST, $A, $B", IIC_LdStLoad, []>;
3449 def STHCIX : XForm_base_r3xo<31, 949, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3450 "sthcix $RST, $A, $B", IIC_LdStLoad, []>;
3451 def STWCIX : XForm_base_r3xo<31, 917, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3452 "stwcix $RST, $A, $B", IIC_LdStLoad, []>;
3453 def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B),
3454 "stdcix $RST, $A, $B", IIC_LdStLoad, []>;
3456 //===----------------------------------------------------------------------===//
3457 // PowerPC Assembler Instruction Aliases
3460 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
3461 // These are aliases that require C++ handling to convert to the target
3462 // instruction, while InstAliases can be handled directly by tblgen.
3463 class PPCAsmPseudo<string asm, dag iops>
3465 let Namespace = "PPC";
3466 bit PPC64 = 0; // Default value, override with isPPC64
3468 let OutOperandList = (outs);
3469 let InOperandList = iops;
3471 let AsmString = asm;
3472 let isAsmParserOnly = 1;
3476 def : InstAlias<"sc", (SC 0)>;
3478 def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>;
3479 def : InstAlias<"msync", (SYNC 0)>, Requires<[HasSYNC]>;
3480 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>;
3481 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>;
3483 def : InstAlias<"wait", (WAIT 0)>;
3484 def : InstAlias<"waitrsv", (WAIT 1)>;
3485 def : InstAlias<"waitimpl", (WAIT 2)>;
3487 def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>;
3489 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3490 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
3491 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3492 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
3494 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
3495 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
3497 def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>;
3498 def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>;
3500 def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>;
3501 def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>;
3503 def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>;
3504 def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>;
3506 def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>;
3507 def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>;
3509 def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>;
3510 def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>;
3512 def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>;
3513 def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>;
3515 def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>;
3516 def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>;
3518 def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>;
3519 def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>;
3521 def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3522 def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>;
3524 def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3525 def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>;
3527 def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>;
3528 def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>;
3530 def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>;
3531 def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>;
3533 def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>;
3534 def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>;
3536 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
3537 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
3538 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
3540 def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>;
3541 def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>;
3543 def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>;
3544 def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3545 def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>;
3546 def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3548 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
3550 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3551 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3553 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3554 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
3556 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
3558 foreach BATR = 0-3 in {
3559 def : InstAlias<"mtdbatu "#BATR#", $Rx",
3560 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>,
3561 Requires<[IsPPC6xx]>;
3562 def : InstAlias<"mfdbatu $Rx, "#BATR,
3563 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>,
3564 Requires<[IsPPC6xx]>;
3565 def : InstAlias<"mtdbatl "#BATR#", $Rx",
3566 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>,
3567 Requires<[IsPPC6xx]>;
3568 def : InstAlias<"mfdbatl $Rx, "#BATR,
3569 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>,
3570 Requires<[IsPPC6xx]>;
3571 def : InstAlias<"mtibatu "#BATR#", $Rx",
3572 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>,
3573 Requires<[IsPPC6xx]>;
3574 def : InstAlias<"mfibatu $Rx, "#BATR,
3575 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>,
3576 Requires<[IsPPC6xx]>;
3577 def : InstAlias<"mtibatl "#BATR#", $Rx",
3578 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>,
3579 Requires<[IsPPC6xx]>;
3580 def : InstAlias<"mfibatl $Rx, "#BATR,
3581 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>,
3582 Requires<[IsPPC6xx]>;
3585 foreach BR = 0-7 in {
3586 def : InstAlias<"mfbr"#BR#" $Rx",
3587 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
3588 Requires<[IsPPC4xx]>;
3589 def : InstAlias<"mtbr"#BR#" $Rx",
3590 (MTDCR gprc:$Rx, !add(BR, 0x80))>,
3591 Requires<[IsPPC4xx]>;
3594 def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3595 def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>;
3597 def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3598 def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>;
3600 def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3601 def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>;
3603 def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3604 def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>;
3606 def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>;
3607 def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>;
3609 def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>;
3610 def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>;
3612 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>;
3614 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm",
3615 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3616 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm",
3617 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3618 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
3619 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3620 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
3621 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
3623 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3624 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3625 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3626 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
3628 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
3629 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
3631 def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>;
3632 def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>;
3634 foreach SPRG = 0-3 in {
3635 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>;
3636 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>;
3637 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3638 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>;
3640 foreach SPRG = 4-7 in {
3641 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>,
3642 Requires<[IsBookE]>;
3643 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>,
3644 Requires<[IsBookE]>;
3645 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3646 Requires<[IsBookE]>;
3647 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>,
3648 Requires<[IsBookE]>;
3651 def : InstAlias<"mtasr $RS", (MTSPR 280, gprc:$RS)>;
3653 def : InstAlias<"mfdec $RT", (MFSPR gprc:$RT, 22)>;
3654 def : InstAlias<"mtdec $RT", (MTSPR 22, gprc:$RT)>;
3656 def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>;
3658 def : InstAlias<"mfsdr1 $RT", (MFSPR gprc:$RT, 25)>;
3659 def : InstAlias<"mtsdr1 $RT", (MTSPR 25, gprc:$RT)>;
3661 def : InstAlias<"mfsrr0 $RT", (MFSPR gprc:$RT, 26)>;
3662 def : InstAlias<"mfsrr1 $RT", (MFSPR gprc:$RT, 27)>;
3663 def : InstAlias<"mtsrr0 $RT", (MTSPR 26, gprc:$RT)>;
3664 def : InstAlias<"mtsrr1 $RT", (MTSPR 27, gprc:$RT)>;
3666 def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>;
3668 def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>,
3669 Requires<[IsPPC4xx]>;
3670 def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>,
3671 Requires<[IsPPC4xx]>;
3672 def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>,
3673 Requires<[IsPPC4xx]>;
3674 def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>,
3675 Requires<[IsPPC4xx]>;
3677 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
3678 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3679 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
3680 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3681 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
3682 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3683 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
3684 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3685 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
3686 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3687 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
3688 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3689 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
3690 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3691 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
3692 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
3693 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
3694 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3695 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
3696 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3697 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
3698 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3699 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
3700 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3701 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
3702 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3703 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
3704 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3705 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
3706 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3707 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
3708 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
3709 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
3710 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3711 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
3712 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
3714 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3715 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
3716 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3717 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
3718 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3719 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
3721 def : InstAlias<"cntlz $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
3722 def : InstAlias<"cntlz. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
3724 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
3725 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3726 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
3727 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3728 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
3729 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3730 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
3731 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3732 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
3733 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3734 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
3735 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
3736 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
3737 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3738 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
3739 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3740 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
3741 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3742 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
3743 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3744 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
3745 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3746 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
3747 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3748 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
3749 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3750 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
3751 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
3752 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
3753 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3754 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
3755 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
3757 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3758 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
3759 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3760 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
3761 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3762 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
3764 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
3765 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3766 def RLWINMobm : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b",
3767 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3768 def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b",
3769 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3770 def RLWIMIobm : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b",
3771 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3772 def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b",
3773 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3774 def RLWNMobm : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b",
3775 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>;
3777 // These generic branch instruction forms are used for the assembler parser only.
3778 // Defs and Uses are conservative, since we don't know the BO value.
3779 let PPC970_Unit = 7 in {
3780 let Defs = [CTR], Uses = [CTR, RM] in {
3781 def gBC : BForm_3<16, 0, 0, (outs),
3782 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3783 "bc $bo, $bi, $dst">;
3784 def gBCA : BForm_3<16, 1, 0, (outs),
3785 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3786 "bca $bo, $bi, $dst">;
3788 let Defs = [LR, CTR], Uses = [CTR, RM] in {
3789 def gBCL : BForm_3<16, 0, 1, (outs),
3790 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst),
3791 "bcl $bo, $bi, $dst">;
3792 def gBCLA : BForm_3<16, 1, 1, (outs),
3793 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst),
3794 "bcla $bo, $bi, $dst">;
3796 let Defs = [CTR], Uses = [CTR, LR, RM] in
3797 def gBCLR : XLForm_2<19, 16, 0, (outs),
3798 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3799 "bclr $bo, $bi, $bh", IIC_BrB, []>;
3800 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3801 def gBCLRL : XLForm_2<19, 16, 1, (outs),
3802 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3803 "bclrl $bo, $bi, $bh", IIC_BrB, []>;
3804 let Defs = [CTR], Uses = [CTR, LR, RM] in
3805 def gBCCTR : XLForm_2<19, 528, 0, (outs),
3806 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3807 "bcctr $bo, $bi, $bh", IIC_BrB, []>;
3808 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
3809 def gBCCTRL : XLForm_2<19, 528, 1, (outs),
3810 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh),
3811 "bcctrl $bo, $bi, $bh", IIC_BrB, []>;
3813 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>;
3814 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>;
3815 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>;
3816 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>;
3818 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> {
3819 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>;
3820 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3821 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>;
3822 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>;
3823 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>;
3824 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>;
3826 multiclass BranchSimpleMnemonic2<string name, string pm, int bo>
3827 : BranchSimpleMnemonic1<name, pm, bo> {
3828 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>;
3829 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>;
3831 defm : BranchSimpleMnemonic2<"t", "", 12>;
3832 defm : BranchSimpleMnemonic2<"f", "", 4>;
3833 defm : BranchSimpleMnemonic2<"t", "-", 14>;
3834 defm : BranchSimpleMnemonic2<"f", "-", 6>;
3835 defm : BranchSimpleMnemonic2<"t", "+", 15>;
3836 defm : BranchSimpleMnemonic2<"f", "+", 7>;
3837 defm : BranchSimpleMnemonic1<"dnzt", "", 8>;
3838 defm : BranchSimpleMnemonic1<"dnzf", "", 0>;
3839 defm : BranchSimpleMnemonic1<"dzt", "", 10>;
3840 defm : BranchSimpleMnemonic1<"dzf", "", 2>;
3842 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> {
3843 def : InstAlias<"b"#name#pm#" $cc, $dst",
3844 (BCC bibo, crrc:$cc, condbrtarget:$dst)>;
3845 def : InstAlias<"b"#name#pm#" $dst",
3846 (BCC bibo, CR0, condbrtarget:$dst)>;
3848 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst",
3849 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3850 def : InstAlias<"b"#name#"a"#pm#" $dst",
3851 (BCCA bibo, CR0, abscondbrtarget:$dst)>;
3853 def : InstAlias<"b"#name#"lr"#pm#" $cc",
3854 (BCCLR bibo, crrc:$cc)>;
3855 def : InstAlias<"b"#name#"lr"#pm,
3858 def : InstAlias<"b"#name#"ctr"#pm#" $cc",
3859 (BCCCTR bibo, crrc:$cc)>;
3860 def : InstAlias<"b"#name#"ctr"#pm,
3861 (BCCCTR bibo, CR0)>;
3863 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst",
3864 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>;
3865 def : InstAlias<"b"#name#"l"#pm#" $dst",
3866 (BCCL bibo, CR0, condbrtarget:$dst)>;
3868 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst",
3869 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>;
3870 def : InstAlias<"b"#name#"la"#pm#" $dst",
3871 (BCCLA bibo, CR0, abscondbrtarget:$dst)>;
3873 def : InstAlias<"b"#name#"lrl"#pm#" $cc",
3874 (BCCLRL bibo, crrc:$cc)>;
3875 def : InstAlias<"b"#name#"lrl"#pm,
3876 (BCCLRL bibo, CR0)>;
3878 def : InstAlias<"b"#name#"ctrl"#pm#" $cc",
3879 (BCCCTRL bibo, crrc:$cc)>;
3880 def : InstAlias<"b"#name#"ctrl"#pm,
3881 (BCCCTRL bibo, CR0)>;
3883 multiclass BranchExtendedMnemonic<string name, int bibo> {
3884 defm : BranchExtendedMnemonicPM<name, "", bibo>;
3885 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>;
3886 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>;
3888 defm : BranchExtendedMnemonic<"lt", 12>;
3889 defm : BranchExtendedMnemonic<"gt", 44>;
3890 defm : BranchExtendedMnemonic<"eq", 76>;
3891 defm : BranchExtendedMnemonic<"un", 108>;
3892 defm : BranchExtendedMnemonic<"so", 108>;
3893 defm : BranchExtendedMnemonic<"ge", 4>;
3894 defm : BranchExtendedMnemonic<"nl", 4>;
3895 defm : BranchExtendedMnemonic<"le", 36>;
3896 defm : BranchExtendedMnemonic<"ng", 36>;
3897 defm : BranchExtendedMnemonic<"ne", 68>;
3898 defm : BranchExtendedMnemonic<"nu", 100>;
3899 defm : BranchExtendedMnemonic<"ns", 100>;
3901 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
3902 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
3903 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
3904 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
3905 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>;
3906 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
3907 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>;
3908 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
3910 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>;
3911 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
3912 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
3913 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
3914 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
3915 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3916 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
3917 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
3919 multiclass TrapExtendedMnemonic<string name, int to> {
3920 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
3921 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
3922 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
3923 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
3925 defm : TrapExtendedMnemonic<"lt", 16>;
3926 defm : TrapExtendedMnemonic<"le", 20>;
3927 defm : TrapExtendedMnemonic<"eq", 4>;
3928 defm : TrapExtendedMnemonic<"ge", 12>;
3929 defm : TrapExtendedMnemonic<"gt", 8>;
3930 defm : TrapExtendedMnemonic<"nl", 12>;
3931 defm : TrapExtendedMnemonic<"ne", 24>;
3932 defm : TrapExtendedMnemonic<"ng", 20>;
3933 defm : TrapExtendedMnemonic<"llt", 2>;
3934 defm : TrapExtendedMnemonic<"lle", 6>;
3935 defm : TrapExtendedMnemonic<"lge", 5>;
3936 defm : TrapExtendedMnemonic<"lgt", 1>;
3937 defm : TrapExtendedMnemonic<"lnl", 5>;
3938 defm : TrapExtendedMnemonic<"lng", 6>;
3939 defm : TrapExtendedMnemonic<"u", 31>;
3942 def : Pat<(atomic_load_8 iaddr:$src), (LBZ memri:$src)>;
3943 def : Pat<(atomic_load_16 iaddr:$src), (LHZ memri:$src)>;
3944 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
3945 def : Pat<(atomic_load_8 xaddr:$src), (LBZX memrr:$src)>;
3946 def : Pat<(atomic_load_16 xaddr:$src), (LHZX memrr:$src)>;
3947 def : Pat<(atomic_load_32 xaddr:$src), (LWZX memrr:$src)>;
3950 def : Pat<(atomic_store_8 iaddr:$ptr, i32:$val), (STB gprc:$val, memri:$ptr)>;
3951 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH gprc:$val, memri:$ptr)>;
3952 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW gprc:$val, memri:$ptr)>;
3953 def : Pat<(atomic_store_8 xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
3954 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
3955 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;