1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
173 [SDNPHasChain, SDNPOptInGlue]>;
175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
176 [SDNPHasChain, SDNPMayLoad]>;
177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
178 [SDNPHasChain, SDNPMayStore]>;
180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
186 // Instructions to support atomic operations
187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
188 [SDNPHasChain, SDNPMayLoad]>;
189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
190 [SDNPHasChain, SDNPMayStore]>;
192 // Instructions to support medium and large code model
193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
198 // Instructions to support dynamic alloca.
199 def SDTDynOp : SDTypeProfile<1, 2, []>;
200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
202 //===----------------------------------------------------------------------===//
203 // PowerPC specific transformation functions and pattern fragments.
206 def SHL32 : SDNodeXForm<imm, [{
207 // Transformation function: 31 - imm
208 return getI32Imm(31 - N->getZExtValue());
211 def SRL32 : SDNodeXForm<imm, [{
212 // Transformation function: 32 - imm
213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
216 def LO16 : SDNodeXForm<imm, [{
217 // Transformation function: get the low 16 bits.
218 return getI32Imm((unsigned short)N->getZExtValue());
221 def HI16 : SDNodeXForm<imm, [{
222 // Transformation function: shift the immediate value down into the low bits.
223 return getI32Imm((unsigned)N->getZExtValue() >> 16);
226 def HA16 : SDNodeXForm<imm, [{
227 // Transformation function: shift the immediate value down into the low bits.
228 signed int Val = N->getZExtValue();
229 return getI32Imm((Val - (signed short)Val) >> 16);
231 def MB : SDNodeXForm<imm, [{
232 // Transformation function: get the start bit of a mask
234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
235 return getI32Imm(mb);
238 def ME : SDNodeXForm<imm, [{
239 // Transformation function: get the end bit of a mask
241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
242 return getI32Imm(me);
244 def maskimm32 : PatLeaf<(imm), [{
245 // maskImm predicate - True if immediate is a run of ones.
247 if (N->getValueType(0) == MVT::i32)
248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
253 def immSExt16 : PatLeaf<(imm), [{
254 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
255 // field. Used by instructions like 'addi'.
256 if (N->getValueType(0) == MVT::i32)
257 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
259 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
261 def immZExt16 : PatLeaf<(imm), [{
262 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
263 // field. Used by instructions like 'ori'.
264 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
267 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
268 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
269 // identical in 32-bit mode, but in 64-bit mode, they return true if the
270 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
272 def imm16ShiftedZExt : PatLeaf<(imm), [{
273 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
274 // immediate are set. Used by instructions like 'xoris'.
275 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
278 def imm16ShiftedSExt : PatLeaf<(imm), [{
279 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
280 // immediate are set. Used by instructions like 'addis'. Identical to
281 // imm16ShiftedZExt in 32-bit mode.
282 if (N->getZExtValue() & 0xFFFF) return false;
283 if (N->getValueType(0) == MVT::i32)
285 // For 64-bit, make sure it is sext right.
286 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
289 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
290 // restricted memrix (offset/4) constants are alignment sensitive. If these
291 // offsets are hidden behind TOC entries than the values of the lower-order
292 // bits cannot be checked directly. As a result, we need to also incorporate
293 // an alignment check into the relevant patterns.
295 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
296 return cast<LoadSDNode>(N)->getAlignment() >= 4;
298 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
299 (store node:$val, node:$ptr), [{
300 return cast<StoreSDNode>(N)->getAlignment() >= 4;
302 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
303 return cast<LoadSDNode>(N)->getAlignment() >= 4;
305 def aligned4pre_store : PatFrag<
306 (ops node:$val, node:$base, node:$offset),
307 (pre_store node:$val, node:$base, node:$offset), [{
308 return cast<StoreSDNode>(N)->getAlignment() >= 4;
311 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
312 return cast<LoadSDNode>(N)->getAlignment() < 4;
314 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
315 (store node:$val, node:$ptr), [{
316 return cast<StoreSDNode>(N)->getAlignment() < 4;
318 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
319 return cast<LoadSDNode>(N)->getAlignment() < 4;
322 //===----------------------------------------------------------------------===//
323 // PowerPC Flag Definitions.
325 class isPPC64 { bit PPC64 = 1; }
326 class isDOT { bit RC = 1; }
328 class RegConstraint<string C> {
329 string Constraints = C;
331 class NoEncode<string E> {
332 string DisableEncoding = E;
336 //===----------------------------------------------------------------------===//
337 // PowerPC Operand Definitions.
339 // In the default PowerPC assembler syntax, registers are specified simply
340 // by number, so they cannot be distinguished from immediate values (without
341 // looking at the opcode). This means that the default operand matching logic
342 // for the asm parser does not work, and we need to specify custom matchers.
343 // Since those can only be specified with RegisterOperand classes and not
344 // directly on the RegisterClass, all instructions patterns used by the asm
345 // parser need to use a RegisterOperand (instead of a RegisterClass) for
346 // all their register operands.
347 // For this purpose, we define one RegisterOperand for each RegisterClass,
348 // using the same name as the class, just in lower case.
350 def PPCRegGPRCAsmOperand : AsmOperandClass {
351 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber";
353 def gprc : RegisterOperand<GPRC> {
354 let ParserMatchClass = PPCRegGPRCAsmOperand;
356 def PPCRegG8RCAsmOperand : AsmOperandClass {
357 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber";
359 def g8rc : RegisterOperand<G8RC> {
360 let ParserMatchClass = PPCRegG8RCAsmOperand;
362 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass {
363 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber";
365 def gprc_nor0 : RegisterOperand<GPRC_NOR0> {
366 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand;
368 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass {
369 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber";
371 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> {
372 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand;
374 def PPCRegF8RCAsmOperand : AsmOperandClass {
375 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber";
377 def f8rc : RegisterOperand<F8RC> {
378 let ParserMatchClass = PPCRegF8RCAsmOperand;
380 def PPCRegF4RCAsmOperand : AsmOperandClass {
381 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
383 def f4rc : RegisterOperand<F4RC> {
384 let ParserMatchClass = PPCRegF4RCAsmOperand;
386 def PPCRegVRRCAsmOperand : AsmOperandClass {
387 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
389 def vrrc : RegisterOperand<VRRC> {
390 let ParserMatchClass = PPCRegVRRCAsmOperand;
392 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
393 let Name = "RegCRBITRC"; let PredicateMethod = "isRegNumber";
395 def crbitrc : RegisterOperand<CRBITRC> {
396 let ParserMatchClass = PPCRegCRBITRCAsmOperand;
398 def PPCRegCRRCAsmOperand : AsmOperandClass {
399 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber";
401 def crrc : RegisterOperand<CRRC> {
402 let ParserMatchClass = PPCRegCRRCAsmOperand;
405 def PPCS5ImmAsmOperand : AsmOperandClass {
406 let Name = "S5Imm"; let PredicateMethod = "isS5Imm";
407 let RenderMethod = "addImmOperands";
409 def s5imm : Operand<i32> {
410 let PrintMethod = "printS5ImmOperand";
411 let ParserMatchClass = PPCS5ImmAsmOperand;
413 def PPCU5ImmAsmOperand : AsmOperandClass {
414 let Name = "U5Imm"; let PredicateMethod = "isU5Imm";
415 let RenderMethod = "addImmOperands";
417 def u5imm : Operand<i32> {
418 let PrintMethod = "printU5ImmOperand";
419 let ParserMatchClass = PPCU5ImmAsmOperand;
421 def PPCU6ImmAsmOperand : AsmOperandClass {
422 let Name = "U6Imm"; let PredicateMethod = "isU6Imm";
423 let RenderMethod = "addImmOperands";
425 def u6imm : Operand<i32> {
426 let PrintMethod = "printU6ImmOperand";
427 let ParserMatchClass = PPCU6ImmAsmOperand;
429 def PPCS16ImmAsmOperand : AsmOperandClass {
430 let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
431 let RenderMethod = "addImmOperands";
433 def s16imm : Operand<i32> {
434 let PrintMethod = "printS16ImmOperand";
435 let ParserMatchClass = PPCS16ImmAsmOperand;
437 def PPCU16ImmAsmOperand : AsmOperandClass {
438 let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
439 let RenderMethod = "addImmOperands";
441 def u16imm : Operand<i32> {
442 let PrintMethod = "printU16ImmOperand";
443 let ParserMatchClass = PPCU16ImmAsmOperand;
445 def directbrtarget : Operand<OtherVT> {
446 let PrintMethod = "printBranchOperand";
447 let EncoderMethod = "getDirectBrEncoding";
449 def condbrtarget : Operand<OtherVT> {
450 let PrintMethod = "printBranchOperand";
451 let EncoderMethod = "getCondBrEncoding";
453 def calltarget : Operand<iPTR> {
454 let EncoderMethod = "getDirectBrEncoding";
456 def aaddr : Operand<iPTR> {
457 let PrintMethod = "printAbsAddrOperand";
459 def symbolHi: Operand<i32> {
460 let PrintMethod = "printSymbolHi";
461 let EncoderMethod = "getHA16Encoding";
462 let ParserMatchClass = PPCS16ImmAsmOperand;
464 def symbolLo: Operand<i32> {
465 let PrintMethod = "printSymbolLo";
466 let EncoderMethod = "getLO16Encoding";
467 let ParserMatchClass = PPCS16ImmAsmOperand;
469 def PPCCRBitMaskOperand : AsmOperandClass {
470 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
472 def crbitm: Operand<i8> {
473 let PrintMethod = "printcrbitm";
474 let EncoderMethod = "get_crbitm_encoding";
475 let ParserMatchClass = PPCCRBitMaskOperand;
478 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
479 def PPCRegGxRCNoR0Operand : AsmOperandClass {
480 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
482 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
483 let ParserMatchClass = PPCRegGxRCNoR0Operand;
485 // A version of ptr_rc usable with the asm parser.
486 def PPCRegGxRCOperand : AsmOperandClass {
487 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
489 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
490 let ParserMatchClass = PPCRegGxRCOperand;
493 def PPCDispRIOperand : AsmOperandClass {
494 let Name = "DispRI"; let PredicateMethod = "isS16Imm";
496 def dispRI : Operand<iPTR> {
497 let ParserMatchClass = PPCDispRIOperand;
499 def PPCDispRIXOperand : AsmOperandClass {
500 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4";
502 def dispRIX : Operand<iPTR> {
503 let ParserMatchClass = PPCDispRIXOperand;
506 def memri : Operand<iPTR> {
507 let PrintMethod = "printMemRegImm";
508 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
509 let EncoderMethod = "getMemRIEncoding";
511 def memrr : Operand<iPTR> {
512 let PrintMethod = "printMemRegReg";
513 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg);
515 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
516 let PrintMethod = "printMemRegImmShifted";
517 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
518 let EncoderMethod = "getMemRIXEncoding";
521 // A single-register address. This is used with the SjLj
522 // pseudo-instructions.
523 def memr : Operand<iPTR> {
524 let MIOperandInfo = (ops ptr_rc:$ptrreg);
527 // PowerPC Predicate operand.
528 def pred : Operand<OtherVT> {
529 let PrintMethod = "printPredicateOperand";
530 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg);
533 // Define PowerPC specific addressing mode.
534 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
535 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
536 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
537 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
539 // The address in a single register. This is used with the SjLj
540 // pseudo-instructions.
541 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
543 /// This is just the offset part of iaddr, used for preinc.
544 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
546 //===----------------------------------------------------------------------===//
547 // PowerPC Instruction Predicate Definitions.
548 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
549 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
550 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
552 //===----------------------------------------------------------------------===//
553 // PowerPC Multiclass Definitions.
555 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
556 string asmbase, string asmstr, InstrItinClass itin,
558 let BaseName = asmbase in {
559 def NAME : XForm_6<opcode, xo, OOL, IOL,
560 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
561 pattern>, RecFormRel;
563 def o : XForm_6<opcode, xo, OOL, IOL,
564 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
565 []>, isDOT, RecFormRel;
569 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
570 string asmbase, string asmstr, InstrItinClass itin,
572 let BaseName = asmbase in {
573 let Defs = [CARRY] in
574 def NAME : XForm_6<opcode, xo, OOL, IOL,
575 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
576 pattern>, RecFormRel;
577 let Defs = [CARRY, CR0] in
578 def o : XForm_6<opcode, xo, OOL, IOL,
579 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
580 []>, isDOT, RecFormRel;
584 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
585 string asmbase, string asmstr, InstrItinClass itin,
587 let BaseName = asmbase in {
588 def NAME : XForm_10<opcode, xo, OOL, IOL,
589 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
590 pattern>, RecFormRel;
592 def o : XForm_10<opcode, xo, OOL, IOL,
593 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
594 []>, isDOT, RecFormRel;
598 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
599 string asmbase, string asmstr, InstrItinClass itin,
601 let BaseName = asmbase in {
602 let Defs = [CARRY] in
603 def NAME : XForm_10<opcode, xo, OOL, IOL,
604 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
605 pattern>, RecFormRel;
606 let Defs = [CARRY, CR0] in
607 def o : XForm_10<opcode, xo, OOL, IOL,
608 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
609 []>, isDOT, RecFormRel;
613 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
614 string asmbase, string asmstr, InstrItinClass itin,
616 let BaseName = asmbase in {
617 def NAME : XForm_11<opcode, xo, OOL, IOL,
618 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
619 pattern>, RecFormRel;
621 def o : XForm_11<opcode, xo, OOL, IOL,
622 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
623 []>, isDOT, RecFormRel;
627 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
628 string asmbase, string asmstr, InstrItinClass itin,
630 let BaseName = asmbase in {
631 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
632 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
633 pattern>, RecFormRel;
635 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
636 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
637 []>, isDOT, RecFormRel;
641 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
642 string asmbase, string asmstr, InstrItinClass itin,
644 let BaseName = asmbase in {
645 let Defs = [CARRY] in
646 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
647 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
648 pattern>, RecFormRel;
649 let Defs = [CARRY, CR0] in
650 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
651 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
652 []>, isDOT, RecFormRel;
656 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
657 string asmbase, string asmstr, InstrItinClass itin,
659 let BaseName = asmbase in {
660 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
661 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
662 pattern>, RecFormRel;
664 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
665 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
666 []>, isDOT, RecFormRel;
670 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
671 string asmbase, string asmstr, InstrItinClass itin,
673 let BaseName = asmbase in {
674 let Defs = [CARRY] in
675 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
676 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
677 pattern>, RecFormRel;
678 let Defs = [CARRY, CR0] in
679 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
680 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
681 []>, isDOT, RecFormRel;
685 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
686 string asmbase, string asmstr, InstrItinClass itin,
688 let BaseName = asmbase in {
689 def NAME : MForm_2<opcode, OOL, IOL,
690 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
691 pattern>, RecFormRel;
693 def o : MForm_2<opcode, OOL, IOL,
694 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
695 []>, isDOT, RecFormRel;
699 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
700 string asmbase, string asmstr, InstrItinClass itin,
702 let BaseName = asmbase in {
703 def NAME : MDForm_1<opcode, xo, OOL, IOL,
704 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
705 pattern>, RecFormRel;
707 def o : MDForm_1<opcode, xo, OOL, IOL,
708 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
709 []>, isDOT, RecFormRel;
713 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
714 string asmbase, string asmstr, InstrItinClass itin,
716 let BaseName = asmbase in {
717 def NAME : MDSForm_1<opcode, xo, OOL, IOL,
718 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
719 pattern>, RecFormRel;
721 def o : MDSForm_1<opcode, xo, OOL, IOL,
722 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
723 []>, isDOT, RecFormRel;
727 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
728 string asmbase, string asmstr, InstrItinClass itin,
730 let BaseName = asmbase in {
731 let Defs = [CARRY] in
732 def NAME : XSForm_1<opcode, xo, OOL, IOL,
733 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
734 pattern>, RecFormRel;
735 let Defs = [CARRY, CR0] in
736 def o : XSForm_1<opcode, xo, OOL, IOL,
737 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
738 []>, isDOT, RecFormRel;
742 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
743 string asmbase, string asmstr, InstrItinClass itin,
745 let BaseName = asmbase in {
746 def NAME : XForm_26<opcode, xo, OOL, IOL,
747 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
748 pattern>, RecFormRel;
750 def o : XForm_26<opcode, xo, OOL, IOL,
751 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
752 []>, isDOT, RecFormRel;
756 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
757 string asmbase, string asmstr, InstrItinClass itin,
759 let BaseName = asmbase in {
760 def NAME : AForm_1<opcode, xo, OOL, IOL,
761 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
762 pattern>, RecFormRel;
764 def o : AForm_1<opcode, xo, OOL, IOL,
765 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
766 []>, isDOT, RecFormRel;
770 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
771 string asmbase, string asmstr, InstrItinClass itin,
773 let BaseName = asmbase in {
774 def NAME : AForm_2<opcode, xo, OOL, IOL,
775 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
776 pattern>, RecFormRel;
778 def o : AForm_2<opcode, xo, OOL, IOL,
779 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
780 []>, isDOT, RecFormRel;
784 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
785 string asmbase, string asmstr, InstrItinClass itin,
787 let BaseName = asmbase in {
788 def NAME : AForm_3<opcode, xo, OOL, IOL,
789 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
790 pattern>, RecFormRel;
792 def o : AForm_3<opcode, xo, OOL, IOL,
793 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
794 []>, isDOT, RecFormRel;
798 //===----------------------------------------------------------------------===//
799 // PowerPC Instruction Definitions.
801 // Pseudo-instructions:
803 let hasCtrlDep = 1 in {
804 let Defs = [R1], Uses = [R1] in {
805 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
806 [(callseq_start timm:$amt)]>;
807 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
808 [(callseq_end timm:$amt1, timm:$amt2)]>;
811 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
812 "UPDATE_VRSAVE $rD, $rS", []>;
815 let Defs = [R1], Uses = [R1] in
816 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
818 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
820 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
821 // instruction selection into a branch sequence.
822 let usesCustomInserter = 1, // Expanded after instruction selection.
823 PPC970_Single = 1 in {
824 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
825 // because either operand might become the first operand in an isel, and
826 // that operand cannot be r0.
827 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
828 gprc_nor0:$T, gprc_nor0:$F,
829 i32imm:$BROPC), "#SELECT_CC_I4",
831 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
832 g8rc_nox0:$T, g8rc_nox0:$F,
833 i32imm:$BROPC), "#SELECT_CC_I8",
835 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
836 i32imm:$BROPC), "#SELECT_CC_F4",
838 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
839 i32imm:$BROPC), "#SELECT_CC_F8",
841 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
842 i32imm:$BROPC), "#SELECT_CC_VRRC",
846 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
847 // scavenge a register for it.
849 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
852 // RESTORE_CR - Indicate that we're restoring the CR register (previously
853 // spilled), so we'll need to scavenge a register for it.
855 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
858 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
859 let isReturn = 1, Uses = [LR, RM] in
860 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
862 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
863 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
865 let isCodeGenOnly = 1 in
866 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
867 "b${cond:cc}ctr ${cond:reg}", BrB, []>;
872 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
875 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
876 let isBarrier = 1 in {
877 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
882 // BCC represents an arbitrary conditional branch on a predicate.
883 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
884 // a two-value operand where a dag node expects two operands. :(
885 let isCodeGenOnly = 1 in {
886 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
887 "b${cond:cc} ${cond:reg}, $dst"
888 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>;
889 let isReturn = 1, Uses = [LR, RM] in
890 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
891 "b${cond:cc}lr ${cond:reg}", BrB, []>;
893 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
894 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
896 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
901 let Defs = [CTR], Uses = [CTR] in {
902 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
904 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
909 // The unconditional BCL used by the SjLj setjmp code.
910 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
911 let Defs = [LR], Uses = [RM] in {
912 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
917 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
918 // Convenient aliases for call instructions
920 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
921 "bl $func", BrB, []>; // See Pat patterns below.
922 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
923 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
925 let Uses = [CTR, RM] in {
926 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
927 "bctrl", BrB, [(PPCbctrl)]>,
928 Requires<[In32BitMode]>;
930 let isCodeGenOnly = 1 in
931 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
932 "b${cond:cc}ctrl ${cond:reg}", BrB, []>;
936 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
937 def TCRETURNdi :Pseudo< (outs),
938 (ins calltarget:$dst, i32imm:$offset),
939 "#TC_RETURNd $dst $offset",
943 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
944 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
945 "#TC_RETURNa $func $offset",
946 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
948 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
949 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
950 "#TC_RETURNr $dst $offset",
954 let isCodeGenOnly = 1 in {
956 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
957 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
958 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
959 Requires<[In32BitMode]>;
963 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
964 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
965 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
971 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
972 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
973 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
977 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
978 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
980 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
981 Requires<[In32BitMode]>;
982 let isTerminator = 1 in
983 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
984 "#EH_SJLJ_LONGJMP32",
985 [(PPCeh_sjlj_longjmp addr:$buf)]>,
986 Requires<[In32BitMode]>;
989 let isBranch = 1, isTerminator = 1 in {
990 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
991 "#EH_SjLj_Setup\t$dst", []>;
995 let PPC970_Unit = 7 in {
996 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev),
997 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>;
1000 // DCB* instructions.
1001 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
1002 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
1003 PPC970_DGroup_Single;
1004 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
1005 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
1006 PPC970_DGroup_Single;
1007 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
1008 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
1009 PPC970_DGroup_Single;
1010 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
1011 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
1012 PPC970_DGroup_Single;
1013 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
1014 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
1015 PPC970_DGroup_Single;
1016 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
1017 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
1018 PPC970_DGroup_Single;
1019 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
1020 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
1021 PPC970_DGroup_Single;
1022 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
1023 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
1024 PPC970_DGroup_Single;
1026 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
1027 (DCBT xoaddr:$dst)>;
1029 // Atomic operations
1030 let usesCustomInserter = 1 in {
1031 let Defs = [CR0] in {
1032 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1033 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8",
1034 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
1035 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1036 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8",
1037 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
1038 def ATOMIC_LOAD_AND_I8 : Pseudo<
1039 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8",
1040 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
1041 def ATOMIC_LOAD_OR_I8 : Pseudo<
1042 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8",
1043 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
1044 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1045 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8",
1046 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
1047 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1048 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8",
1049 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
1050 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1051 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16",
1052 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
1053 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1054 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16",
1055 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
1056 def ATOMIC_LOAD_AND_I16 : Pseudo<
1057 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16",
1058 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
1059 def ATOMIC_LOAD_OR_I16 : Pseudo<
1060 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16",
1061 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
1062 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1063 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16",
1064 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
1065 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1066 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16",
1067 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
1068 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1069 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32",
1070 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
1071 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1072 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32",
1073 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
1074 def ATOMIC_LOAD_AND_I32 : Pseudo<
1075 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32",
1076 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
1077 def ATOMIC_LOAD_OR_I32 : Pseudo<
1078 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32",
1079 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
1080 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1081 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32",
1082 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
1083 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1084 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32",
1085 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
1087 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1088 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8",
1089 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
1090 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1091 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
1092 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
1093 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1094 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
1095 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
1097 def ATOMIC_SWAP_I8 : Pseudo<
1098 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8",
1099 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
1100 def ATOMIC_SWAP_I16 : Pseudo<
1101 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16",
1102 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
1103 def ATOMIC_SWAP_I32 : Pseudo<
1104 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32",
1105 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
1109 // Instructions to support atomic operations
1110 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src),
1111 "lwarx $rD, $src", LdStLWARX,
1112 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
1115 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
1116 "stwcx. $rS, $dst", LdStSTWCX,
1117 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
1120 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
1121 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
1123 //===----------------------------------------------------------------------===//
1124 // PPC32 Load Instructions.
1127 // Unindexed (r+i) Loads.
1128 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1129 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src),
1130 "lbz $rD, $src", LdStLoad,
1131 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
1132 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src),
1133 "lha $rD, $src", LdStLHA,
1134 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
1135 PPC970_DGroup_Cracked;
1136 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src),
1137 "lhz $rD, $src", LdStLoad,
1138 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
1139 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
1140 "lwz $rD, $src", LdStLoad,
1141 [(set i32:$rD, (load iaddr:$src))]>;
1143 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src),
1144 "lfs $rD, $src", LdStLFD,
1145 [(set f32:$rD, (load iaddr:$src))]>;
1146 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src),
1147 "lfd $rD, $src", LdStLFD,
1148 [(set f64:$rD, (load iaddr:$src))]>;
1151 // Unindexed (r+i) Loads with Update (preinc).
1152 let mayLoad = 1, neverHasSideEffects = 1 in {
1153 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1154 "lbzu $rD, $addr", LdStLoadUpd,
1155 []>, RegConstraint<"$addr.reg = $ea_result">,
1156 NoEncode<"$ea_result">;
1158 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1159 "lhau $rD, $addr", LdStLHAU,
1160 []>, RegConstraint<"$addr.reg = $ea_result">,
1161 NoEncode<"$ea_result">;
1163 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1164 "lhzu $rD, $addr", LdStLoadUpd,
1165 []>, RegConstraint<"$addr.reg = $ea_result">,
1166 NoEncode<"$ea_result">;
1168 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1169 "lwzu $rD, $addr", LdStLoadUpd,
1170 []>, RegConstraint<"$addr.reg = $ea_result">,
1171 NoEncode<"$ea_result">;
1173 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1174 "lfsu $rD, $addr", LdStLFDU,
1175 []>, RegConstraint<"$addr.reg = $ea_result">,
1176 NoEncode<"$ea_result">;
1178 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
1179 "lfdu $rD, $addr", LdStLFDU,
1180 []>, RegConstraint<"$addr.reg = $ea_result">,
1181 NoEncode<"$ea_result">;
1184 // Indexed (r+r) Loads with Update (preinc).
1185 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1187 "lbzux $rD, $addr", LdStLoadUpd,
1188 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1189 NoEncode<"$ea_result">;
1191 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1193 "lhaux $rD, $addr", LdStLHAU,
1194 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1195 NoEncode<"$ea_result">;
1197 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1199 "lhzux $rD, $addr", LdStLoadUpd,
1200 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1201 NoEncode<"$ea_result">;
1203 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result),
1205 "lwzux $rD, $addr", LdStLoadUpd,
1206 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1207 NoEncode<"$ea_result">;
1209 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result),
1211 "lfsux $rD, $addr", LdStLFDU,
1212 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1213 NoEncode<"$ea_result">;
1215 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result),
1217 "lfdux $rD, $addr", LdStLFDU,
1218 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1219 NoEncode<"$ea_result">;
1223 // Indexed (r+r) Loads.
1225 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1226 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src),
1227 "lbzx $rD, $src", LdStLoad,
1228 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1229 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src),
1230 "lhax $rD, $src", LdStLHA,
1231 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1232 PPC970_DGroup_Cracked;
1233 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src),
1234 "lhzx $rD, $src", LdStLoad,
1235 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1236 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src),
1237 "lwzx $rD, $src", LdStLoad,
1238 [(set i32:$rD, (load xaddr:$src))]>;
1241 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src),
1242 "lhbrx $rD, $src", LdStLoad,
1243 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1244 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src),
1245 "lwbrx $rD, $src", LdStLoad,
1246 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1248 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src),
1249 "lfsx $frD, $src", LdStLFD,
1250 [(set f32:$frD, (load xaddr:$src))]>;
1251 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src),
1252 "lfdx $frD, $src", LdStLFD,
1253 [(set f64:$frD, (load xaddr:$src))]>;
1255 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src),
1256 "lfiwax $frD, $src", LdStLFD,
1257 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1258 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src),
1259 "lfiwzx $frD, $src", LdStLFD,
1260 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1263 //===----------------------------------------------------------------------===//
1264 // PPC32 Store Instructions.
1267 // Unindexed (r+i) Stores.
1268 let PPC970_Unit = 2 in {
1269 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src),
1270 "stb $rS, $src", LdStStore,
1271 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1272 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src),
1273 "sth $rS, $src", LdStStore,
1274 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1275 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src),
1276 "stw $rS, $src", LdStStore,
1277 [(store i32:$rS, iaddr:$src)]>;
1278 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst),
1279 "stfs $rS, $dst", LdStSTFD,
1280 [(store f32:$rS, iaddr:$dst)]>;
1281 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst),
1282 "stfd $rS, $dst", LdStSTFD,
1283 [(store f64:$rS, iaddr:$dst)]>;
1286 // Unindexed (r+i) Stores with Update (preinc).
1287 let PPC970_Unit = 2, mayStore = 1 in {
1288 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1289 "stbu $rS, $dst", LdStStoreUpd, []>,
1290 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1291 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1292 "sthu $rS, $dst", LdStStoreUpd, []>,
1293 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1294 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst),
1295 "stwu $rS, $dst", LdStStoreUpd, []>,
1296 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1297 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst),
1298 "stfsu $rS, $dst", LdStSTFDU, []>,
1299 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1300 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst),
1301 "stfdu $rS, $dst", LdStSTFDU, []>,
1302 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1305 // Patterns to match the pre-inc stores. We can't put the patterns on
1306 // the instruction definitions directly as ISel wants the address base
1307 // and offset to be separate operands, not a single complex operand.
1308 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1309 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1310 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1311 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1312 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1313 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1314 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1315 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1316 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1317 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1319 // Indexed (r+r) Stores.
1320 let PPC970_Unit = 2 in {
1321 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst),
1322 "stbx $rS, $dst", LdStStore,
1323 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1324 PPC970_DGroup_Cracked;
1325 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst),
1326 "sthx $rS, $dst", LdStStore,
1327 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1328 PPC970_DGroup_Cracked;
1329 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst),
1330 "stwx $rS, $dst", LdStStore,
1331 [(store i32:$rS, xaddr:$dst)]>,
1332 PPC970_DGroup_Cracked;
1334 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst),
1335 "sthbrx $rS, $dst", LdStStore,
1336 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1337 PPC970_DGroup_Cracked;
1338 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst),
1339 "stwbrx $rS, $dst", LdStStore,
1340 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1341 PPC970_DGroup_Cracked;
1343 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst),
1344 "stfiwx $frS, $dst", LdStSTFD,
1345 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1347 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst),
1348 "stfsx $frS, $dst", LdStSTFD,
1349 [(store f32:$frS, xaddr:$dst)]>;
1350 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst),
1351 "stfdx $frS, $dst", LdStSTFD,
1352 [(store f64:$frS, xaddr:$dst)]>;
1355 // Indexed (r+r) Stores with Update (preinc).
1356 let PPC970_Unit = 2, mayStore = 1 in {
1357 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1358 "stbux $rS, $dst", LdStStoreUpd, []>,
1359 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1360 PPC970_DGroup_Cracked;
1361 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1362 "sthux $rS, $dst", LdStStoreUpd, []>,
1363 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1364 PPC970_DGroup_Cracked;
1365 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst),
1366 "stwux $rS, $dst", LdStStoreUpd, []>,
1367 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1368 PPC970_DGroup_Cracked;
1369 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst),
1370 "stfsux $rS, $dst", LdStSTFDU, []>,
1371 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1372 PPC970_DGroup_Cracked;
1373 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst),
1374 "stfdux $rS, $dst", LdStSTFDU, []>,
1375 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1376 PPC970_DGroup_Cracked;
1379 // Patterns to match the pre-inc stores. We can't put the patterns on
1380 // the instruction definitions directly as ISel wants the address base
1381 // and offset to be separate operands, not a single complex operand.
1382 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1383 (STBUX $rS, $ptrreg, $ptroff)>;
1384 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1385 (STHUX $rS, $ptrreg, $ptroff)>;
1386 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1387 (STWUX $rS, $ptrreg, $ptroff)>;
1388 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1389 (STFSUX $rS, $ptrreg, $ptroff)>;
1390 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1391 (STFDUX $rS, $ptrreg, $ptroff)>;
1393 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1397 //===----------------------------------------------------------------------===//
1398 // PPC32 Arithmetic Instructions.
1401 let PPC970_Unit = 1 in { // FXU Operations.
1402 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$imm),
1403 "addi $rD, $rA, $imm", IntSimple,
1404 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
1405 let BaseName = "addic" in {
1406 let Defs = [CARRY] in
1407 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1408 "addic $rD, $rA, $imm", IntGeneral,
1409 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
1410 RecFormRel, PPC970_DGroup_Cracked;
1411 let Defs = [CARRY, CR0] in
1412 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1413 "addic. $rD, $rA, $imm", IntGeneral,
1414 []>, isDOT, RecFormRel;
1416 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolHi:$imm),
1417 "addis $rD, $rA, $imm", IntSimple,
1418 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1419 let isCodeGenOnly = 1 in
1420 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$sym),
1421 "la $rD, $sym($rA)", IntGeneral,
1422 [(set i32:$rD, (add i32:$rA,
1423 (PPClo tglobaladdr:$sym, 0)))]>;
1424 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1425 "mulli $rD, $rA, $imm", IntMulLI,
1426 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1427 let Defs = [CARRY] in
1428 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
1429 "subfic $rD, $rA, $imm", IntGeneral,
1430 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1432 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1433 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins symbolLo:$imm),
1434 "li $rD, $imm", IntSimple,
1435 [(set i32:$rD, immSExt16:$imm)]>;
1436 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins symbolHi:$imm),
1437 "lis $rD, $imm", IntSimple,
1438 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1442 let PPC970_Unit = 1 in { // FXU Operations.
1443 let Defs = [CR0] in {
1444 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1445 "andi. $dst, $src1, $src2", IntGeneral,
1446 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1448 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1449 "andis. $dst, $src1, $src2", IntGeneral,
1450 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1453 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1454 "ori $dst, $src1, $src2", IntSimple,
1455 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1456 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1457 "oris $dst, $src1, $src2", IntSimple,
1458 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1459 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1460 "xori $dst, $src1, $src2", IntSimple,
1461 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1462 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
1463 "xoris $dst, $src1, $src2", IntSimple,
1464 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1465 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1467 let isCompare = 1, neverHasSideEffects = 1 in {
1468 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm),
1469 "cmpwi $crD, $rA, $imm", IntCompare>;
1470 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2),
1471 "cmplwi $dst, $src1, $src2", IntCompare>;
1475 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1476 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1477 "nand", "$rA, $rS, $rB", IntSimple,
1478 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1479 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1480 "and", "$rA, $rS, $rB", IntSimple,
1481 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1482 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1483 "andc", "$rA, $rS, $rB", IntSimple,
1484 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1485 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1486 "or", "$rA, $rS, $rB", IntSimple,
1487 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1488 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1489 "nor", "$rA, $rS, $rB", IntSimple,
1490 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1491 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1492 "orc", "$rA, $rS, $rB", IntSimple,
1493 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1494 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1495 "eqv", "$rA, $rS, $rB", IntSimple,
1496 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1497 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1498 "xor", "$rA, $rS, $rB", IntSimple,
1499 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1500 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1501 "slw", "$rA, $rS, $rB", IntGeneral,
1502 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1503 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1504 "srw", "$rA, $rS, $rB", IntGeneral,
1505 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1506 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
1507 "sraw", "$rA, $rS, $rB", IntShift,
1508 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1511 let PPC970_Unit = 1 in { // FXU Operations.
1512 let neverHasSideEffects = 1 in {
1513 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
1514 "srawi", "$rA, $rS, $SH", IntShift,
1515 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1516 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS),
1517 "cntlzw", "$rA, $rS", IntGeneral,
1518 [(set i32:$rA, (ctlz i32:$rS))]>;
1519 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS),
1520 "extsb", "$rA, $rS", IntSimple,
1521 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1522 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS),
1523 "extsh", "$rA, $rS", IntSimple,
1524 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1526 let isCompare = 1, neverHasSideEffects = 1 in {
1527 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1528 "cmpw $crD, $rA, $rB", IntCompare>;
1529 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB),
1530 "cmplw $crD, $rA, $rB", IntCompare>;
1533 let PPC970_Unit = 3 in { // FPU Operations.
1534 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1535 // "fcmpo $crD, $fA, $fB", FPCompare>;
1536 let isCompare = 1, neverHasSideEffects = 1 in {
1537 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
1538 "fcmpu $crD, $fA, $fB", FPCompare>;
1539 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
1540 "fcmpu $crD, $fA, $fB", FPCompare>;
1543 let Uses = [RM] in {
1544 let neverHasSideEffects = 1 in {
1545 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
1546 "fctiwz", "$frD, $frB", FPGeneral,
1547 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1549 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
1550 "frsp", "$frD, $frB", FPGeneral,
1551 [(set f32:$frD, (fround f64:$frB))]>;
1553 // The frin -> nearbyint mapping is valid only in fast-math mode.
1554 let Interpretation64Bit = 1 in
1555 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB),
1556 "frin", "$frD, $frB", FPGeneral,
1557 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1558 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB),
1559 "frin", "$frD, $frB", FPGeneral,
1560 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1563 // These pseudos expand to rint but also set FE_INEXACT when the result does
1564 // not equal the argument.
1565 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1566 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB),
1567 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1568 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB),
1569 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1572 let neverHasSideEffects = 1 in {
1573 let Interpretation64Bit = 1 in
1574 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB),
1575 "frip", "$frD, $frB", FPGeneral,
1576 [(set f64:$frD, (fceil f64:$frB))]>;
1577 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB),
1578 "frip", "$frD, $frB", FPGeneral,
1579 [(set f32:$frD, (fceil f32:$frB))]>;
1580 let Interpretation64Bit = 1 in
1581 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB),
1582 "friz", "$frD, $frB", FPGeneral,
1583 [(set f64:$frD, (ftrunc f64:$frB))]>;
1584 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB),
1585 "friz", "$frD, $frB", FPGeneral,
1586 [(set f32:$frD, (ftrunc f32:$frB))]>;
1587 let Interpretation64Bit = 1 in
1588 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
1589 "frim", "$frD, $frB", FPGeneral,
1590 [(set f64:$frD, (ffloor f64:$frB))]>;
1591 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
1592 "frim", "$frD, $frB", FPGeneral,
1593 [(set f32:$frD, (ffloor f32:$frB))]>;
1595 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
1596 "fsqrt", "$frD, $frB", FPSqrt,
1597 [(set f64:$frD, (fsqrt f64:$frB))]>;
1598 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
1599 "fsqrts", "$frD, $frB", FPSqrt,
1600 [(set f32:$frD, (fsqrt f32:$frB))]>;
1605 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1606 /// often coalesced away and we don't want the dispatch group builder to think
1607 /// that they will fill slots (which could cause the load of a LSU reject to
1608 /// sneak into a d-group with a store).
1609 let neverHasSideEffects = 1 in
1610 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB),
1611 "fmr", "$frD, $frB", FPGeneral,
1612 []>, // (set f32:$frD, f32:$frB)
1615 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1616 // These are artificially split into two different forms, for 4/8 byte FP.
1617 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB),
1618 "fabs", "$frD, $frB", FPGeneral,
1619 [(set f32:$frD, (fabs f32:$frB))]>;
1620 let Interpretation64Bit = 1 in
1621 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB),
1622 "fabs", "$frD, $frB", FPGeneral,
1623 [(set f64:$frD, (fabs f64:$frB))]>;
1624 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB),
1625 "fnabs", "$frD, $frB", FPGeneral,
1626 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1627 let Interpretation64Bit = 1 in
1628 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB),
1629 "fnabs", "$frD, $frB", FPGeneral,
1630 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1631 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB),
1632 "fneg", "$frD, $frB", FPGeneral,
1633 [(set f32:$frD, (fneg f32:$frB))]>;
1634 let Interpretation64Bit = 1 in
1635 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB),
1636 "fneg", "$frD, $frB", FPGeneral,
1637 [(set f64:$frD, (fneg f64:$frB))]>;
1639 // Reciprocal estimates.
1640 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB),
1641 "fre", "$frD, $frB", FPGeneral,
1642 [(set f64:$frD, (PPCfre f64:$frB))]>;
1643 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB),
1644 "fres", "$frD, $frB", FPGeneral,
1645 [(set f32:$frD, (PPCfre f32:$frB))]>;
1646 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB),
1647 "frsqrte", "$frD, $frB", FPGeneral,
1648 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1649 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB),
1650 "frsqrtes", "$frD, $frB", FPGeneral,
1651 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1654 // XL-Form instructions. condition register logical ops.
1656 let neverHasSideEffects = 1 in
1657 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA),
1658 "mcrf $BF, $BFA", BrMCR>,
1659 PPC970_DGroup_First, PPC970_Unit_CRU;
1661 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD),
1662 (ins crbitrc:$CRA, crbitrc:$CRB),
1663 "creqv $CRD, $CRA, $CRB", BrCR,
1666 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD),
1667 (ins crbitrc:$CRA, crbitrc:$CRB),
1668 "cror $CRD, $CRA, $CRB", BrCR,
1671 let isCodeGenOnly = 1 in {
1672 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins),
1673 "creqv $dst, $dst, $dst", BrCR,
1676 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins),
1677 "crxor $dst, $dst, $dst", BrCR,
1680 let Defs = [CR1EQ], CRD = 6 in {
1681 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1682 "creqv 6, 6, 6", BrCR,
1685 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1686 "crxor 6, 6, 6", BrCR,
1691 // XFX-Form instructions. Instructions that deal with SPRs.
1693 let Uses = [CTR] in {
1694 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins),
1695 "mfctr $rT", SprMFSPR>,
1696 PPC970_DGroup_First, PPC970_Unit_FXU;
1698 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1699 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1700 "mtctr $rS", SprMTSPR>,
1701 PPC970_DGroup_First, PPC970_Unit_FXU;
1703 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
1704 let Pattern = [(int_ppc_mtctr i32:$rS)] in
1705 def MTCTRse : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
1706 "mtctr $rS", SprMTSPR>,
1707 PPC970_DGroup_First, PPC970_Unit_FXU;
1710 let Defs = [LR] in {
1711 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
1712 "mtlr $rS", SprMTSPR>,
1713 PPC970_DGroup_First, PPC970_Unit_FXU;
1715 let Uses = [LR] in {
1716 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
1717 "mflr $rT", SprMFSPR>,
1718 PPC970_DGroup_First, PPC970_Unit_FXU;
1721 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1722 // a GPR on the PPC970. As such, copies in and out have the same performance
1723 // characteristics as an OR instruction.
1724 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
1725 "mtspr 256, $rS", IntGeneral>,
1726 PPC970_DGroup_Single, PPC970_Unit_FXU;
1727 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins),
1728 "mfspr $rT, 256", IntGeneral>,
1729 PPC970_DGroup_First, PPC970_Unit_FXU;
1731 let isCodeGenOnly = 1 in {
1732 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1733 (outs VRSAVERC:$reg), (ins gprc:$rS),
1734 "mtspr 256, $rS", IntGeneral>,
1735 PPC970_DGroup_Single, PPC970_Unit_FXU;
1736 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT),
1737 (ins VRSAVERC:$reg),
1738 "mfspr $rT, 256", IntGeneral>,
1739 PPC970_DGroup_First, PPC970_Unit_FXU;
1742 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1743 // so we'll need to scavenge a register for it.
1745 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1746 "#SPILL_VRSAVE", []>;
1748 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1749 // spilled), so we'll need to scavenge a register for it.
1751 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1752 "#RESTORE_VRSAVE", []>;
1754 let neverHasSideEffects = 1 in {
1755 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins gprc:$rS),
1756 "mtcrf $FXM, $rS", BrMCRX>,
1757 PPC970_MicroCode, PPC970_Unit_CRU;
1759 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1760 // declaring that here gives the local register allocator problems with this:
1762 // MFCR <kill of whatever preg got assigned to vreg>
1763 // while not declaring it breaks DeadMachineInstructionElimination.
1764 // As it turns out, in all cases where we currently use this,
1765 // we're only interested in one subregister of it. Represent this in the
1766 // instruction to keep the register allocator from becoming confused.
1768 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1769 let isCodeGenOnly = 1 in
1770 def MFCRpseud: XFXForm_3<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1771 "#MFCRpseud", SprMFCR>,
1772 PPC970_MicroCode, PPC970_Unit_CRU;
1774 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
1775 "mfocrf $rT, $FXM", SprMFCR>,
1776 PPC970_DGroup_First, PPC970_Unit_CRU;
1777 } // neverHasSideEffects = 1
1779 let neverHasSideEffects = 1 in
1780 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
1781 "mfcr $rT", SprMFCR>,
1782 PPC970_MicroCode, PPC970_Unit_CRU;
1784 // Pseudo instruction to perform FADD in round-to-zero mode.
1785 let usesCustomInserter = 1, Uses = [RM] in {
1786 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1787 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1790 // The above pseudo gets expanded to make use of the following instructions
1791 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1792 let Uses = [RM], Defs = [RM] in {
1793 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1794 "mtfsb0 $FM", IntMTFSB0, []>,
1795 PPC970_DGroup_Single, PPC970_Unit_FPU;
1796 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1797 "mtfsb1 $FM", IntMTFSB0, []>,
1798 PPC970_DGroup_Single, PPC970_Unit_FPU;
1799 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
1800 "mtfsf $FM, $rT", IntMTFSB0, []>,
1801 PPC970_DGroup_Single, PPC970_Unit_FPU;
1803 let Uses = [RM] in {
1804 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins),
1805 "mffs $rT", IntMFFS,
1806 [(set f64:$rT, (PPCmffs))]>,
1807 PPC970_DGroup_Single, PPC970_Unit_FPU;
1811 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1812 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1814 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1815 "add", "$rT, $rA, $rB", IntSimple,
1816 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1817 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1818 "addc", "$rT, $rA, $rB", IntGeneral,
1819 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1820 PPC970_DGroup_Cracked;
1821 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1822 "divw", "$rT, $rA, $rB", IntDivW,
1823 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1824 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1825 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1826 "divwu", "$rT, $rA, $rB", IntDivW,
1827 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1828 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1829 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1830 "mulhw", "$rT, $rA, $rB", IntMulHW,
1831 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1832 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1833 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1834 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1835 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1836 "mullw", "$rT, $rA, $rB", IntMulHW,
1837 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1838 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1839 "subf", "$rT, $rA, $rB", IntGeneral,
1840 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1841 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1842 "subfc", "$rT, $rA, $rB", IntGeneral,
1843 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1844 PPC970_DGroup_Cracked;
1845 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA),
1846 "neg", "$rT, $rA", IntSimple,
1847 [(set i32:$rT, (ineg i32:$rA))]>;
1848 let Uses = [CARRY] in {
1849 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1850 "adde", "$rT, $rA, $rB", IntGeneral,
1851 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1852 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA),
1853 "addme", "$rT, $rA", IntGeneral,
1854 [(set i32:$rT, (adde i32:$rA, -1))]>;
1855 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA),
1856 "addze", "$rT, $rA", IntGeneral,
1857 [(set i32:$rT, (adde i32:$rA, 0))]>;
1858 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
1859 "subfe", "$rT, $rA, $rB", IntGeneral,
1860 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1861 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
1862 "subfme", "$rT, $rA", IntGeneral,
1863 [(set i32:$rT, (sube -1, i32:$rA))]>;
1864 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
1865 "subfze", "$rT, $rA", IntGeneral,
1866 [(set i32:$rT, (sube 0, i32:$rA))]>;
1870 // A-Form instructions. Most of the instructions executed in the FPU are of
1873 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1874 let Uses = [RM] in {
1875 defm FMADD : AForm_1r<63, 29,
1876 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1877 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1878 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1879 defm FMADDS : AForm_1r<59, 29,
1880 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1881 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1882 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1883 defm FMSUB : AForm_1r<63, 28,
1884 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1885 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1887 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1888 defm FMSUBS : AForm_1r<59, 28,
1889 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1890 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1892 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1893 defm FNMADD : AForm_1r<63, 31,
1894 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1895 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1897 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1898 defm FNMADDS : AForm_1r<59, 31,
1899 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1900 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1902 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1903 defm FNMSUB : AForm_1r<63, 30,
1904 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1905 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1906 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1907 (fneg f64:$FRB))))]>;
1908 defm FNMSUBS : AForm_1r<59, 30,
1909 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1910 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1911 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1912 (fneg f32:$FRB))))]>;
1914 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1915 // having 4 of these, force the comparison to always be an 8-byte double (code
1916 // should use an FMRSD if the input comparison value really wants to be a float)
1917 // and 4/8 byte forms for the result and operand type..
1918 let Interpretation64Bit = 1 in
1919 defm FSELD : AForm_1r<63, 23,
1920 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
1921 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1922 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1923 defm FSELS : AForm_1r<63, 23,
1924 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB),
1925 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1926 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1927 let Uses = [RM] in {
1928 defm FADD : AForm_2r<63, 21,
1929 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1930 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
1931 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1932 defm FADDS : AForm_2r<59, 21,
1933 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1934 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
1935 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1936 defm FDIV : AForm_2r<63, 18,
1937 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1938 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
1939 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1940 defm FDIVS : AForm_2r<59, 18,
1941 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1942 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
1943 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1944 defm FMUL : AForm_3r<63, 25,
1945 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
1946 "fmul", "$FRT, $FRA, $FRC", FPFused,
1947 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1948 defm FMULS : AForm_3r<59, 25,
1949 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
1950 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
1951 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1952 defm FSUB : AForm_2r<63, 20,
1953 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
1954 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
1955 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1956 defm FSUBS : AForm_2r<59, 20,
1957 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB),
1958 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
1959 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1963 let neverHasSideEffects = 1 in {
1964 let PPC970_Unit = 1 in { // FXU Operations.
1966 def ISEL : AForm_4<31, 15,
1967 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond),
1968 "isel $rT, $rA, $rB, $cond", IntGeneral,
1972 let PPC970_Unit = 1 in { // FXU Operations.
1973 // M-Form instructions. rotate and mask instructions.
1975 let isCommutable = 1 in {
1976 // RLWIMI can be commuted if the rotate amount is zero.
1977 defm RLWIMI : MForm_2r<20, (outs gprc:$rA),
1978 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB,
1979 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
1980 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1983 let BaseName = "rlwinm" in {
1984 def RLWINM : MForm_2<21,
1985 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1986 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1989 def RLWINMo : MForm_2<21,
1990 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1991 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1992 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
1994 defm RLWNM : MForm_2r<23, (outs gprc:$rA),
1995 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME),
1996 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
1999 } // neverHasSideEffects = 1
2001 //===----------------------------------------------------------------------===//
2002 // PowerPC Instruction Patterns
2005 // Arbitrary immediate support. Implement in terms of LIS/ORI.
2006 def : Pat<(i32 imm:$imm),
2007 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
2009 // Implement the 'not' operation with the NOR instruction.
2010 def NOT : Pat<(not i32:$in),
2013 // ADD an arbitrary immediate.
2014 def : Pat<(add i32:$in, imm:$imm),
2015 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
2016 // OR an arbitrary immediate.
2017 def : Pat<(or i32:$in, imm:$imm),
2018 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2019 // XOR an arbitrary immediate.
2020 def : Pat<(xor i32:$in, imm:$imm),
2021 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
2023 def : Pat<(sub immSExt16:$imm, i32:$in),
2024 (SUBFIC $in, imm:$imm)>;
2027 def : Pat<(shl i32:$in, (i32 imm:$imm)),
2028 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
2029 def : Pat<(srl i32:$in, (i32 imm:$imm)),
2030 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
2033 def : Pat<(rotl i32:$in, i32:$sh),
2034 (RLWNM $in, $sh, 0, 31)>;
2035 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
2036 (RLWINM $in, imm:$imm, 0, 31)>;
2039 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
2040 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
2043 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
2044 (BL tglobaladdr:$dst)>;
2045 def : Pat<(PPCcall (i32 texternalsym:$dst)),
2046 (BL texternalsym:$dst)>;
2049 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
2050 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
2052 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
2053 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
2055 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
2056 (TCRETURNri CTRRC:$dst, imm:$imm)>;
2060 // Hi and Lo for Darwin Global Addresses.
2061 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
2062 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
2063 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
2064 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
2065 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
2066 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
2067 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
2068 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
2069 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
2070 (ADDIS $in, tglobaltlsaddr:$g)>;
2071 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
2072 (ADDI $in, tglobaltlsaddr:$g)>;
2073 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
2074 (ADDIS $in, tglobaladdr:$g)>;
2075 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
2076 (ADDIS $in, tconstpool:$g)>;
2077 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
2078 (ADDIS $in, tjumptable:$g)>;
2079 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
2080 (ADDIS $in, tblockaddress:$g)>;
2082 // Standard shifts. These are represented separately from the real shifts above
2083 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
2085 def : Pat<(sra i32:$rS, i32:$rB),
2087 def : Pat<(srl i32:$rS, i32:$rB),
2089 def : Pat<(shl i32:$rS, i32:$rB),
2092 def : Pat<(zextloadi1 iaddr:$src),
2094 def : Pat<(zextloadi1 xaddr:$src),
2096 def : Pat<(extloadi1 iaddr:$src),
2098 def : Pat<(extloadi1 xaddr:$src),
2100 def : Pat<(extloadi8 iaddr:$src),
2102 def : Pat<(extloadi8 xaddr:$src),
2104 def : Pat<(extloadi16 iaddr:$src),
2106 def : Pat<(extloadi16 xaddr:$src),
2108 def : Pat<(f64 (extloadf32 iaddr:$src)),
2109 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
2110 def : Pat<(f64 (extloadf32 xaddr:$src)),
2111 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
2113 def : Pat<(f64 (fextend f32:$src)),
2114 (COPY_TO_REGCLASS $src, F8RC)>;
2116 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
2118 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
2119 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
2120 (FNMSUB $A, $C, $B)>;
2121 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
2122 (FNMSUB $A, $C, $B)>;
2123 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
2124 (FNMSUBS $A, $C, $B)>;
2125 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
2126 (FNMSUBS $A, $C, $B)>;
2128 include "PPCInstrAltivec.td"
2129 include "PPCInstr64Bit.td"
2132 //===----------------------------------------------------------------------===//
2133 // PowerPC Instructions used for assembler/disassembler only
2136 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
2137 "isync", SprISYNC, []>;
2139 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
2140 "icbi $src", LdStICBI, []>;
2142 //===----------------------------------------------------------------------===//
2143 // PowerPC Assembler Instruction Aliases
2146 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
2147 // These are aliases that require C++ handling to convert to the target
2148 // instruction, while InstAliases can be handled directly by tblgen.
2149 class PPCAsmPseudo<string asm, dag iops>
2151 let Namespace = "PPC";
2152 bit PPC64 = 0; // Default value, override with isPPC64
2154 let OutOperandList = (outs);
2155 let InOperandList = iops;
2157 let AsmString = asm;
2158 let isAsmParserOnly = 1;
2162 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
2164 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
2165 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2166 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
2167 (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
2168 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
2169 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2170 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
2171 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
2173 def : InstAlias<"blt $cc, $dst", (BCC 12, crrc:$cc, condbrtarget:$dst)>;
2174 def : InstAlias<"bgt $cc, $dst", (BCC 44, crrc:$cc, condbrtarget:$dst)>;
2175 def : InstAlias<"beq $cc, $dst", (BCC 76, crrc:$cc, condbrtarget:$dst)>;
2176 def : InstAlias<"bun $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
2177 def : InstAlias<"bso $cc, $dst", (BCC 108, crrc:$cc, condbrtarget:$dst)>;
2178 def : InstAlias<"bge $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
2179 def : InstAlias<"bnl $cc, $dst", (BCC 4, crrc:$cc, condbrtarget:$dst)>;
2180 def : InstAlias<"ble $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
2181 def : InstAlias<"bng $cc, $dst", (BCC 36, crrc:$cc, condbrtarget:$dst)>;
2182 def : InstAlias<"bne $cc, $dst", (BCC 68, crrc:$cc, condbrtarget:$dst)>;
2183 def : InstAlias<"bnu $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
2184 def : InstAlias<"bns $cc, $dst", (BCC 100, crrc:$cc, condbrtarget:$dst)>;
2186 def : InstAlias<"bltlr $cc", (BCLR 12, crrc:$cc)>;
2187 def : InstAlias<"bgtlr $cc", (BCLR 44, crrc:$cc)>;
2188 def : InstAlias<"beqlr $cc", (BCLR 76, crrc:$cc)>;
2189 def : InstAlias<"bunlr $cc", (BCLR 108, crrc:$cc)>;
2190 def : InstAlias<"bsolr $cc", (BCLR 108, crrc:$cc)>;
2191 def : InstAlias<"bgelr $cc", (BCLR 4, crrc:$cc)>;
2192 def : InstAlias<"bnllr $cc", (BCLR 4, crrc:$cc)>;
2193 def : InstAlias<"blelr $cc", (BCLR 36, crrc:$cc)>;
2194 def : InstAlias<"bnglr $cc", (BCLR 36, crrc:$cc)>;
2195 def : InstAlias<"bnelr $cc", (BCLR 68, crrc:$cc)>;
2196 def : InstAlias<"bnulr $cc", (BCLR 100, crrc:$cc)>;
2197 def : InstAlias<"bnslr $cc", (BCLR 100, crrc:$cc)>;
2199 def : InstAlias<"bltctr $cc", (BCCTR 12, crrc:$cc)>;
2200 def : InstAlias<"bgtctr $cc", (BCCTR 44, crrc:$cc)>;
2201 def : InstAlias<"beqctr $cc", (BCCTR 76, crrc:$cc)>;
2202 def : InstAlias<"bunctr $cc", (BCCTR 108, crrc:$cc)>;
2203 def : InstAlias<"bsoctr $cc", (BCCTR 108, crrc:$cc)>;
2204 def : InstAlias<"bgectr $cc", (BCCTR 4, crrc:$cc)>;
2205 def : InstAlias<"bnlctr $cc", (BCCTR 4, crrc:$cc)>;
2206 def : InstAlias<"blectr $cc", (BCCTR 36, crrc:$cc)>;
2207 def : InstAlias<"bngctr $cc", (BCCTR 36, crrc:$cc)>;
2208 def : InstAlias<"bnectr $cc", (BCCTR 68, crrc:$cc)>;
2209 def : InstAlias<"bnuctr $cc", (BCCTR 100, crrc:$cc)>;
2210 def : InstAlias<"bnsctr $cc", (BCCTR 100, crrc:$cc)>;
2212 def : InstAlias<"bltctrl $cc", (BCCTRL 12, crrc:$cc)>;
2213 def : InstAlias<"bgtctrl $cc", (BCCTRL 44, crrc:$cc)>;
2214 def : InstAlias<"beqctrl $cc", (BCCTRL 76, crrc:$cc)>;
2215 def : InstAlias<"bunctrl $cc", (BCCTRL 108, crrc:$cc)>;
2216 def : InstAlias<"bsoctrl $cc", (BCCTRL 108, crrc:$cc)>;
2217 def : InstAlias<"bgectrl $cc", (BCCTRL 4, crrc:$cc)>;
2218 def : InstAlias<"bnlctrl $cc", (BCCTRL 4, crrc:$cc)>;
2219 def : InstAlias<"blectrl $cc", (BCCTRL 36, crrc:$cc)>;
2220 def : InstAlias<"bngctrl $cc", (BCCTRL 36, crrc:$cc)>;
2221 def : InstAlias<"bnectrl $cc", (BCCTRL 68, crrc:$cc)>;
2222 def : InstAlias<"bnuctrl $cc", (BCCTRL 100, crrc:$cc)>;
2223 def : InstAlias<"bnsctrl $cc", (BCCTRL 100, crrc:$cc)>;