1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
33 //===----------------------------------------------------------------------===//
34 // PowerPC specific transformation functions and pattern fragments.
37 def SHL32 : SDNodeXForm<imm, [{
38 // Transformation function: 31 - imm
39 return getI32Imm(31 - N->getValue());
42 def SHL64 : SDNodeXForm<imm, [{
43 // Transformation function: 63 - imm
44 return getI32Imm(63 - N->getValue());
47 def SRL32 : SDNodeXForm<imm, [{
48 // Transformation function: 32 - imm
49 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
52 def SRL64 : SDNodeXForm<imm, [{
53 // Transformation function: 64 - imm
54 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
57 def LO16 : SDNodeXForm<imm, [{
58 // Transformation function: get the low 16 bits.
59 return getI32Imm((unsigned short)N->getValue());
62 def HI16 : SDNodeXForm<imm, [{
63 // Transformation function: shift the immediate value down into the low bits.
64 return getI32Imm((unsigned)N->getValue() >> 16);
67 def HA16 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 signed int Val = N->getValue();
70 return getI32Imm((Val - (signed short)Val) >> 16);
74 def immSExt16 : PatLeaf<(imm), [{
75 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
76 // field. Used by instructions like 'addi'.
77 return (int)N->getValue() == (short)N->getValue();
79 def immZExt16 : PatLeaf<(imm), [{
80 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
81 // field. Used by instructions like 'ori'.
82 return (unsigned)N->getValue() == (unsigned short)N->getValue();
85 def imm16Shifted : PatLeaf<(imm), [{
86 // imm16Shifted predicate - True if only bits in the top 16-bits of the
87 // immediate are set. Used by instructions like 'addis'.
88 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
92 // Example of a legalize expander: Only for PPC64.
93 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
94 [(set f64:$tmp , (FCTIDZ f64:$src)),
95 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
96 (store f64:$tmp, i32:$tmpFI),
97 (set i64:$dst, (load i32:$tmpFI))],
101 //===----------------------------------------------------------------------===//
102 // PowerPC Flag Definitions.
104 class isPPC64 { bit PPC64 = 1; }
105 class isVMX { bit VMX = 1; }
107 list<Register> Defs = [CR0];
113 //===----------------------------------------------------------------------===//
114 // PowerPC Operand Definitions.
116 def u5imm : Operand<i32> {
117 let PrintMethod = "printU5ImmOperand";
119 def u6imm : Operand<i32> {
120 let PrintMethod = "printU6ImmOperand";
122 def s16imm : Operand<i32> {
123 let PrintMethod = "printS16ImmOperand";
125 def u16imm : Operand<i32> {
126 let PrintMethod = "printU16ImmOperand";
128 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
129 let PrintMethod = "printS16X4ImmOperand";
131 def target : Operand<OtherVT> {
132 let PrintMethod = "printBranchOperand";
134 def calltarget : Operand<i32> {
135 let PrintMethod = "printCallOperand";
137 def aaddr : Operand<i32> {
138 let PrintMethod = "printAbsAddrOperand";
140 def piclabel: Operand<i32> {
141 let PrintMethod = "printPICLabel";
143 def symbolHi: Operand<i32> {
144 let PrintMethod = "printSymbolHi";
146 def symbolLo: Operand<i32> {
147 let PrintMethod = "printSymbolLo";
149 def crbitm: Operand<i8> {
150 let PrintMethod = "printcrbitm";
155 //===----------------------------------------------------------------------===//
156 // PowerPC Instruction Definitions.
158 // Pseudo-instructions:
159 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
162 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
163 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
165 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
166 [(set GPRC:$rD, (undef))]>;
167 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
168 [(set F8RC:$rD, (undef))]>;
169 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
170 [(set F4RC:$rD, (undef))]>;
172 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
173 // scheduler into a branch sequence.
174 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
175 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
176 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
177 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
178 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
179 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
180 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
184 let isTerminator = 1 in {
186 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
187 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
191 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
193 let isBranch = 1, isTerminator = 1 in {
194 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
195 target:$true, target:$false),
196 "; COND_BRANCH", []>;
197 def B : IForm<18, 0, 0, (ops target:$dst),
201 // FIXME: 4*CR# needs to be added to the BI field!
202 // This will only work for CR0 as it stands now
203 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
204 "blt $crS, $block", BrB>;
205 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
206 "ble $crS, $block", BrB>;
207 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
208 "beq $crS, $block", BrB>;
209 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
210 "bge $crS, $block", BrB>;
211 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
212 "bgt $crS, $block", BrB>;
213 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
214 "bne $crS, $block", BrB>;
215 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
216 "bun $crS, $block", BrB>;
217 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
218 "bnu $crS, $block", BrB>;
222 // All calls clobber the non-callee saved registers...
223 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
224 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
226 CR0,CR1,CR5,CR6,CR7] in {
227 // Convenient aliases for call instructions
228 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
229 "bl $func", BrB, []>;
230 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
231 "bla $func", BrB, []>;
232 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
235 // D-Form instructions. Most instructions that perform an operation on a
236 // register and an immediate are of this type.
239 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
240 "lbz $rD, $disp($rA)", LdStGeneral>;
241 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
242 "lha $rD, $disp($rA)", LdStLHA>;
243 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
244 "lhz $rD, $disp($rA)", LdStGeneral>;
245 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
246 "lmw $rD, $disp($rA)", LdStLMW>;
247 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
248 "lwz $rD, $disp($rA)", LdStGeneral>;
249 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
250 "lwzu $rD, $disp($rA)", LdStGeneral>;
252 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
253 "addi $rD, $rA, $imm", IntGeneral,
254 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
255 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
256 "addic $rD, $rA, $imm", IntGeneral,
258 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
259 "addic. $rD, $rA, $imm", IntGeneral,
261 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
262 "addis $rD, $rA, $imm", IntGeneral,
263 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
264 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
265 "la $rD, $sym($rA)", IntGeneral,
266 [(set GPRC:$rD, (add GPRC:$rA,
267 (PPClo tglobaladdr:$sym, 0)))]>;
268 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
269 "mulli $rD, $rA, $imm", IntMulLI,
270 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
271 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
272 "subfic $rD, $rA, $imm", IntGeneral,
273 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
274 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
275 "li $rD, $imm", IntGeneral,
276 [(set GPRC:$rD, immSExt16:$imm)]>;
277 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
278 "lis $rD, $imm", IntGeneral,
279 [(set GPRC:$rD, imm16Shifted:$imm)]>;
281 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
282 "stmw $rS, $disp($rA)", LdStLMW>;
283 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
284 "stb $rS, $disp($rA)", LdStGeneral>;
285 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
286 "sth $rS, $disp($rA)", LdStGeneral>;
287 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
288 "stw $rS, $disp($rA)", LdStGeneral>;
289 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
290 "stwu $rS, $disp($rA)", LdStGeneral>;
292 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
293 "andi. $dst, $src1, $src2", IntGeneral,
295 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
296 "andis. $dst, $src1, $src2", IntGeneral,
298 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
299 "ori $dst, $src1, $src2", IntGeneral,
300 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
301 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
302 "oris $dst, $src1, $src2", IntGeneral,
303 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
304 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
305 "xori $dst, $src1, $src2", IntGeneral,
306 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
307 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
308 "xoris $dst, $src1, $src2", IntGeneral,
309 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
310 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>;
311 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
312 "cmpi $crD, $L, $rA, $imm", IntCompare>;
313 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
314 "cmpwi $crD, $rA, $imm", IntCompare>;
315 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
316 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
317 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
318 "cmpli $dst, $size, $src1, $src2", IntCompare>;
319 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
320 "cmplwi $dst, $src1, $src2", IntCompare>;
321 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
322 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
324 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
325 "lfs $rD, $disp($rA)", LdStLFDU>;
326 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
327 "lfd $rD, $disp($rA)", LdStLFD>;
330 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
331 "stfs $rS, $disp($rA)", LdStUX>;
332 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
333 "stfd $rS, $disp($rA)", LdStUX>;
336 // DS-Form instructions. Load/Store instructions available in PPC-64
339 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
340 "lwa $rT, $DS($rA)", LdStLWA>, isPPC64;
341 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
342 "ld $rT, $DS($rA)", LdStLD>, isPPC64;
345 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
346 "std $rT, $DS($rA)", LdStSTD>, isPPC64;
347 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
348 "stdu $rT, $DS($rA)", LdStSTD>, isPPC64;
351 // X-Form instructions. Most instructions that perform an operation on a
352 // register and another register are of this type.
355 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
356 "lbzx $dst, $base, $index", LdStGeneral>;
357 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
358 "lhax $dst, $base, $index", LdStLHA>;
359 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
360 "lhzx $dst, $base, $index", LdStGeneral>;
361 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
362 "lwax $dst, $base, $index", LdStLHA>, isPPC64;
363 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
364 "lwzx $dst, $base, $index", LdStGeneral>;
365 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
366 "ldx $dst, $base, $index", LdStLD>, isPPC64;
367 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
368 "lvebx $vD, $base, $rA", LdStGeneral>;
369 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
370 "lvehx $vD, $base, $rA", LdStGeneral>;
371 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
372 "lvewx $vD, $base, $rA", LdStGeneral>;
373 def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
374 "lvx $vD, $base, $rA", LdStGeneral>;
375 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
376 "lvsl $vD, $base, $rA", LdStGeneral>;
377 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
378 "lvsl $vD, $base, $rA", LdStGeneral>;
380 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
381 "nand $rA, $rS, $rB", IntGeneral,
382 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
383 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
384 "and $rA, $rS, $rB", IntGeneral,
385 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
386 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
387 "and. $rA, $rS, $rB", IntGeneral,
389 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
390 "andc $rA, $rS, $rB", IntGeneral,
391 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
392 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
393 "or $rA, $rS, $rB", IntGeneral,
394 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
395 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
396 "or $rA, $rS, $rB", IntGeneral,
397 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
398 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
399 "or $rA, $rS, $rB", IntGeneral,
401 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
402 "or $rA, $rS, $rB", IntGeneral,
404 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
405 "nor $rA, $rS, $rB", IntGeneral,
406 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
407 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
408 "or. $rA, $rS, $rB", IntGeneral,
410 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
411 "orc $rA, $rS, $rB", IntGeneral,
412 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
413 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
414 "eqv $rA, $rS, $rB", IntGeneral,
415 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
416 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
417 "xor $rA, $rS, $rB", IntGeneral,
418 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
419 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
420 "sld $rA, $rS, $rB", IntRotateD,
421 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
422 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
423 "slw $rA, $rS, $rB", IntGeneral,
424 [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
425 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
426 "srd $rA, $rS, $rB", IntRotateD,
427 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
428 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
429 "srw $rA, $rS, $rB", IntGeneral,
430 [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
431 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
432 "srad $rA, $rS, $rB", IntRotateD,
433 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
434 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
435 "sraw $rA, $rS, $rB", IntShift,
436 [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
438 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
439 "stbx $rS, $rA, $rB", LdStGeneral>;
440 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
441 "sthx $rS, $rA, $rB", LdStGeneral>;
442 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
443 "stwx $rS, $rA, $rB", LdStGeneral>;
444 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
445 "stwux $rS, $rA, $rB", LdStGeneral>;
446 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
447 "stdx $rS, $rA, $rB", LdStSTD>, isPPC64;
448 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
449 "stdux $rS, $rA, $rB", LdStSTD>, isPPC64;
450 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
451 "stvebx $rS, $rA, $rB", LdStGeneral>;
452 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
453 "stvehx $rS, $rA, $rB", LdStGeneral>;
454 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
455 "stvewx $rS, $rA, $rB", LdStGeneral>;
456 def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
457 "stvx $rS, $rA, $rB", LdStGeneral>;
459 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
460 "srawi $rA, $rS, $SH", IntShift,
461 [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
462 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
463 "cntlzw $rA, $rS", IntGeneral,
464 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
465 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
466 "extsb $rA, $rS", IntGeneral,
467 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
468 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
469 "extsh $rA, $rS", IntGeneral,
470 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
471 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
472 "extsw $rA, $rS", IntGeneral,
473 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
474 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
475 "cmp $crD, $long, $rA, $rB", IntCompare>;
476 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
477 "cmpl $crD, $long, $rA, $rB", IntCompare>;
478 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
479 "cmpw $crD, $rA, $rB", IntCompare>;
480 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
481 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
482 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
483 "cmplw $crD, $rA, $rB", IntCompare>;
484 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
485 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
486 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
487 // "fcmpo $crD, $fA, $fB", FPCompare>;
488 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
489 "fcmpu $crD, $fA, $fB", FPCompare>;
490 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
491 "fcmpu $crD, $fA, $fB", FPCompare>;
494 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
495 "lfsx $dst, $base, $index", LdStLFDU>;
496 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
497 "lfdx $dst, $base, $index", LdStLFDU>;
499 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
500 "fcfid $frD, $frB", FPGeneral,
501 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
502 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
503 "fctidz $frD, $frB", FPGeneral,
504 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
505 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
506 "fctiwz $frD, $frB", FPGeneral,
507 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
508 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
509 "frsp $frD, $frB", FPGeneral,
510 [(set F4RC:$frD, (fround F8RC:$frB))]>;
511 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
512 "fsqrt $frD, $frB", FPSqrt,
513 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
514 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
515 "fsqrts $frD, $frB", FPSqrt,
516 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
518 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
519 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
520 "fmr $frD, $frB", FPGeneral,
521 []>; // (set F4RC:$frD, F4RC:$frB)
522 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
523 "fmr $frD, $frB", FPGeneral,
524 []>; // (set F8RC:$frD, F8RC:$frB)
525 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
526 "fmr $frD, $frB", FPGeneral,
527 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
529 // These are artificially split into two different forms, for 4/8 byte FP.
530 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
531 "fabs $frD, $frB", FPGeneral,
532 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
533 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
534 "fabs $frD, $frB", FPGeneral,
535 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
536 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
537 "fnabs $frD, $frB", FPGeneral,
538 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
539 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
540 "fnabs $frD, $frB", FPGeneral,
541 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
542 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
543 "fneg $frD, $frB", FPGeneral,
544 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
545 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
546 "fneg $frD, $frB", FPGeneral,
547 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
551 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
552 "stfsx $frS, $rA, $rB", LdStUX>;
553 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
554 "stfdx $frS, $rA, $rB", LdStUX>;
557 // XL-Form instructions. condition register logical ops.
559 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
560 "mcrf $BF, $BFA", BrMCR>;
562 // XFX-Form instructions. Instructions that deal with SPRs
564 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
565 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
566 // which means the SPR value needs to be multiplied by a factor of 32.
567 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
568 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
569 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
570 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
571 "mtcrf $FXM, $rS", BrMCRX>;
572 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
573 "mfcr $rT, $FXM", SprMFCR>;
574 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
575 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
576 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
579 // XS-Form instructions. Just 'sradi'
581 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
582 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
584 // XO-Form instructions. Arithmetic instructions that can set overflow bit
586 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
587 "add $rT, $rA, $rB", IntGeneral,
588 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
589 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
590 "add $rT, $rA, $rB", IntGeneral,
591 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
592 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
593 "addc $rT, $rA, $rB", IntGeneral,
595 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
596 "adde $rT, $rA, $rB", IntGeneral,
598 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
599 "divd $rT, $rA, $rB", IntDivD,
600 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
601 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
602 "divdu $rT, $rA, $rB", IntDivD,
603 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
604 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
605 "divw $rT, $rA, $rB", IntDivW,
606 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
607 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
608 "divwu $rT, $rA, $rB", IntDivW,
609 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
610 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
611 "mulhd $rT, $rA, $rB", IntMulHW,
612 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
613 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
614 "mulhdu $rT, $rA, $rB", IntMulHWU,
615 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
616 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
617 "mulhw $rT, $rA, $rB", IntMulHW,
618 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
619 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
620 "mulhwu $rT, $rA, $rB", IntMulHWU,
621 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
622 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
623 "mulld $rT, $rA, $rB", IntMulHD,
624 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
625 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
626 "mullw $rT, $rA, $rB", IntMulHW,
627 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
628 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
629 "subf $rT, $rA, $rB", IntGeneral,
630 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
631 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
632 "subfc $rT, $rA, $rB", IntGeneral,
634 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
635 "subfe $rT, $rA, $rB", IntGeneral,
637 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
638 "addme $rT, $rA", IntGeneral,
640 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
641 "addze $rT, $rA", IntGeneral,
643 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
644 "neg $rT, $rA", IntGeneral,
645 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
646 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
647 "subfze $rT, $rA", IntGeneral,
650 // A-Form instructions. Most of the instructions executed in the FPU are of
653 def FMADD : AForm_1<63, 29,
654 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
655 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
656 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
658 def FMADDS : AForm_1<59, 29,
659 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
660 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
661 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
663 def FMSUB : AForm_1<63, 28,
664 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
665 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
666 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
668 def FMSUBS : AForm_1<59, 28,
669 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
670 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
671 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
673 def FNMADD : AForm_1<63, 31,
674 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
675 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
676 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
678 def FNMADDS : AForm_1<59, 31,
679 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
680 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
681 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
683 def FNMSUB : AForm_1<63, 30,
684 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
685 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
686 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
688 def FNMSUBS : AForm_1<59, 30,
689 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
690 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
691 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
693 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
694 // having 4 of these, force the comparison to always be an 8-byte double (code
695 // should use an FMRSD if the input comparison value really wants to be a float)
696 // and 4/8 byte forms for the result and operand type..
697 def FSELD : AForm_1<63, 23,
698 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
699 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
700 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
701 def FSELS : AForm_1<63, 23,
702 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
703 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
704 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
705 def FADD : AForm_2<63, 21,
706 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
707 "fadd $FRT, $FRA, $FRB", FPGeneral,
708 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
709 def FADDS : AForm_2<59, 21,
710 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
711 "fadds $FRT, $FRA, $FRB", FPGeneral,
712 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
713 def FDIV : AForm_2<63, 18,
714 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
715 "fdiv $FRT, $FRA, $FRB", FPDivD,
716 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
717 def FDIVS : AForm_2<59, 18,
718 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
719 "fdivs $FRT, $FRA, $FRB", FPDivS,
720 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
721 def FMUL : AForm_3<63, 25,
722 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
723 "fmul $FRT, $FRA, $FRB", FPFused,
724 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
725 def FMULS : AForm_3<59, 25,
726 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
727 "fmuls $FRT, $FRA, $FRB", FPGeneral,
728 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
729 def FSUB : AForm_2<63, 20,
730 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
731 "fsub $FRT, $FRA, $FRB", FPGeneral,
732 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
733 def FSUBS : AForm_2<59, 20,
734 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
735 "fsubs $FRT, $FRA, $FRB", FPGeneral,
736 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
738 // M-Form instructions. rotate and mask instructions.
740 let isTwoAddress = 1, isCommutable = 1 in {
741 // RLWIMI can be commuted if the rotate amount is zero.
742 def RLWIMI : MForm_2<20,
743 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
744 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
746 def RLDIMI : MDForm_1<30, 3,
747 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
748 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
751 def RLWINM : MForm_2<21,
752 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
753 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
755 def RLWINMo : MForm_2<21,
756 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
757 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
759 def RLWNM : MForm_2<23,
760 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
761 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
764 // MD-Form instructions. 64 bit rotate instructions.
766 def RLDICL : MDForm_1<30, 0,
767 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
768 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
770 def RLDICR : MDForm_1<30, 1,
771 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
772 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
775 // VA-Form instructions. 3-input AltiVec ops.
776 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
777 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
778 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
780 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
781 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
782 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
786 // VX-Form instructions. AltiVec arithmetic ops.
787 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
788 "vaddfp $vD, $vA, $vB", VecFP,
789 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
790 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
791 "vcfsx $vD, $vB, $UIMM", VecFP,
793 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
794 "vcfux $vD, $vB, $UIMM", VecFP,
796 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
797 "vctsxs $vD, $vB, $UIMM", VecFP,
799 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
800 "vctuxs $vD, $vB, $UIMM", VecFP,
802 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
803 "vexptefp $vD, $vB", VecFP,
805 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
806 "vlogefp $vD, $vB", VecFP,
808 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
809 "vmaxfp $vD, $vA, $vB", VecFP,
811 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
812 "vminfp $vD, $vA, $vB", VecFP,
814 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
815 "vrefp $vD, $vB", VecFP,
817 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
818 "vrfim $vD, $vB", VecFP,
820 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
821 "vrfin $vD, $vB", VecFP,
823 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
824 "vrfip $vD, $vB", VecFP,
826 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
827 "vrfiz $vD, $vB", VecFP,
829 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
830 "vrsqrtefp $vD, $vB", VecFP,
832 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
833 "vsubfp $vD, $vA, $vB", VecFP,
834 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
836 //===----------------------------------------------------------------------===//
837 // PowerPC Instruction Patterns
840 // Arbitrary immediate support. Implement in terms of LIS/ORI.
841 def : Pat<(i32 imm:$imm),
842 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
844 // Implement the 'not' operation with the NOR instruction.
845 def NOT : Pat<(not GPRC:$in),
846 (NOR GPRC:$in, GPRC:$in)>;
848 // ADD an arbitrary immediate.
849 def : Pat<(add GPRC:$in, imm:$imm),
850 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
851 // OR an arbitrary immediate.
852 def : Pat<(or GPRC:$in, imm:$imm),
853 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
854 // XOR an arbitrary immediate.
855 def : Pat<(xor GPRC:$in, imm:$imm),
856 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
857 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
858 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
859 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
861 def : Pat<(zext GPRC:$in),
862 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
863 def : Pat<(anyext GPRC:$in),
864 (OR4To8 GPRC:$in, GPRC:$in)>;
865 def : Pat<(trunc G8RC:$in),
866 (OR8To4 G8RC:$in, G8RC:$in)>;
869 def : Pat<(shl GPRC:$in, imm:$imm),
870 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
871 def : Pat<(shl G8RC:$in, imm:$imm),
872 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
874 def : Pat<(srl GPRC:$in, imm:$imm),
875 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
876 def : Pat<(srl G8RC:$in, imm:$imm),
877 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
879 // Hi and Lo for Darwin Global Addresses.
880 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS tglobaladdr:$in)>;
881 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI tglobaladdr:$in)>;
882 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
883 (ADDIS GPRC:$in, tglobaladdr:$g)>;
885 // Same as above, but using a temporary. FIXME: implement temporaries :)
887 def : Pattern<(xor GPRC:$in, imm:$imm),
888 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
889 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
892 //===----------------------------------------------------------------------===//
893 // PowerPCInstrInfo Definition
895 def PowerPCInstrInfo : InstrInfo {
898 let TSFlagsFields = [ "VMX", "PPC64" ];
899 let TSFlagsShifts = [ 0, 1 ];
901 let isLittleEndianEncoding = 1;