1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
24 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
26 def SDT_PPCCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
27 def SDT_PPCCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
29 def SDT_PPCvperm : SDTypeProfile<1, 3, [
30 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
33 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
34 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
37 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
38 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
41 def SDT_PPClbrx : SDTypeProfile<1, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
44 def SDT_PPCstbrx : SDTypeProfile<0, 4, [
45 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
48 //===----------------------------------------------------------------------===//
49 // PowerPC specific DAG Nodes.
52 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
53 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
54 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
55 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, [SDNPHasChain]>;
57 // This sequence is used for long double->int conversions. It changes the
58 // bits in the FPSCR which is not modelled.
59 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
61 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
62 [SDNPInFlag, SDNPOutFlag]>;
63 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
64 [SDNPInFlag, SDNPOutFlag]>;
65 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
66 [SDNPInFlag, SDNPOutFlag]>;
67 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
68 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
72 def PPCfsel : SDNode<"PPCISD::FSEL",
73 // Type constraint for fsel.
74 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
75 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
77 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
78 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
79 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
80 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
82 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
84 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
85 // amounts. These nodes are generated by the multi-precision shift code.
86 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
87 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
88 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
90 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
91 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
93 // These are target-independent nodes, but have target-specific formats.
94 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq_start,
95 [SDNPHasChain, SDNPOutFlag]>;
96 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq_end,
97 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
99 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
100 def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
101 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
102 def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
103 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
104 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
105 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
106 def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTRet,
107 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
109 def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTRet,
110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
112 def retflag : SDNode<"PPCISD::RET_FLAG", SDTRet,
113 [SDNPHasChain, SDNPOptInFlag]>;
115 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
116 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
118 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
119 [SDNPHasChain, SDNPOptInFlag]>;
121 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
122 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
124 // Instructions to support dynamic alloca.
125 def SDTDynOp : SDTypeProfile<1, 2, []>;
126 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
128 //===----------------------------------------------------------------------===//
129 // PowerPC specific transformation functions and pattern fragments.
132 def SHL32 : SDNodeXForm<imm, [{
133 // Transformation function: 31 - imm
134 return getI32Imm(31 - N->getValue());
137 def SRL32 : SDNodeXForm<imm, [{
138 // Transformation function: 32 - imm
139 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
142 def LO16 : SDNodeXForm<imm, [{
143 // Transformation function: get the low 16 bits.
144 return getI32Imm((unsigned short)N->getValue());
147 def HI16 : SDNodeXForm<imm, [{
148 // Transformation function: shift the immediate value down into the low bits.
149 return getI32Imm((unsigned)N->getValue() >> 16);
152 def HA16 : SDNodeXForm<imm, [{
153 // Transformation function: shift the immediate value down into the low bits.
154 signed int Val = N->getValue();
155 return getI32Imm((Val - (signed short)Val) >> 16);
157 def MB : SDNodeXForm<imm, [{
158 // Transformation function: get the start bit of a mask
160 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
161 return getI32Imm(mb);
164 def ME : SDNodeXForm<imm, [{
165 // Transformation function: get the end bit of a mask
167 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
168 return getI32Imm(me);
170 def maskimm32 : PatLeaf<(imm), [{
171 // maskImm predicate - True if immediate is a run of ones.
173 if (N->getValueType(0) == MVT::i32)
174 return isRunOfOnes((unsigned)N->getValue(), mb, me);
179 def immSExt16 : PatLeaf<(imm), [{
180 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
181 // field. Used by instructions like 'addi'.
182 if (N->getValueType(0) == MVT::i32)
183 return (int32_t)N->getValue() == (short)N->getValue();
185 return (int64_t)N->getValue() == (short)N->getValue();
187 def immZExt16 : PatLeaf<(imm), [{
188 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
189 // field. Used by instructions like 'ori'.
190 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
193 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
194 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
195 // identical in 32-bit mode, but in 64-bit mode, they return true if the
196 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
198 def imm16ShiftedZExt : PatLeaf<(imm), [{
199 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
200 // immediate are set. Used by instructions like 'xoris'.
201 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
204 def imm16ShiftedSExt : PatLeaf<(imm), [{
205 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
206 // immediate are set. Used by instructions like 'addis'. Identical to
207 // imm16ShiftedZExt in 32-bit mode.
208 if (N->getValue() & 0xFFFF) return false;
209 if (N->getValueType(0) == MVT::i32)
211 // For 64-bit, make sure it is sext right.
212 return N->getValue() == (uint64_t)(int)N->getValue();
216 //===----------------------------------------------------------------------===//
217 // PowerPC Flag Definitions.
219 class isPPC64 { bit PPC64 = 1; }
221 list<Register> Defs = [CR0];
225 class RegConstraint<string C> {
226 string Constraints = C;
228 class NoEncode<string E> {
229 string DisableEncoding = E;
233 //===----------------------------------------------------------------------===//
234 // PowerPC Operand Definitions.
236 def s5imm : Operand<i32> {
237 let PrintMethod = "printS5ImmOperand";
239 def u5imm : Operand<i32> {
240 let PrintMethod = "printU5ImmOperand";
242 def u6imm : Operand<i32> {
243 let PrintMethod = "printU6ImmOperand";
245 def s16imm : Operand<i32> {
246 let PrintMethod = "printS16ImmOperand";
248 def u16imm : Operand<i32> {
249 let PrintMethod = "printU16ImmOperand";
251 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
252 let PrintMethod = "printS16X4ImmOperand";
254 def target : Operand<OtherVT> {
255 let PrintMethod = "printBranchOperand";
257 def calltarget : Operand<iPTR> {
258 let PrintMethod = "printCallOperand";
260 def aaddr : Operand<iPTR> {
261 let PrintMethod = "printAbsAddrOperand";
263 def piclabel: Operand<iPTR> {
264 let PrintMethod = "printPICLabel";
266 def symbolHi: Operand<i32> {
267 let PrintMethod = "printSymbolHi";
269 def symbolLo: Operand<i32> {
270 let PrintMethod = "printSymbolLo";
272 def crbitm: Operand<i8> {
273 let PrintMethod = "printcrbitm";
276 def memri : Operand<iPTR> {
277 let PrintMethod = "printMemRegImm";
278 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
280 def memrr : Operand<iPTR> {
281 let PrintMethod = "printMemRegReg";
282 let MIOperandInfo = (ops ptr_rc, ptr_rc);
284 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
285 let PrintMethod = "printMemRegImmShifted";
286 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
289 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
290 // that doesn't matter.
291 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
292 (ops (i32 20), CR0)> {
293 let PrintMethod = "printPredicateOperand";
296 // Define PowerPC specific addressing mode.
297 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
298 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
299 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
300 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
302 /// This is just the offset part of iaddr, used for preinc.
303 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
305 //===----------------------------------------------------------------------===//
306 // PowerPC Instruction Predicate Definitions.
307 def FPContractions : Predicate<"!NoExcessFPPrecision">;
308 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
309 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
312 //===----------------------------------------------------------------------===//
313 // PowerPC Instruction Definitions.
315 // Pseudo-instructions:
317 let hasCtrlDep = 1 in {
318 let Defs = [R1], Uses = [R1] in {
319 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
320 "${:comment} ADJCALLSTACKDOWN",
321 [(callseq_start imm:$amt)]>;
322 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
323 "${:comment} ADJCALLSTACKUP",
324 [(callseq_end imm:$amt1, imm:$amt2)]>;
327 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
328 "UPDATE_VRSAVE $rD, $rS", []>;
331 let Defs = [R1], Uses = [R1] in
332 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
333 "${:comment} DYNALLOC $result, $negsize, $fpsi",
335 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
337 def IMPLICIT_DEF_GPRC: Pseudo<(outs GPRC:$rD), (ins),
338 "${:comment}IMPLICIT_DEF_GPRC $rD",
339 [(set GPRC:$rD, (undef))]>;
340 def IMPLICIT_DEF_F8 : Pseudo<(outs F8RC:$rD), (ins),
341 "${:comment} IMPLICIT_DEF_F8 $rD",
342 [(set F8RC:$rD, (undef))]>;
343 def IMPLICIT_DEF_F4 : Pseudo<(outs F4RC:$rD), (ins),
344 "${:comment} IMPLICIT_DEF_F4 $rD",
345 [(set F4RC:$rD, (undef))]>;
347 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
348 // scheduler into a branch sequence.
349 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
350 PPC970_Single = 1 in {
351 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
352 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
354 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
355 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
357 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
358 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
360 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
361 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
363 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
364 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
368 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
370 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
371 "b${p:cc}lr ${p:reg}", BrB,
373 let isBranch = 1, isIndirectBranch = 1 in
374 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
380 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
383 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
384 let isBarrier = 1 in {
385 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
390 // BCC represents an arbitrary conditional branch on a predicate.
391 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
392 // a two-value operand where a dag node expects two operands. :(
393 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
394 "b${cond:cc} ${cond:reg}, $dst"
395 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
399 let isCall = 1, PPC970_Unit = 7,
400 // All calls clobber the non-callee saved registers...
401 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
402 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
403 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
405 CR0,CR1,CR5,CR6,CR7] in {
406 // Convenient aliases for call instructions
407 def BL_Macho : IForm<18, 0, 1,
408 (outs), (ins calltarget:$func, variable_ops),
409 "bl $func", BrB, []>; // See Pat patterns below.
410 def BLA_Macho : IForm<18, 1, 1,
411 (outs), (ins aaddr:$func, variable_ops),
412 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
413 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
414 (outs), (ins variable_ops),
416 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
420 let isCall = 1, PPC970_Unit = 7,
421 // All calls clobber the non-callee saved registers...
422 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
423 F0,F1,F2,F3,F4,F5,F6,F7,F8,
424 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
426 CR0,CR1,CR5,CR6,CR7] in {
427 // Convenient aliases for call instructions
428 def BL_ELF : IForm<18, 0, 1,
429 (outs), (ins calltarget:$func, variable_ops),
430 "bl $func", BrB, []>; // See Pat patterns below.
431 def BLA_ELF : IForm<18, 1, 1,
432 (outs), (ins aaddr:$func, variable_ops),
434 [(PPCcall_ELF (i32 imm:$func))]>;
435 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
436 (outs), (ins variable_ops),
438 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
441 // DCB* instructions.
442 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
443 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
444 PPC970_DGroup_Single;
445 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
446 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
447 PPC970_DGroup_Single;
448 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
449 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
450 PPC970_DGroup_Single;
451 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
452 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
453 PPC970_DGroup_Single;
454 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
455 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
456 PPC970_DGroup_Single;
457 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
458 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
459 PPC970_DGroup_Single;
460 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
461 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
462 PPC970_DGroup_Single;
463 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
464 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
465 PPC970_DGroup_Single;
467 //===----------------------------------------------------------------------===//
468 // PPC32 Load Instructions.
471 // Unindexed (r+i) Loads.
472 let isLoad = 1, PPC970_Unit = 2 in {
473 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
474 "lbz $rD, $src", LdStGeneral,
475 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
476 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
477 "lha $rD, $src", LdStLHA,
478 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
479 PPC970_DGroup_Cracked;
480 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
481 "lhz $rD, $src", LdStGeneral,
482 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
483 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
484 "lwz $rD, $src", LdStGeneral,
485 [(set GPRC:$rD, (load iaddr:$src))]>;
487 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
488 "lfs $rD, $src", LdStLFDU,
489 [(set F4RC:$rD, (load iaddr:$src))]>;
490 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
491 "lfd $rD, $src", LdStLFD,
492 [(set F8RC:$rD, (load iaddr:$src))]>;
495 // Unindexed (r+i) Loads with Update (preinc).
496 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
497 "lbzu $rD, $addr", LdStGeneral,
498 []>, RegConstraint<"$addr.reg = $ea_result">,
499 NoEncode<"$ea_result">;
501 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
502 "lhau $rD, $addr", LdStGeneral,
503 []>, RegConstraint<"$addr.reg = $ea_result">,
504 NoEncode<"$ea_result">;
506 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
507 "lhzu $rD, $addr", LdStGeneral,
508 []>, RegConstraint<"$addr.reg = $ea_result">,
509 NoEncode<"$ea_result">;
511 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
512 "lwzu $rD, $addr", LdStGeneral,
513 []>, RegConstraint<"$addr.reg = $ea_result">,
514 NoEncode<"$ea_result">;
516 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
517 "lfs $rD, $addr", LdStLFDU,
518 []>, RegConstraint<"$addr.reg = $ea_result">,
519 NoEncode<"$ea_result">;
521 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
522 "lfd $rD, $addr", LdStLFD,
523 []>, RegConstraint<"$addr.reg = $ea_result">,
524 NoEncode<"$ea_result">;
527 // Indexed (r+r) Loads.
529 let isLoad = 1, PPC970_Unit = 2 in {
530 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
531 "lbzx $rD, $src", LdStGeneral,
532 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
533 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
534 "lhax $rD, $src", LdStLHA,
535 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
536 PPC970_DGroup_Cracked;
537 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
538 "lhzx $rD, $src", LdStGeneral,
539 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
540 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
541 "lwzx $rD, $src", LdStGeneral,
542 [(set GPRC:$rD, (load xaddr:$src))]>;
545 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
546 "lhbrx $rD, $src", LdStGeneral,
547 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
548 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
549 "lwbrx $rD, $src", LdStGeneral,
550 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
552 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
553 "lfsx $frD, $src", LdStLFDU,
554 [(set F4RC:$frD, (load xaddr:$src))]>;
555 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
556 "lfdx $frD, $src", LdStLFDU,
557 [(set F8RC:$frD, (load xaddr:$src))]>;
560 //===----------------------------------------------------------------------===//
561 // PPC32 Store Instructions.
564 // Unindexed (r+i) Stores.
565 let isStore = 1, PPC970_Unit = 2 in {
566 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
567 "stb $rS, $src", LdStGeneral,
568 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
569 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
570 "sth $rS, $src", LdStGeneral,
571 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
572 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
573 "stw $rS, $src", LdStGeneral,
574 [(store GPRC:$rS, iaddr:$src)]>;
575 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
576 "stfs $rS, $dst", LdStUX,
577 [(store F4RC:$rS, iaddr:$dst)]>;
578 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
579 "stfd $rS, $dst", LdStUX,
580 [(store F8RC:$rS, iaddr:$dst)]>;
583 // Unindexed (r+i) Stores with Update (preinc).
584 let isStore = 1, PPC970_Unit = 2 in {
585 def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
586 symbolLo:$ptroff, ptr_rc:$ptrreg),
587 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
588 [(set ptr_rc:$ea_res,
589 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
590 iaddroff:$ptroff))]>,
591 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
592 def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
593 symbolLo:$ptroff, ptr_rc:$ptrreg),
594 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
595 [(set ptr_rc:$ea_res,
596 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
597 iaddroff:$ptroff))]>,
598 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
599 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
600 symbolLo:$ptroff, ptr_rc:$ptrreg),
601 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
602 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
603 iaddroff:$ptroff))]>,
604 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
605 def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
606 symbolLo:$ptroff, ptr_rc:$ptrreg),
607 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
608 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
609 iaddroff:$ptroff))]>,
610 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
611 def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
612 symbolLo:$ptroff, ptr_rc:$ptrreg),
613 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
614 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
615 iaddroff:$ptroff))]>,
616 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
620 // Indexed (r+r) Stores.
622 let isStore = 1, PPC970_Unit = 2 in {
623 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
624 "stbx $rS, $dst", LdStGeneral,
625 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
626 PPC970_DGroup_Cracked;
627 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
628 "sthx $rS, $dst", LdStGeneral,
629 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
630 PPC970_DGroup_Cracked;
631 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
632 "stwx $rS, $dst", LdStGeneral,
633 [(store GPRC:$rS, xaddr:$dst)]>,
634 PPC970_DGroup_Cracked;
635 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
636 "stwux $rS, $rA, $rB", LdStGeneral,
638 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
639 "sthbrx $rS, $dst", LdStGeneral,
640 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
641 PPC970_DGroup_Cracked;
642 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
643 "stwbrx $rS, $dst", LdStGeneral,
644 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
645 PPC970_DGroup_Cracked;
647 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
648 "stfiwx $frS, $dst", LdStUX,
649 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
650 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
651 "stfsx $frS, $dst", LdStUX,
652 [(store F4RC:$frS, xaddr:$dst)]>;
653 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
654 "stfdx $frS, $dst", LdStUX,
655 [(store F8RC:$frS, xaddr:$dst)]>;
659 //===----------------------------------------------------------------------===//
660 // PPC32 Arithmetic Instructions.
663 let PPC970_Unit = 1 in { // FXU Operations.
664 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
665 "addi $rD, $rA, $imm", IntGeneral,
666 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
667 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
668 "addic $rD, $rA, $imm", IntGeneral,
669 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
670 PPC970_DGroup_Cracked;
671 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
672 "addic. $rD, $rA, $imm", IntGeneral,
674 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
675 "addis $rD, $rA, $imm", IntGeneral,
676 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
677 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
678 "la $rD, $sym($rA)", IntGeneral,
679 [(set GPRC:$rD, (add GPRC:$rA,
680 (PPClo tglobaladdr:$sym, 0)))]>;
681 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
682 "mulli $rD, $rA, $imm", IntMulLI,
683 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
684 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
685 "subfic $rD, $rA, $imm", IntGeneral,
686 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
687 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
688 "li $rD, $imm", IntGeneral,
689 [(set GPRC:$rD, immSExt16:$imm)]>;
690 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
691 "lis $rD, $imm", IntGeneral,
692 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
695 let PPC970_Unit = 1 in { // FXU Operations.
696 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
697 "andi. $dst, $src1, $src2", IntGeneral,
698 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
700 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
701 "andis. $dst, $src1, $src2", IntGeneral,
702 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
704 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
705 "ori $dst, $src1, $src2", IntGeneral,
706 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
707 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
708 "oris $dst, $src1, $src2", IntGeneral,
709 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
710 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
711 "xori $dst, $src1, $src2", IntGeneral,
712 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
713 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
714 "xoris $dst, $src1, $src2", IntGeneral,
715 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
716 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
718 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
719 "cmpwi $crD, $rA, $imm", IntCompare>;
720 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
721 "cmplwi $dst, $src1, $src2", IntCompare>;
725 let PPC970_Unit = 1 in { // FXU Operations.
726 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
727 "nand $rA, $rS, $rB", IntGeneral,
728 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
729 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
730 "and $rA, $rS, $rB", IntGeneral,
731 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
732 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
733 "andc $rA, $rS, $rB", IntGeneral,
734 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
735 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
736 "or $rA, $rS, $rB", IntGeneral,
737 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
738 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
739 "nor $rA, $rS, $rB", IntGeneral,
740 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
741 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
742 "orc $rA, $rS, $rB", IntGeneral,
743 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
744 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
745 "eqv $rA, $rS, $rB", IntGeneral,
746 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
747 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
748 "xor $rA, $rS, $rB", IntGeneral,
749 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
750 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
751 "slw $rA, $rS, $rB", IntGeneral,
752 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
753 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
754 "srw $rA, $rS, $rB", IntGeneral,
755 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
756 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
757 "sraw $rA, $rS, $rB", IntShift,
758 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
761 let PPC970_Unit = 1 in { // FXU Operations.
762 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
763 "srawi $rA, $rS, $SH", IntShift,
764 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
765 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
766 "cntlzw $rA, $rS", IntGeneral,
767 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
768 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
769 "extsb $rA, $rS", IntGeneral,
770 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
771 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
772 "extsh $rA, $rS", IntGeneral,
773 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
775 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
776 "cmpw $crD, $rA, $rB", IntCompare>;
777 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
778 "cmplw $crD, $rA, $rB", IntCompare>;
780 let PPC970_Unit = 3 in { // FPU Operations.
781 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
782 // "fcmpo $crD, $fA, $fB", FPCompare>;
783 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
784 "fcmpu $crD, $fA, $fB", FPCompare>;
785 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
786 "fcmpu $crD, $fA, $fB", FPCompare>;
788 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
789 "fctiwz $frD, $frB", FPGeneral,
790 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
791 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
792 "frsp $frD, $frB", FPGeneral,
793 [(set F4RC:$frD, (fround F8RC:$frB))]>;
794 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
795 "fsqrt $frD, $frB", FPSqrt,
796 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
797 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
798 "fsqrts $frD, $frB", FPSqrt,
799 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
802 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
804 /// Note that these are defined as pseudo-ops on the PPC970 because they are
805 /// often coalesced away and we don't want the dispatch group builder to think
806 /// that they will fill slots (which could cause the load of a LSU reject to
807 /// sneak into a d-group with a store).
808 def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
809 "fmr $frD, $frB", FPGeneral,
810 []>, // (set F4RC:$frD, F4RC:$frB)
812 def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
813 "fmr $frD, $frB", FPGeneral,
814 []>, // (set F8RC:$frD, F8RC:$frB)
816 def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
817 "fmr $frD, $frB", FPGeneral,
818 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
821 let PPC970_Unit = 3 in { // FPU Operations.
822 // These are artificially split into two different forms, for 4/8 byte FP.
823 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
824 "fabs $frD, $frB", FPGeneral,
825 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
826 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
827 "fabs $frD, $frB", FPGeneral,
828 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
829 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
830 "fnabs $frD, $frB", FPGeneral,
831 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
832 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
833 "fnabs $frD, $frB", FPGeneral,
834 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
835 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
836 "fneg $frD, $frB", FPGeneral,
837 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
838 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
839 "fneg $frD, $frB", FPGeneral,
840 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
844 // XL-Form instructions. condition register logical ops.
846 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
847 "mcrf $BF, $BFA", BrMCR>,
848 PPC970_DGroup_First, PPC970_Unit_CRU;
850 def CREQV : XLForm_1<19, 289, (outs CRRC:$CRD), (ins CRRC:$CRA, CRRC:$CRB),
851 "creqv $CRD, $CRA, $CRB", BrCR,
854 def SETCR : XLForm_1_ext<19, 289, (outs CRRC:$dst), (ins),
855 "creqv $dst, $dst, $dst", BrCR,
858 // XFX-Form instructions. Instructions that deal with SPRs.
860 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
861 "mfctr $rT", SprMFSPR>,
862 PPC970_DGroup_First, PPC970_Unit_FXU;
863 let Pattern = [(PPCmtctr GPRC:$rS)] in {
864 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
865 "mtctr $rS", SprMTSPR>,
866 PPC970_DGroup_First, PPC970_Unit_FXU;
869 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
870 "mtlr $rS", SprMTSPR>,
871 PPC970_DGroup_First, PPC970_Unit_FXU;
872 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
873 "mflr $rT", SprMFSPR>,
874 PPC970_DGroup_First, PPC970_Unit_FXU;
876 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
877 // a GPR on the PPC970. As such, copies in and out have the same performance
878 // characteristics as an OR instruction.
879 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
880 "mtspr 256, $rS", IntGeneral>,
881 PPC970_DGroup_Single, PPC970_Unit_FXU;
882 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
883 "mfspr $rT, 256", IntGeneral>,
884 PPC970_DGroup_First, PPC970_Unit_FXU;
886 def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
887 "mtcrf $FXM, $rS", BrMCRX>,
888 PPC970_MicroCode, PPC970_Unit_CRU;
889 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
890 PPC970_MicroCode, PPC970_Unit_CRU;
891 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
892 "mfcr $rT, $FXM", SprMFCR>,
893 PPC970_DGroup_First, PPC970_Unit_CRU;
895 // Instructions to manipulate FPSCR. Only long double handling uses these.
896 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
898 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
900 [(set F8RC:$rT, (PPCmffs))]>,
901 PPC970_DGroup_Single, PPC970_Unit_FPU;
902 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
903 "mtfsb0 $FM", IntMTFSB0,
904 [(PPCmtfsb0 (i32 imm:$FM))]>,
905 PPC970_DGroup_Single, PPC970_Unit_FPU;
906 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
907 "mtfsb1 $FM", IntMTFSB0,
908 [(PPCmtfsb1 (i32 imm:$FM))]>,
909 PPC970_DGroup_Single, PPC970_Unit_FPU;
910 def FADDrtz: AForm_2<63, 21,
911 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
912 "fadd $FRT, $FRA, $FRB", FPGeneral,
913 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
914 PPC970_DGroup_Single, PPC970_Unit_FPU;
915 // MTFSF does not actually produce an FP result. We pretend it copies
916 // input reg B to the output. If we didn't do this it would look like the
917 // instruction had no outputs (because we aren't modelling the FPSCR) and
918 // it would be deleted.
919 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
920 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
921 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
922 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
923 F8RC:$rT, F8RC:$FRB))]>,
924 PPC970_DGroup_Single, PPC970_Unit_FPU;
926 let PPC970_Unit = 1 in { // FXU Operations.
928 // XO-Form instructions. Arithmetic instructions that can set overflow bit
930 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
931 "add $rT, $rA, $rB", IntGeneral,
932 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
933 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
934 "addc $rT, $rA, $rB", IntGeneral,
935 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
936 PPC970_DGroup_Cracked;
937 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
938 "adde $rT, $rA, $rB", IntGeneral,
939 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
940 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
941 "divw $rT, $rA, $rB", IntDivW,
942 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
943 PPC970_DGroup_First, PPC970_DGroup_Cracked;
944 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
945 "divwu $rT, $rA, $rB", IntDivW,
946 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
947 PPC970_DGroup_First, PPC970_DGroup_Cracked;
948 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
949 "mulhw $rT, $rA, $rB", IntMulHW,
950 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
951 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
952 "mulhwu $rT, $rA, $rB", IntMulHWU,
953 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
954 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
955 "mullw $rT, $rA, $rB", IntMulHW,
956 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
957 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
958 "subf $rT, $rA, $rB", IntGeneral,
959 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
960 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
961 "subfc $rT, $rA, $rB", IntGeneral,
962 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
963 PPC970_DGroup_Cracked;
964 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
965 "subfe $rT, $rA, $rB", IntGeneral,
966 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
967 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
968 "addme $rT, $rA", IntGeneral,
969 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
970 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
971 "addze $rT, $rA", IntGeneral,
972 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
973 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
974 "neg $rT, $rA", IntGeneral,
975 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
976 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
977 "subfme $rT, $rA", IntGeneral,
978 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
979 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
980 "subfze $rT, $rA", IntGeneral,
981 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
984 // A-Form instructions. Most of the instructions executed in the FPU are of
987 let PPC970_Unit = 3 in { // FPU Operations.
988 def FMADD : AForm_1<63, 29,
989 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
990 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
991 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
993 Requires<[FPContractions]>;
994 def FMADDS : AForm_1<59, 29,
995 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
996 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
997 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
999 Requires<[FPContractions]>;
1000 def FMSUB : AForm_1<63, 28,
1001 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1002 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1003 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1005 Requires<[FPContractions]>;
1006 def FMSUBS : AForm_1<59, 28,
1007 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1008 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1009 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1011 Requires<[FPContractions]>;
1012 def FNMADD : AForm_1<63, 31,
1013 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1014 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1015 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1017 Requires<[FPContractions]>;
1018 def FNMADDS : AForm_1<59, 31,
1019 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1020 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1021 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1023 Requires<[FPContractions]>;
1024 def FNMSUB : AForm_1<63, 30,
1025 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1026 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1027 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1029 Requires<[FPContractions]>;
1030 def FNMSUBS : AForm_1<59, 30,
1031 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1032 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1033 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
1035 Requires<[FPContractions]>;
1036 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1037 // having 4 of these, force the comparison to always be an 8-byte double (code
1038 // should use an FMRSD if the input comparison value really wants to be a float)
1039 // and 4/8 byte forms for the result and operand type..
1040 def FSELD : AForm_1<63, 23,
1041 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1042 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1043 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1044 def FSELS : AForm_1<63, 23,
1045 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1046 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1047 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1048 def FADD : AForm_2<63, 21,
1049 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1050 "fadd $FRT, $FRA, $FRB", FPGeneral,
1051 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1052 def FADDS : AForm_2<59, 21,
1053 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1054 "fadds $FRT, $FRA, $FRB", FPGeneral,
1055 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1056 def FDIV : AForm_2<63, 18,
1057 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1058 "fdiv $FRT, $FRA, $FRB", FPDivD,
1059 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1060 def FDIVS : AForm_2<59, 18,
1061 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1062 "fdivs $FRT, $FRA, $FRB", FPDivS,
1063 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1064 def FMUL : AForm_3<63, 25,
1065 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1066 "fmul $FRT, $FRA, $FRB", FPFused,
1067 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1068 def FMULS : AForm_3<59, 25,
1069 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1070 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1071 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1072 def FSUB : AForm_2<63, 20,
1073 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1074 "fsub $FRT, $FRA, $FRB", FPGeneral,
1075 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1076 def FSUBS : AForm_2<59, 20,
1077 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1078 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1079 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1082 let PPC970_Unit = 1 in { // FXU Operations.
1083 // M-Form instructions. rotate and mask instructions.
1085 let isCommutable = 1 in {
1086 // RLWIMI can be commuted if the rotate amount is zero.
1087 def RLWIMI : MForm_2<20,
1088 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1089 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1090 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1093 def RLWINM : MForm_2<21,
1094 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1095 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1097 def RLWINMo : MForm_2<21,
1098 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1099 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1100 []>, isDOT, PPC970_DGroup_Cracked;
1101 def RLWNM : MForm_2<23,
1102 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1103 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1108 //===----------------------------------------------------------------------===//
1109 // DWARF Pseudo Instructions
1112 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
1113 "${:comment} .loc $file, $line, $col",
1114 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
1117 //===----------------------------------------------------------------------===//
1118 // PowerPC Instruction Patterns
1121 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1122 def : Pat<(i32 imm:$imm),
1123 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1125 // Implement the 'not' operation with the NOR instruction.
1126 def NOT : Pat<(not GPRC:$in),
1127 (NOR GPRC:$in, GPRC:$in)>;
1129 // ADD an arbitrary immediate.
1130 def : Pat<(add GPRC:$in, imm:$imm),
1131 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1132 // OR an arbitrary immediate.
1133 def : Pat<(or GPRC:$in, imm:$imm),
1134 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1135 // XOR an arbitrary immediate.
1136 def : Pat<(xor GPRC:$in, imm:$imm),
1137 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1139 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1140 (SUBFIC GPRC:$in, imm:$imm)>;
1143 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1144 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1145 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1146 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1149 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1150 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1151 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1152 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1155 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1156 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1159 def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1160 (BL_Macho tglobaladdr:$dst)>;
1161 def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1162 (BL_Macho texternalsym:$dst)>;
1163 def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
1164 (BL_ELF tglobaladdr:$dst)>;
1165 def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
1166 (BL_ELF texternalsym:$dst)>;
1168 // Hi and Lo for Darwin Global Addresses.
1169 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1170 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1171 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1172 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1173 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1174 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1175 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1176 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1177 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1178 (ADDIS GPRC:$in, tconstpool:$g)>;
1179 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1180 (ADDIS GPRC:$in, tjumptable:$g)>;
1182 // Fused negative multiply subtract, alternate pattern
1183 def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1184 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1185 Requires<[FPContractions]>;
1186 def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1187 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1188 Requires<[FPContractions]>;
1190 // Standard shifts. These are represented separately from the real shifts above
1191 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1193 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1194 (SRAW GPRC:$rS, GPRC:$rB)>;
1195 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1196 (SRW GPRC:$rS, GPRC:$rB)>;
1197 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1198 (SLW GPRC:$rS, GPRC:$rB)>;
1200 def : Pat<(zextloadi1 iaddr:$src),
1202 def : Pat<(zextloadi1 xaddr:$src),
1204 def : Pat<(extloadi1 iaddr:$src),
1206 def : Pat<(extloadi1 xaddr:$src),
1208 def : Pat<(extloadi8 iaddr:$src),
1210 def : Pat<(extloadi8 xaddr:$src),
1212 def : Pat<(extloadi16 iaddr:$src),
1214 def : Pat<(extloadi16 xaddr:$src),
1216 def : Pat<(extloadf32 iaddr:$src),
1217 (FMRSD (LFS iaddr:$src))>;
1218 def : Pat<(extloadf32 xaddr:$src),
1219 (FMRSD (LFSX xaddr:$src))>;
1221 include "PPCInstrAltivec.td"
1222 include "PPCInstr64Bit.td"