1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
123 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
126 [SDNPHasChain, SDNPSideEffect,
127 SDNPInGlue, SDNPOutGlue]>;
128 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
129 [SDNPHasChain, SDNPSideEffect,
130 SDNPInGlue, SDNPOutGlue]>;
131 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
133 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
141 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
144 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
147 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
148 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
150 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
151 [SDNPHasChain, SDNPOptInGlue]>;
153 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
154 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
156 [SDNPHasChain, SDNPMayStore]>;
158 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
159 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
160 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
161 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
162 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
164 // Instructions to support atomic operations
165 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
166 [SDNPHasChain, SDNPMayLoad]>;
167 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
168 [SDNPHasChain, SDNPMayStore]>;
170 // Instructions to support dynamic alloca.
171 def SDTDynOp : SDTypeProfile<1, 2, []>;
172 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
174 //===----------------------------------------------------------------------===//
175 // PowerPC specific transformation functions and pattern fragments.
178 def SHL32 : SDNodeXForm<imm, [{
179 // Transformation function: 31 - imm
180 return getI32Imm(31 - N->getZExtValue());
183 def SRL32 : SDNodeXForm<imm, [{
184 // Transformation function: 32 - imm
185 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
188 def LO16 : SDNodeXForm<imm, [{
189 // Transformation function: get the low 16 bits.
190 return getI32Imm((unsigned short)N->getZExtValue());
193 def HI16 : SDNodeXForm<imm, [{
194 // Transformation function: shift the immediate value down into the low bits.
195 return getI32Imm((unsigned)N->getZExtValue() >> 16);
198 def HA16 : SDNodeXForm<imm, [{
199 // Transformation function: shift the immediate value down into the low bits.
200 signed int Val = N->getZExtValue();
201 return getI32Imm((Val - (signed short)Val) >> 16);
203 def MB : SDNodeXForm<imm, [{
204 // Transformation function: get the start bit of a mask
206 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
207 return getI32Imm(mb);
210 def ME : SDNodeXForm<imm, [{
211 // Transformation function: get the end bit of a mask
213 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
214 return getI32Imm(me);
216 def maskimm32 : PatLeaf<(imm), [{
217 // maskImm predicate - True if immediate is a run of ones.
219 if (N->getValueType(0) == MVT::i32)
220 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
225 def immSExt16 : PatLeaf<(imm), [{
226 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
227 // field. Used by instructions like 'addi'.
228 if (N->getValueType(0) == MVT::i32)
229 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
231 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
233 def immZExt16 : PatLeaf<(imm), [{
234 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
235 // field. Used by instructions like 'ori'.
236 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
239 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
240 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
241 // identical in 32-bit mode, but in 64-bit mode, they return true if the
242 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
244 def imm16ShiftedZExt : PatLeaf<(imm), [{
245 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
246 // immediate are set. Used by instructions like 'xoris'.
247 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
250 def imm16ShiftedSExt : PatLeaf<(imm), [{
251 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
252 // immediate are set. Used by instructions like 'addis'. Identical to
253 // imm16ShiftedZExt in 32-bit mode.
254 if (N->getZExtValue() & 0xFFFF) return false;
255 if (N->getValueType(0) == MVT::i32)
257 // For 64-bit, make sure it is sext right.
258 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
262 //===----------------------------------------------------------------------===//
263 // PowerPC Flag Definitions.
265 class isPPC64 { bit PPC64 = 1; }
267 list<Register> Defs = [CR0];
271 class RegConstraint<string C> {
272 string Constraints = C;
274 class NoEncode<string E> {
275 string DisableEncoding = E;
279 //===----------------------------------------------------------------------===//
280 // PowerPC Operand Definitions.
282 def s5imm : Operand<i32> {
283 let PrintMethod = "printS5ImmOperand";
285 def u5imm : Operand<i32> {
286 let PrintMethod = "printU5ImmOperand";
288 def u6imm : Operand<i32> {
289 let PrintMethod = "printU6ImmOperand";
291 def s16imm : Operand<i32> {
292 let PrintMethod = "printS16ImmOperand";
294 def u16imm : Operand<i32> {
295 let PrintMethod = "printU16ImmOperand";
297 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
298 let PrintMethod = "printS16X4ImmOperand";
300 def directbrtarget : Operand<OtherVT> {
301 let PrintMethod = "printBranchOperand";
302 let EncoderMethod = "getDirectBrEncoding";
304 def condbrtarget : Operand<OtherVT> {
305 let PrintMethod = "printBranchOperand";
306 let EncoderMethod = "getCondBrEncoding";
308 def calltarget : Operand<iPTR> {
309 let EncoderMethod = "getDirectBrEncoding";
311 def aaddr : Operand<iPTR> {
312 let PrintMethod = "printAbsAddrOperand";
314 def symbolHi: Operand<i32> {
315 let PrintMethod = "printSymbolHi";
316 let EncoderMethod = "getHA16Encoding";
318 def symbolLo: Operand<i32> {
319 let PrintMethod = "printSymbolLo";
320 let EncoderMethod = "getLO16Encoding";
322 def crbitm: Operand<i8> {
323 let PrintMethod = "printcrbitm";
324 let EncoderMethod = "get_crbitm_encoding";
327 def memri : Operand<iPTR> {
328 let PrintMethod = "printMemRegImm";
329 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
330 let EncoderMethod = "getMemRIEncoding";
332 def memrr : Operand<iPTR> {
333 let PrintMethod = "printMemRegReg";
334 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg);
336 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
337 let PrintMethod = "printMemRegImmShifted";
338 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
339 let EncoderMethod = "getMemRIXEncoding";
342 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
343 // that doesn't matter.
344 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
345 (ops (i32 20), (i32 zero_reg))> {
346 let PrintMethod = "printPredicateOperand";
349 // Define PowerPC specific addressing mode.
350 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
351 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
352 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
353 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
355 /// This is just the offset part of iaddr, used for preinc.
356 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
357 def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
359 //===----------------------------------------------------------------------===//
360 // PowerPC Instruction Predicate Definitions.
361 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
362 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
363 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
365 //===----------------------------------------------------------------------===//
366 // PowerPC Instruction Definitions.
368 // Pseudo-instructions:
370 let hasCtrlDep = 1 in {
371 let Defs = [R1], Uses = [R1] in {
372 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
373 [(callseq_start timm:$amt)]>;
374 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
375 [(callseq_end timm:$amt1, timm:$amt2)]>;
378 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
379 "UPDATE_VRSAVE $rD, $rS", []>;
382 let Defs = [R1], Uses = [R1] in
383 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
385 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
387 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
388 // instruction selection into a branch sequence.
389 let usesCustomInserter = 1, // Expanded after instruction selection.
390 PPC970_Single = 1 in {
391 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
392 i32imm:$BROPC), "#SELECT_CC_I4",
394 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
395 i32imm:$BROPC), "#SELECT_CC_I8",
397 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
398 i32imm:$BROPC), "#SELECT_CC_F4",
400 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
401 i32imm:$BROPC), "#SELECT_CC_F8",
403 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
404 i32imm:$BROPC), "#SELECT_CC_VRRC",
408 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
409 // scavenge a register for it.
411 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
414 // RESTORE_CR - Indicate that we're restoring the CR register (previously
415 // spilled), so we'll need to scavenge a register for it.
417 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
420 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
421 let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
422 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
423 "b${p:cc}lr ${p:reg}", BrB,
425 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
426 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
430 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
433 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
434 let isBarrier = 1 in {
435 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
440 // BCC represents an arbitrary conditional branch on a predicate.
441 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
442 // a two-value operand where a dag node expects two operands. :(
443 let isCodeGenOnly = 1 in
444 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
445 "b${cond:cc} ${cond:reg}, $dst"
446 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
448 let Defs = [CTR], Uses = [CTR] in {
449 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
450 "bdz $dst", BrB, []>;
451 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
452 "bdnz $dst", BrB, []>;
457 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
458 // Convenient aliases for call instructions
460 def BL_Darwin : IForm<18, 0, 1,
461 (outs), (ins calltarget:$func),
462 "bl $func", BrB, []>; // See Pat patterns below.
463 def BLA_Darwin : IForm<18, 1, 1,
464 (outs), (ins aaddr:$func),
465 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
467 let Uses = [CTR, RM] in {
468 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
471 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
476 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
477 // Convenient aliases for call instructions
479 def BL_SVR4 : IForm<18, 0, 1,
480 (outs), (ins calltarget:$func),
481 "bl $func", BrB, []>; // See Pat patterns below.
482 def BLA_SVR4 : IForm<18, 1, 1,
483 (outs), (ins aaddr:$func),
485 [(PPCcall_SVR4 (i32 imm:$func))]>;
487 let Uses = [CTR, RM] in {
488 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
491 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
496 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
497 def TCRETURNdi :Pseudo< (outs),
498 (ins calltarget:$dst, i32imm:$offset),
499 "#TC_RETURNd $dst $offset",
503 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
504 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
505 "#TC_RETURNa $func $offset",
506 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
508 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
509 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
510 "#TC_RETURNr $dst $offset",
514 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
515 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
516 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
517 Requires<[In32BitMode]>;
521 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
522 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
523 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
528 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
529 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
530 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
535 // DCB* instructions.
536 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
537 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
538 PPC970_DGroup_Single;
539 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
540 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
541 PPC970_DGroup_Single;
542 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
543 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
544 PPC970_DGroup_Single;
545 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
546 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
547 PPC970_DGroup_Single;
548 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
549 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
550 PPC970_DGroup_Single;
551 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
552 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
553 PPC970_DGroup_Single;
554 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
555 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
556 PPC970_DGroup_Single;
557 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
558 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
559 PPC970_DGroup_Single;
561 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
565 let usesCustomInserter = 1 in {
566 let Defs = [CR0] in {
567 def ATOMIC_LOAD_ADD_I8 : Pseudo<
568 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
569 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
570 def ATOMIC_LOAD_SUB_I8 : Pseudo<
571 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
572 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
573 def ATOMIC_LOAD_AND_I8 : Pseudo<
574 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
575 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
576 def ATOMIC_LOAD_OR_I8 : Pseudo<
577 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
578 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
579 def ATOMIC_LOAD_XOR_I8 : Pseudo<
580 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
581 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
582 def ATOMIC_LOAD_NAND_I8 : Pseudo<
583 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
584 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
585 def ATOMIC_LOAD_ADD_I16 : Pseudo<
586 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
587 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
588 def ATOMIC_LOAD_SUB_I16 : Pseudo<
589 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
590 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
591 def ATOMIC_LOAD_AND_I16 : Pseudo<
592 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
593 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
594 def ATOMIC_LOAD_OR_I16 : Pseudo<
595 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
596 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
597 def ATOMIC_LOAD_XOR_I16 : Pseudo<
598 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
599 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
600 def ATOMIC_LOAD_NAND_I16 : Pseudo<
601 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
602 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
603 def ATOMIC_LOAD_ADD_I32 : Pseudo<
604 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
605 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
606 def ATOMIC_LOAD_SUB_I32 : Pseudo<
607 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
608 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
609 def ATOMIC_LOAD_AND_I32 : Pseudo<
610 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
611 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
612 def ATOMIC_LOAD_OR_I32 : Pseudo<
613 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
614 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
615 def ATOMIC_LOAD_XOR_I32 : Pseudo<
616 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
617 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
618 def ATOMIC_LOAD_NAND_I32 : Pseudo<
619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
620 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
622 def ATOMIC_CMP_SWAP_I8 : Pseudo<
623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
625 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
626 def ATOMIC_CMP_SWAP_I16 : Pseudo<
627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
629 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
630 def ATOMIC_CMP_SWAP_I32 : Pseudo<
631 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
633 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
635 def ATOMIC_SWAP_I8 : Pseudo<
636 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
637 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
638 def ATOMIC_SWAP_I16 : Pseudo<
639 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
640 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
641 def ATOMIC_SWAP_I32 : Pseudo<
642 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
643 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
647 // Instructions to support atomic operations
648 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
649 "lwarx $rD, $src", LdStLWARX,
650 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
653 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
654 "stwcx. $rS, $dst", LdStSTWCX,
655 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
658 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
659 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
661 //===----------------------------------------------------------------------===//
662 // PPC32 Load Instructions.
665 // Unindexed (r+i) Loads.
666 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
667 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
668 "lbz $rD, $src", LdStLoad,
669 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
670 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
671 "lha $rD, $src", LdStLHA,
672 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
673 PPC970_DGroup_Cracked;
674 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
675 "lhz $rD, $src", LdStLoad,
676 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
677 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
678 "lwz $rD, $src", LdStLoad,
679 [(set GPRC:$rD, (load iaddr:$src))]>;
681 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
682 "lfs $rD, $src", LdStLFD,
683 [(set F4RC:$rD, (load iaddr:$src))]>;
684 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
685 "lfd $rD, $src", LdStLFD,
686 [(set F8RC:$rD, (load iaddr:$src))]>;
689 // Unindexed (r+i) Loads with Update (preinc).
691 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
692 "lbzu $rD, $addr", LdStLoadUpd,
693 []>, RegConstraint<"$addr.reg = $ea_result">,
694 NoEncode<"$ea_result">;
696 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
697 "lhau $rD, $addr", LdStLHAU,
698 []>, RegConstraint<"$addr.reg = $ea_result">,
699 NoEncode<"$ea_result">;
701 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
702 "lhzu $rD, $addr", LdStLoadUpd,
703 []>, RegConstraint<"$addr.reg = $ea_result">,
704 NoEncode<"$ea_result">;
706 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
707 "lwzu $rD, $addr", LdStLoadUpd,
708 []>, RegConstraint<"$addr.reg = $ea_result">,
709 NoEncode<"$ea_result">;
711 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
712 "lfsu $rD, $addr", LdStLFDU,
713 []>, RegConstraint<"$addr.reg = $ea_result">,
714 NoEncode<"$ea_result">;
716 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
717 "lfdu $rD, $addr", LdStLFDU,
718 []>, RegConstraint<"$addr.reg = $ea_result">,
719 NoEncode<"$ea_result">;
722 // Indexed (r+r) Loads with Update (preinc).
723 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
725 "lbzux $rD, $addr", LdStLoadUpd,
726 []>, RegConstraint<"$addr.offreg = $ea_result">,
727 NoEncode<"$ea_result">;
729 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
731 "lhaux $rD, $addr", LdStLHAU,
732 []>, RegConstraint<"$addr.offreg = $ea_result">,
733 NoEncode<"$ea_result">;
735 def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result),
737 "lhzux $rD, $addr", LdStLoadUpd,
738 []>, RegConstraint<"$addr.offreg = $ea_result">,
739 NoEncode<"$ea_result">;
741 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
743 "lwzux $rD, $addr", LdStLoadUpd,
744 []>, RegConstraint<"$addr.offreg = $ea_result">,
745 NoEncode<"$ea_result">;
747 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
749 "lfsux $rD, $addr", LdStLFDU,
750 []>, RegConstraint<"$addr.offreg = $ea_result">,
751 NoEncode<"$ea_result">;
753 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
755 "lfdux $rD, $addr", LdStLFDU,
756 []>, RegConstraint<"$addr.offreg = $ea_result">,
757 NoEncode<"$ea_result">;
761 // Indexed (r+r) Loads.
763 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
764 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
765 "lbzx $rD, $src", LdStLoad,
766 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
767 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
768 "lhax $rD, $src", LdStLHA,
769 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
770 PPC970_DGroup_Cracked;
771 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
772 "lhzx $rD, $src", LdStLoad,
773 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
774 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
775 "lwzx $rD, $src", LdStLoad,
776 [(set GPRC:$rD, (load xaddr:$src))]>;
779 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
780 "lhbrx $rD, $src", LdStLoad,
781 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
782 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
783 "lwbrx $rD, $src", LdStLoad,
784 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
786 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
787 "lfsx $frD, $src", LdStLFD,
788 [(set F4RC:$frD, (load xaddr:$src))]>;
789 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
790 "lfdx $frD, $src", LdStLFD,
791 [(set F8RC:$frD, (load xaddr:$src))]>;
794 //===----------------------------------------------------------------------===//
795 // PPC32 Store Instructions.
798 // Unindexed (r+i) Stores.
799 let PPC970_Unit = 2 in {
800 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
801 "stb $rS, $src", LdStStore,
802 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
803 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
804 "sth $rS, $src", LdStStore,
805 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
806 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
807 "stw $rS, $src", LdStStore,
808 [(store GPRC:$rS, iaddr:$src)]>;
809 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
810 "stfs $rS, $dst", LdStSTFD,
811 [(store F4RC:$rS, iaddr:$dst)]>;
812 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
813 "stfd $rS, $dst", LdStSTFD,
814 [(store F8RC:$rS, iaddr:$dst)]>;
817 // Unindexed (r+i) Stores with Update (preinc).
818 let PPC970_Unit = 2 in {
819 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
820 symbolLo:$ptroff, ptr_rc:$ptrreg),
821 "stbu $rS, $ptroff($ptrreg)", LdStStoreUpd,
822 [(set ptr_rc:$ea_res,
823 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
824 iaddroff:$ptroff))]>,
825 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
826 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
827 symbolLo:$ptroff, ptr_rc:$ptrreg),
828 "sthu $rS, $ptroff($ptrreg)", LdStStoreUpd,
829 [(set ptr_rc:$ea_res,
830 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
831 iaddroff:$ptroff))]>,
832 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
833 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
834 symbolLo:$ptroff, ptr_rc:$ptrreg),
835 "stwu $rS, $ptroff($ptrreg)", LdStStoreUpd,
836 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
837 iaddroff:$ptroff))]>,
838 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
839 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
840 symbolLo:$ptroff, ptr_rc:$ptrreg),
841 "stfsu $rS, $ptroff($ptrreg)", LdStSTFDU,
842 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
843 iaddroff:$ptroff))]>,
844 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
845 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
846 symbolLo:$ptroff, ptr_rc:$ptrreg),
847 "stfdu $rS, $ptroff($ptrreg)", LdStSTFDU,
848 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
849 iaddroff:$ptroff))]>,
850 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
854 // Indexed (r+r) Stores.
856 let PPC970_Unit = 2 in {
857 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
858 "stbx $rS, $dst", LdStStore,
859 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
860 PPC970_DGroup_Cracked;
861 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
862 "sthx $rS, $dst", LdStStore,
863 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
864 PPC970_DGroup_Cracked;
865 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
866 "stwx $rS, $dst", LdStStore,
867 [(store GPRC:$rS, xaddr:$dst)]>,
868 PPC970_DGroup_Cracked;
870 def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
871 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
872 "stbux $rS, $ptroff, $ptrreg", LdStStoreUpd,
873 [(set ptr_rc:$ea_res,
874 (pre_truncsti8 GPRC:$rS,
875 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
876 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
877 PPC970_DGroup_Cracked;
879 def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
880 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
881 "sthux $rS, $ptroff, $ptrreg", LdStStoreUpd,
882 [(set ptr_rc:$ea_res,
883 (pre_truncsti16 GPRC:$rS,
884 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
885 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
886 PPC970_DGroup_Cracked;
888 def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
889 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
890 "stwux $rS, $ptroff, $ptrreg", LdStStoreUpd,
891 [(set ptr_rc:$ea_res,
892 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
893 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
894 PPC970_DGroup_Cracked;
896 def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
897 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
898 "stfsux $rS, $ptroff, $ptrreg", LdStSTFDU,
899 [(set ptr_rc:$ea_res,
900 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
901 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
902 PPC970_DGroup_Cracked;
904 def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
905 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
906 "stfdux $rS, $ptroff, $ptrreg", LdStSTFDU,
907 [(set ptr_rc:$ea_res,
908 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
909 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
910 PPC970_DGroup_Cracked;
912 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
913 "sthbrx $rS, $dst", LdStStore,
914 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
915 PPC970_DGroup_Cracked;
916 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
917 "stwbrx $rS, $dst", LdStStore,
918 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
919 PPC970_DGroup_Cracked;
921 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
922 "stfiwx $frS, $dst", LdStSTFD,
923 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
925 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
926 "stfsx $frS, $dst", LdStSTFD,
927 [(store F4RC:$frS, xaddr:$dst)]>;
928 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
929 "stfdx $frS, $dst", LdStSTFD,
930 [(store F8RC:$frS, xaddr:$dst)]>;
933 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
937 //===----------------------------------------------------------------------===//
938 // PPC32 Arithmetic Instructions.
941 let PPC970_Unit = 1 in { // FXU Operations.
942 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
943 "addi $rD, $rA, $imm", IntSimple,
944 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
945 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
946 "addi $rD, $rA, $imm", IntSimple,
947 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
948 let Defs = [CARRY] in {
949 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
950 "addic $rD, $rA, $imm", IntGeneral,
951 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
952 PPC970_DGroup_Cracked;
953 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
954 "addic. $rD, $rA, $imm", IntGeneral,
957 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
958 "addis $rD, $rA, $imm", IntSimple,
959 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
960 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
961 "la $rD, $sym($rA)", IntGeneral,
962 [(set GPRC:$rD, (add GPRC:$rA,
963 (PPClo tglobaladdr:$sym, 0)))]>;
964 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
965 "mulli $rD, $rA, $imm", IntMulLI,
966 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
967 let Defs = [CARRY] in {
968 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
969 "subfic $rD, $rA, $imm", IntGeneral,
970 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
973 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
974 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
975 "li $rD, $imm", IntSimple,
976 [(set GPRC:$rD, immSExt16:$imm)]>;
977 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
978 "lis $rD, $imm", IntSimple,
979 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
983 let PPC970_Unit = 1 in { // FXU Operations.
984 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
985 "andi. $dst, $src1, $src2", IntGeneral,
986 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
988 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
989 "andis. $dst, $src1, $src2", IntGeneral,
990 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
992 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
993 "ori $dst, $src1, $src2", IntSimple,
994 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
995 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
996 "oris $dst, $src1, $src2", IntSimple,
997 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
998 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
999 "xori $dst, $src1, $src2", IntSimple,
1000 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
1001 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1002 "xoris $dst, $src1, $src2", IntSimple,
1003 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
1004 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1006 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1007 "cmpwi $crD, $rA, $imm", IntCompare>;
1008 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1009 "cmplwi $dst, $src1, $src2", IntCompare>;
1013 let PPC970_Unit = 1 in { // FXU Operations.
1014 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1015 "nand $rA, $rS, $rB", IntSimple,
1016 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
1017 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1018 "and $rA, $rS, $rB", IntSimple,
1019 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
1020 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1021 "andc $rA, $rS, $rB", IntSimple,
1022 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
1023 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1024 "or $rA, $rS, $rB", IntSimple,
1025 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
1026 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1027 "nor $rA, $rS, $rB", IntSimple,
1028 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
1029 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1030 "orc $rA, $rS, $rB", IntSimple,
1031 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
1032 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1033 "eqv $rA, $rS, $rB", IntSimple,
1034 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
1035 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1036 "xor $rA, $rS, $rB", IntSimple,
1037 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
1038 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1039 "slw $rA, $rS, $rB", IntGeneral,
1040 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
1041 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1042 "srw $rA, $rS, $rB", IntGeneral,
1043 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
1044 let Defs = [CARRY] in {
1045 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1046 "sraw $rA, $rS, $rB", IntShift,
1047 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
1051 let PPC970_Unit = 1 in { // FXU Operations.
1052 let Defs = [CARRY] in {
1053 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1054 "srawi $rA, $rS, $SH", IntShift,
1055 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
1057 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1058 "cntlzw $rA, $rS", IntGeneral,
1059 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
1060 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1061 "extsb $rA, $rS", IntSimple,
1062 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
1063 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1064 "extsh $rA, $rS", IntSimple,
1065 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
1067 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1068 "cmpw $crD, $rA, $rB", IntCompare>;
1069 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1070 "cmplw $crD, $rA, $rB", IntCompare>;
1072 let PPC970_Unit = 3 in { // FPU Operations.
1073 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1074 // "fcmpo $crD, $fA, $fB", FPCompare>;
1075 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1076 "fcmpu $crD, $fA, $fB", FPCompare>;
1077 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1078 "fcmpu $crD, $fA, $fB", FPCompare>;
1080 let Uses = [RM] in {
1081 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1082 "fctiwz $frD, $frB", FPGeneral,
1083 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1084 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1085 "frsp $frD, $frB", FPGeneral,
1086 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1087 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1088 "fsqrt $frD, $frB", FPSqrt,
1089 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1090 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1091 "fsqrts $frD, $frB", FPSqrt,
1092 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1096 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1097 /// often coalesced away and we don't want the dispatch group builder to think
1098 /// that they will fill slots (which could cause the load of a LSU reject to
1099 /// sneak into a d-group with a store).
1100 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1101 "fmr $frD, $frB", FPGeneral,
1102 []>, // (set F4RC:$frD, F4RC:$frB)
1105 let PPC970_Unit = 3 in { // FPU Operations.
1106 // These are artificially split into two different forms, for 4/8 byte FP.
1107 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1108 "fabs $frD, $frB", FPGeneral,
1109 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1110 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1111 "fabs $frD, $frB", FPGeneral,
1112 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1113 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1114 "fnabs $frD, $frB", FPGeneral,
1115 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1116 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1117 "fnabs $frD, $frB", FPGeneral,
1118 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1119 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1120 "fneg $frD, $frB", FPGeneral,
1121 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1122 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1123 "fneg $frD, $frB", FPGeneral,
1124 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1128 // XL-Form instructions. condition register logical ops.
1130 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1131 "mcrf $BF, $BFA", BrMCR>,
1132 PPC970_DGroup_First, PPC970_Unit_CRU;
1134 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1135 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1136 "creqv $CRD, $CRA, $CRB", BrCR,
1139 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1140 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1141 "cror $CRD, $CRA, $CRB", BrCR,
1144 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1145 "creqv $dst, $dst, $dst", BrCR,
1148 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1149 "crxor $dst, $dst, $dst", BrCR,
1152 let Defs = [CR1EQ], CRD = 6 in {
1153 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1154 "creqv 6, 6, 6", BrCR,
1157 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1158 "crxor 6, 6, 6", BrCR,
1162 // XFX-Form instructions. Instructions that deal with SPRs.
1164 let Uses = [CTR] in {
1165 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1166 "mfctr $rT", SprMFSPR>,
1167 PPC970_DGroup_First, PPC970_Unit_FXU;
1169 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1170 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1171 "mtctr $rS", SprMTSPR>,
1172 PPC970_DGroup_First, PPC970_Unit_FXU;
1175 let Defs = [LR] in {
1176 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1177 "mtlr $rS", SprMTSPR>,
1178 PPC970_DGroup_First, PPC970_Unit_FXU;
1180 let Uses = [LR] in {
1181 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1182 "mflr $rT", SprMFSPR>,
1183 PPC970_DGroup_First, PPC970_Unit_FXU;
1186 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1187 // a GPR on the PPC970. As such, copies in and out have the same performance
1188 // characteristics as an OR instruction.
1189 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1190 "mtspr 256, $rS", IntGeneral>,
1191 PPC970_DGroup_Single, PPC970_Unit_FXU;
1192 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1193 "mfspr $rT, 256", IntGeneral>,
1194 PPC970_DGroup_First, PPC970_Unit_FXU;
1196 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1197 "mtcrf $FXM, $rS", BrMCRX>,
1198 PPC970_MicroCode, PPC970_Unit_CRU;
1200 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1201 // declaring that here gives the local register allocator problems with this:
1203 // MFCR <kill of whatever preg got assigned to vreg>
1204 // while not declaring it breaks DeadMachineInstructionElimination.
1205 // As it turns out, in all cases where we currently use this,
1206 // we're only interested in one subregister of it. Represent this in the
1207 // instruction to keep the register allocator from becoming confused.
1209 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1210 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1211 "#MFCRpseud", SprMFCR>,
1212 PPC970_MicroCode, PPC970_Unit_CRU;
1214 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1215 "mfcr $rT", SprMFCR>,
1216 PPC970_MicroCode, PPC970_Unit_CRU;
1218 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1219 "mfocrf $rT, $FXM", SprMFCR>,
1220 PPC970_DGroup_First, PPC970_Unit_CRU;
1222 // Instructions to manipulate FPSCR. Only long double handling uses these.
1223 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1225 let Uses = [RM], Defs = [RM] in {
1226 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1227 "mtfsb0 $FM", IntMTFSB0,
1228 [(PPCmtfsb0 (i32 imm:$FM))]>,
1229 PPC970_DGroup_Single, PPC970_Unit_FPU;
1230 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1231 "mtfsb1 $FM", IntMTFSB0,
1232 [(PPCmtfsb1 (i32 imm:$FM))]>,
1233 PPC970_DGroup_Single, PPC970_Unit_FPU;
1234 // MTFSF does not actually produce an FP result. We pretend it copies
1235 // input reg B to the output. If we didn't do this it would look like the
1236 // instruction had no outputs (because we aren't modelling the FPSCR) and
1237 // it would be deleted.
1238 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1239 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1240 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1241 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1242 F8RC:$rT, F8RC:$FRB))]>,
1243 PPC970_DGroup_Single, PPC970_Unit_FPU;
1245 let Uses = [RM] in {
1246 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1247 "mffs $rT", IntMFFS,
1248 [(set F8RC:$rT, (PPCmffs))]>,
1249 PPC970_DGroup_Single, PPC970_Unit_FPU;
1250 def FADDrtz: AForm_2<63, 21,
1251 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1252 "fadd $FRT, $FRA, $FRB", FPAddSub,
1253 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1254 PPC970_DGroup_Single, PPC970_Unit_FPU;
1258 let PPC970_Unit = 1 in { // FXU Operations.
1260 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1262 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1263 "add $rT, $rA, $rB", IntSimple,
1264 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1265 let Defs = [CARRY] in {
1266 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1267 "addc $rT, $rA, $rB", IntGeneral,
1268 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1269 PPC970_DGroup_Cracked;
1271 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1272 "divw $rT, $rA, $rB", IntDivW,
1273 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1274 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1275 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1276 "divwu $rT, $rA, $rB", IntDivW,
1277 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1278 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1279 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1280 "mulhw $rT, $rA, $rB", IntMulHW,
1281 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1282 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1283 "mulhwu $rT, $rA, $rB", IntMulHWU,
1284 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1285 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1286 "mullw $rT, $rA, $rB", IntMulHW,
1287 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1288 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1289 "subf $rT, $rA, $rB", IntGeneral,
1290 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1291 let Defs = [CARRY] in {
1292 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1293 "subfc $rT, $rA, $rB", IntGeneral,
1294 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1295 PPC970_DGroup_Cracked;
1297 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1298 "neg $rT, $rA", IntSimple,
1299 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1300 let Uses = [CARRY], Defs = [CARRY] in {
1301 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1302 "adde $rT, $rA, $rB", IntGeneral,
1303 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1304 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1305 "addme $rT, $rA", IntGeneral,
1306 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1307 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1308 "addze $rT, $rA", IntGeneral,
1309 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1310 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1311 "subfe $rT, $rA, $rB", IntGeneral,
1312 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1313 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1314 "subfme $rT, $rA", IntGeneral,
1315 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1316 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1317 "subfze $rT, $rA", IntGeneral,
1318 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1322 // A-Form instructions. Most of the instructions executed in the FPU are of
1325 let PPC970_Unit = 3 in { // FPU Operations.
1326 let Uses = [RM] in {
1327 def FMADD : AForm_1<63, 29,
1328 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1329 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1331 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
1332 def FMADDS : AForm_1<59, 29,
1333 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1334 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1336 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
1337 def FMSUB : AForm_1<63, 28,
1338 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1339 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1341 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
1342 def FMSUBS : AForm_1<59, 28,
1343 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1344 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1346 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
1347 def FNMADD : AForm_1<63, 31,
1348 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1349 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1351 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
1352 def FNMADDS : AForm_1<59, 31,
1353 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1354 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1356 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
1357 def FNMSUB : AForm_1<63, 30,
1358 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1359 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1360 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
1361 (fneg F8RC:$FRB))))]>;
1362 def FNMSUBS : AForm_1<59, 30,
1363 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1364 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1365 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
1366 (fneg F4RC:$FRB))))]>;
1368 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1369 // having 4 of these, force the comparison to always be an 8-byte double (code
1370 // should use an FMRSD if the input comparison value really wants to be a float)
1371 // and 4/8 byte forms for the result and operand type..
1372 def FSELD : AForm_1<63, 23,
1373 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1374 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1375 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1376 def FSELS : AForm_1<63, 23,
1377 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1378 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1379 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1380 let Uses = [RM] in {
1381 def FADD : AForm_2<63, 21,
1382 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1383 "fadd $FRT, $FRA, $FRB", FPAddSub,
1384 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1385 def FADDS : AForm_2<59, 21,
1386 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1387 "fadds $FRT, $FRA, $FRB", FPGeneral,
1388 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1389 def FDIV : AForm_2<63, 18,
1390 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1391 "fdiv $FRT, $FRA, $FRB", FPDivD,
1392 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1393 def FDIVS : AForm_2<59, 18,
1394 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1395 "fdivs $FRT, $FRA, $FRB", FPDivS,
1396 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1397 def FMUL : AForm_3<63, 25,
1398 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1399 "fmul $FRT, $FRA, $FRB", FPFused,
1400 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1401 def FMULS : AForm_3<59, 25,
1402 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1403 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1404 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1405 def FSUB : AForm_2<63, 20,
1406 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1407 "fsub $FRT, $FRA, $FRB", FPAddSub,
1408 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1409 def FSUBS : AForm_2<59, 20,
1410 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1411 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1412 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1416 let PPC970_Unit = 1 in { // FXU Operations.
1417 def ISEL : AForm_1<31, 15,
1418 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
1419 "isel $rT, $rA, $rB, $cond", IntGeneral,
1423 let PPC970_Unit = 1 in { // FXU Operations.
1424 // M-Form instructions. rotate and mask instructions.
1426 let isCommutable = 1 in {
1427 // RLWIMI can be commuted if the rotate amount is zero.
1428 def RLWIMI : MForm_2<20,
1429 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1430 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1431 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1434 def RLWINM : MForm_2<21,
1435 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1436 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1438 def RLWINMo : MForm_2<21,
1439 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1440 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1441 []>, isDOT, PPC970_DGroup_Cracked;
1442 def RLWNM : MForm_2<23,
1443 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1444 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1449 //===----------------------------------------------------------------------===//
1450 // PowerPC Instruction Patterns
1453 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1454 def : Pat<(i32 imm:$imm),
1455 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1457 // Implement the 'not' operation with the NOR instruction.
1458 def NOT : Pat<(not GPRC:$in),
1459 (NOR GPRC:$in, GPRC:$in)>;
1461 // ADD an arbitrary immediate.
1462 def : Pat<(add GPRC:$in, imm:$imm),
1463 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1464 // OR an arbitrary immediate.
1465 def : Pat<(or GPRC:$in, imm:$imm),
1466 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1467 // XOR an arbitrary immediate.
1468 def : Pat<(xor GPRC:$in, imm:$imm),
1469 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1471 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1472 (SUBFIC GPRC:$in, imm:$imm)>;
1475 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1476 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1477 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1478 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1481 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1482 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1483 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1484 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1487 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1488 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1491 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1492 (BL_Darwin tglobaladdr:$dst)>;
1493 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1494 (BL_Darwin texternalsym:$dst)>;
1495 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1496 (BL_SVR4 tglobaladdr:$dst)>;
1497 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1498 (BL_SVR4 texternalsym:$dst)>;
1501 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1502 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1504 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1505 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1507 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1508 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1512 // Hi and Lo for Darwin Global Addresses.
1513 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1514 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1515 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1516 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1517 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1518 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1519 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1520 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1521 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1522 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1523 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1524 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1525 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1526 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1527 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1528 (ADDIS GPRC:$in, tconstpool:$g)>;
1529 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1530 (ADDIS GPRC:$in, tjumptable:$g)>;
1531 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1532 (ADDIS GPRC:$in, tblockaddress:$g)>;
1534 // Standard shifts. These are represented separately from the real shifts above
1535 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1537 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1538 (SRAW GPRC:$rS, GPRC:$rB)>;
1539 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1540 (SRW GPRC:$rS, GPRC:$rB)>;
1541 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1542 (SLW GPRC:$rS, GPRC:$rB)>;
1544 def : Pat<(zextloadi1 iaddr:$src),
1546 def : Pat<(zextloadi1 xaddr:$src),
1548 def : Pat<(extloadi1 iaddr:$src),
1550 def : Pat<(extloadi1 xaddr:$src),
1552 def : Pat<(extloadi8 iaddr:$src),
1554 def : Pat<(extloadi8 xaddr:$src),
1556 def : Pat<(extloadi16 iaddr:$src),
1558 def : Pat<(extloadi16 xaddr:$src),
1560 def : Pat<(f64 (extloadf32 iaddr:$src)),
1561 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1562 def : Pat<(f64 (extloadf32 xaddr:$src)),
1563 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1565 def : Pat<(f64 (fextend F4RC:$src)),
1566 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1569 def : Pat<(membarrier (i32 imm /*ll*/),
1573 (i32 imm /*device*/)),
1576 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1578 include "PPCInstrAltivec.td"
1579 include "PPCInstr64Bit.td"