1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x
24 SDTCisVT<0, f64>, SDTCisPtrTy<1>
27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
30 def SDT_PPCvperm : SDTypeProfile<1, 3, [
31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
42 def SDT_PPClbrx : SDTypeProfile<1, 2, [
43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
49 def SDT_PPClarx : SDTypeProfile<1, 1, [
50 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCstcx : SDTypeProfile<0, 2, [
53 SDTCisInt<0>, SDTCisPtrTy<1>
56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
57 SDTCisPtrTy<0>, SDTCisVT<1, i32>
61 //===----------------------------------------------------------------------===//
62 // PowerPC specific DAG Nodes.
65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>;
66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>;
68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>;
69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>;
70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>;
71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>;
72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>;
75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>;
76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
77 [SDNPHasChain, SDNPMayStore]>;
78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,
79 [SDNPHasChain, SDNPMayLoad]>;
80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,
81 [SDNPHasChain, SDNPMayLoad]>;
83 // Extract FPSCR (not modeled at the DAG level).
84 def PPCmffs : SDNode<"PPCISD::MFFS",
85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>;
87 // Perform FADD in round-to-zero mode.
88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>;
91 def PPCfsel : SDNode<"PPCISD::FSEL",
92 // Type constraint for fsel.
93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>;
109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>;
110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>;
111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>;
112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp,
114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
119 // amounts. These nodes are generated by the multi-precision shift code.
120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
124 // These are target-independent nodes, but have target-specific formats.
125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
126 [SDNPHasChain, SDNPOutGlue]>;
127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall,
135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
140 [SDNPHasChain, SDNPSideEffect,
141 SDNPInGlue, SDNPOutGlue]>;
142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
143 [SDNPHasChain, SDNPSideEffect,
144 SDNPInGlue, SDNPOutGlue]>;
145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone,
148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP",
158 SDTypeProfile<1, 1, [SDTCisInt<0>,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
166 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
168 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
169 [SDNPHasChain, SDNPOptInGlue]>;
171 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
172 [SDNPHasChain, SDNPMayLoad]>;
173 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
174 [SDNPHasChain, SDNPMayStore]>;
176 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
177 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone,
178 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
179 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
182 // Instructions to support atomic operations
183 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
184 [SDNPHasChain, SDNPMayLoad]>;
185 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
186 [SDNPHasChain, SDNPMayStore]>;
188 // Instructions to support medium and large code model
189 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>;
190 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>;
191 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>;
194 // Instructions to support dynamic alloca.
195 def SDTDynOp : SDTypeProfile<1, 2, []>;
196 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
198 //===----------------------------------------------------------------------===//
199 // PowerPC specific transformation functions and pattern fragments.
202 def SHL32 : SDNodeXForm<imm, [{
203 // Transformation function: 31 - imm
204 return getI32Imm(31 - N->getZExtValue());
207 def SRL32 : SDNodeXForm<imm, [{
208 // Transformation function: 32 - imm
209 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
212 def LO16 : SDNodeXForm<imm, [{
213 // Transformation function: get the low 16 bits.
214 return getI32Imm((unsigned short)N->getZExtValue());
217 def HI16 : SDNodeXForm<imm, [{
218 // Transformation function: shift the immediate value down into the low bits.
219 return getI32Imm((unsigned)N->getZExtValue() >> 16);
222 def HA16 : SDNodeXForm<imm, [{
223 // Transformation function: shift the immediate value down into the low bits.
224 signed int Val = N->getZExtValue();
225 return getI32Imm((Val - (signed short)Val) >> 16);
227 def MB : SDNodeXForm<imm, [{
228 // Transformation function: get the start bit of a mask
230 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
231 return getI32Imm(mb);
234 def ME : SDNodeXForm<imm, [{
235 // Transformation function: get the end bit of a mask
237 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
238 return getI32Imm(me);
240 def maskimm32 : PatLeaf<(imm), [{
241 // maskImm predicate - True if immediate is a run of ones.
243 if (N->getValueType(0) == MVT::i32)
244 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
249 def immSExt16 : PatLeaf<(imm), [{
250 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
251 // field. Used by instructions like 'addi'.
252 if (N->getValueType(0) == MVT::i32)
253 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
255 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
257 def immZExt16 : PatLeaf<(imm), [{
258 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
259 // field. Used by instructions like 'ori'.
260 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
263 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
264 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
265 // identical in 32-bit mode, but in 64-bit mode, they return true if the
266 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
268 def imm16ShiftedZExt : PatLeaf<(imm), [{
269 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
270 // immediate are set. Used by instructions like 'xoris'.
271 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
274 def imm16ShiftedSExt : PatLeaf<(imm), [{
275 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
276 // immediate are set. Used by instructions like 'addis'. Identical to
277 // imm16ShiftedZExt in 32-bit mode.
278 if (N->getZExtValue() & 0xFFFF) return false;
279 if (N->getValueType(0) == MVT::i32)
281 // For 64-bit, make sure it is sext right.
282 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
285 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require
286 // restricted memrix (offset/4) constants are alignment sensitive. If these
287 // offsets are hidden behind TOC entries than the values of the lower-order
288 // bits cannot be checked directly. As a result, we need to also incorporate
289 // an alignment check into the relevant patterns.
291 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
292 return cast<LoadSDNode>(N)->getAlignment() >= 4;
294 def aligned4store : PatFrag<(ops node:$val, node:$ptr),
295 (store node:$val, node:$ptr), [{
296 return cast<StoreSDNode>(N)->getAlignment() >= 4;
298 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
299 return cast<LoadSDNode>(N)->getAlignment() >= 4;
301 def aligned4pre_store : PatFrag<
302 (ops node:$val, node:$base, node:$offset),
303 (pre_store node:$val, node:$base, node:$offset), [{
304 return cast<StoreSDNode>(N)->getAlignment() >= 4;
307 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
308 return cast<LoadSDNode>(N)->getAlignment() < 4;
310 def unaligned4store : PatFrag<(ops node:$val, node:$ptr),
311 (store node:$val, node:$ptr), [{
312 return cast<StoreSDNode>(N)->getAlignment() < 4;
314 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{
315 return cast<LoadSDNode>(N)->getAlignment() < 4;
318 //===----------------------------------------------------------------------===//
319 // PowerPC Flag Definitions.
321 class isPPC64 { bit PPC64 = 1; }
323 list<Register> Defs = [CR0];
327 list<Register> Defs = [CR1];
331 class RegConstraint<string C> {
332 string Constraints = C;
334 class NoEncode<string E> {
335 string DisableEncoding = E;
339 //===----------------------------------------------------------------------===//
340 // PowerPC Operand Definitions.
342 def s5imm : Operand<i32> {
343 let PrintMethod = "printS5ImmOperand";
345 def u5imm : Operand<i32> {
346 let PrintMethod = "printU5ImmOperand";
348 def u6imm : Operand<i32> {
349 let PrintMethod = "printU6ImmOperand";
351 def s16imm : Operand<i32> {
352 let PrintMethod = "printS16ImmOperand";
354 def u16imm : Operand<i32> {
355 let PrintMethod = "printU16ImmOperand";
357 def directbrtarget : Operand<OtherVT> {
358 let PrintMethod = "printBranchOperand";
359 let EncoderMethod = "getDirectBrEncoding";
361 def condbrtarget : Operand<OtherVT> {
362 let PrintMethod = "printBranchOperand";
363 let EncoderMethod = "getCondBrEncoding";
365 def calltarget : Operand<iPTR> {
366 let EncoderMethod = "getDirectBrEncoding";
368 def aaddr : Operand<iPTR> {
369 let PrintMethod = "printAbsAddrOperand";
371 def symbolHi: Operand<i32> {
372 let PrintMethod = "printSymbolHi";
373 let EncoderMethod = "getHA16Encoding";
375 def symbolLo: Operand<i32> {
376 let PrintMethod = "printSymbolLo";
377 let EncoderMethod = "getLO16Encoding";
379 def crbitm: Operand<i8> {
380 let PrintMethod = "printcrbitm";
381 let EncoderMethod = "get_crbitm_encoding";
384 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
385 def ptr_rc_nor0 : PointerLikeRegClass<1>;
387 def dispRI : Operand<iPTR>;
388 def dispRIX : Operand<iPTR>;
390 def memri : Operand<iPTR> {
391 let PrintMethod = "printMemRegImm";
392 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
393 let EncoderMethod = "getMemRIEncoding";
395 def memrr : Operand<iPTR> {
396 let PrintMethod = "printMemRegReg";
397 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc:$offreg);
399 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
400 let PrintMethod = "printMemRegImmShifted";
401 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
402 let EncoderMethod = "getMemRIXEncoding";
405 // A single-register address. This is used with the SjLj
406 // pseudo-instructions.
407 def memr : Operand<iPTR> {
408 let MIOperandInfo = (ops ptr_rc:$ptrreg);
411 // PowerPC Predicate operand.
412 def pred : Operand<OtherVT> {
413 let PrintMethod = "printPredicateOperand";
414 let MIOperandInfo = (ops i32imm:$bibo, CRRC:$reg);
417 // Define PowerPC specific addressing mode.
418 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
419 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
420 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
421 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
423 // The address in a single register. This is used with the SjLj
424 // pseudo-instructions.
425 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
427 /// This is just the offset part of iaddr, used for preinc.
428 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
430 //===----------------------------------------------------------------------===//
431 // PowerPC Instruction Predicate Definitions.
432 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
433 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
434 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
436 //===----------------------------------------------------------------------===//
437 // PowerPC Multiclass Definitions.
439 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
440 string asmbase, string asmstr, InstrItinClass itin,
442 let BaseName = asmbase in {
443 def NAME : XForm_6<opcode, xo, OOL, IOL,
444 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
445 pattern>, RecFormRel;
446 def o : XForm_6<opcode, xo, OOL, IOL,
447 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
448 []>, isDOT, RecFormRel;
452 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
453 string asmbase, string asmstr, InstrItinClass itin,
455 let BaseName = asmbase in {
456 def NAME : XForm_10<opcode, xo, OOL, IOL,
457 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
458 pattern>, RecFormRel;
459 def o : XForm_10<opcode, xo, OOL, IOL,
460 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
461 []>, isDOT, RecFormRel;
465 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
466 string asmbase, string asmstr, InstrItinClass itin,
468 let BaseName = asmbase in {
469 def NAME : XForm_11<opcode, xo, OOL, IOL,
470 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
471 pattern>, RecFormRel;
472 def o : XForm_11<opcode, xo, OOL, IOL,
473 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
474 []>, isDOT, RecFormRel;
478 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
479 string asmbase, string asmstr, InstrItinClass itin,
481 let BaseName = asmbase in {
482 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
483 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
484 pattern>, RecFormRel;
485 def o : XOForm_1<opcode, xo, oe, OOL, IOL,
486 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
487 []>, isDOT, RecFormRel;
491 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
492 string asmbase, string asmstr, InstrItinClass itin,
494 let BaseName = asmbase in {
495 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL,
496 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
497 pattern>, RecFormRel;
498 def o : XOForm_3<opcode, xo, oe, OOL, IOL,
499 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
500 []>, isDOT, RecFormRel;
504 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL,
505 string asmbase, string asmstr, InstrItinClass itin,
507 let BaseName = asmbase in {
508 def NAME : MForm_2<opcode, OOL, IOL,
509 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
510 pattern>, RecFormRel;
511 def o : MForm_2<opcode, OOL, IOL,
512 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
513 []>, isDOT, RecFormRel;
517 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
518 string asmbase, string asmstr, InstrItinClass itin,
520 let BaseName = asmbase in {
521 def NAME : MDForm_1<opcode, xo, OOL, IOL,
522 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
523 pattern>, RecFormRel;
524 def o : MDForm_1<opcode, xo, OOL, IOL,
525 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
526 []>, isDOT, RecFormRel;
530 multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
531 string asmbase, string asmstr, InstrItinClass itin,
533 let BaseName = asmbase in {
534 def NAME : XSForm_1<opcode, xo, OOL, IOL,
535 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
536 pattern>, RecFormRel;
537 def o : XSForm_1<opcode, xo, OOL, IOL,
538 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
539 []>, isDOT, RecFormRel;
543 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
544 string asmbase, string asmstr, InstrItinClass itin,
546 let BaseName = asmbase in {
547 def NAME : XForm_26<opcode, xo, OOL, IOL,
548 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
549 pattern>, RecFormRel;
550 def o : XForm_26<opcode, xo, OOL, IOL,
551 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
552 []>, isDOT1, RecFormRel;
556 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
557 string asmbase, string asmstr, InstrItinClass itin,
559 let BaseName = asmbase in {
560 def NAME : AForm_1<opcode, xo, OOL, IOL,
561 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
562 pattern>, RecFormRel;
563 def o : AForm_1<opcode, xo, OOL, IOL,
564 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
565 []>, isDOT1, RecFormRel;
569 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
570 string asmbase, string asmstr, InstrItinClass itin,
572 let BaseName = asmbase in {
573 def NAME : AForm_2<opcode, xo, OOL, IOL,
574 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
575 pattern>, RecFormRel;
576 def o : AForm_2<opcode, xo, OOL, IOL,
577 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
578 []>, isDOT1, RecFormRel;
582 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
583 string asmbase, string asmstr, InstrItinClass itin,
585 let BaseName = asmbase in {
586 def NAME : AForm_3<opcode, xo, OOL, IOL,
587 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
588 pattern>, RecFormRel;
589 def o : AForm_3<opcode, xo, OOL, IOL,
590 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
591 []>, isDOT1, RecFormRel;
595 //===----------------------------------------------------------------------===//
596 // PowerPC Instruction Definitions.
598 // Pseudo-instructions:
600 let hasCtrlDep = 1 in {
601 let Defs = [R1], Uses = [R1] in {
602 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
603 [(callseq_start timm:$amt)]>;
604 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
605 [(callseq_end timm:$amt1, timm:$amt2)]>;
608 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
609 "UPDATE_VRSAVE $rD, $rS", []>;
612 let Defs = [R1], Uses = [R1] in
613 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
615 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
617 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
618 // instruction selection into a branch sequence.
619 let usesCustomInserter = 1, // Expanded after instruction selection.
620 PPC970_Single = 1 in {
621 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes
622 // because either operand might become the first operand in an isel, and
623 // that operand cannot be r0.
624 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond,
625 GPRC_NOR0:$T, GPRC_NOR0:$F,
626 i32imm:$BROPC), "#SELECT_CC_I4",
628 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond,
629 G8RC_NOX0:$T, G8RC_NOX0:$F,
630 i32imm:$BROPC), "#SELECT_CC_I8",
632 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
633 i32imm:$BROPC), "#SELECT_CC_F4",
635 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
636 i32imm:$BROPC), "#SELECT_CC_F8",
638 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
639 i32imm:$BROPC), "#SELECT_CC_VRRC",
643 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
644 // scavenge a register for it.
646 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
649 // RESTORE_CR - Indicate that we're restoring the CR register (previously
650 // spilled), so we'll need to scavenge a register for it.
652 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
655 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
656 let isReturn = 1, Uses = [LR, RM] in
657 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB,
659 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in {
660 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
662 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
663 "b${cond:cc}ctr ${cond:reg}", BrB, []>;
668 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
671 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
672 let isBarrier = 1 in {
673 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
678 // BCC represents an arbitrary conditional branch on a predicate.
679 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
680 // a two-value operand where a dag node expects two operands. :(
681 let isCodeGenOnly = 1 in {
682 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
683 "b${cond:cc} ${cond:reg}, $dst"
684 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
685 let isReturn = 1, Uses = [LR, RM] in
686 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
687 "b${cond:cc}lr ${cond:reg}", BrB, []>;
689 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
690 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
692 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
697 let Defs = [CTR], Uses = [CTR] in {
698 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
700 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
705 // The unconditional BCL used by the SjLj setjmp code.
706 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in {
707 let Defs = [LR], Uses = [RM] in {
708 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst),
713 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
714 // Convenient aliases for call instructions
716 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func),
717 "bl $func", BrB, []>; // See Pat patterns below.
718 def BLA : IForm<18, 1, 1, (outs), (ins aaddr:$func),
719 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
721 let Uses = [CTR, RM] in {
722 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
723 "bctrl", BrB, [(PPCbctrl)]>,
724 Requires<[In32BitMode]>;
725 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
726 "b${cond:cc}ctrl ${cond:reg}", BrB, []>;
730 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
731 def TCRETURNdi :Pseudo< (outs),
732 (ins calltarget:$dst, i32imm:$offset),
733 "#TC_RETURNd $dst $offset",
737 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
738 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
739 "#TC_RETURNa $func $offset",
740 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
742 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
743 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
744 "#TC_RETURNr $dst $offset",
748 let isCodeGenOnly = 1 in {
750 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
751 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
752 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
753 Requires<[In32BitMode]>;
757 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
758 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
759 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
765 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
766 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
767 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
771 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
772 def EH_SjLj_SetJmp32 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
774 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
775 Requires<[In32BitMode]>;
776 let isTerminator = 1 in
777 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
778 "#EH_SJLJ_LONGJMP32",
779 [(PPCeh_sjlj_longjmp addr:$buf)]>,
780 Requires<[In32BitMode]>;
783 let isBranch = 1, isTerminator = 1 in {
784 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
785 "#EH_SjLj_Setup\t$dst", []>;
788 // DCB* instructions.
789 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
790 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
791 PPC970_DGroup_Single;
792 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
793 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
794 PPC970_DGroup_Single;
795 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
796 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
797 PPC970_DGroup_Single;
798 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
799 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
800 PPC970_DGroup_Single;
801 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
802 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
803 PPC970_DGroup_Single;
804 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
805 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
806 PPC970_DGroup_Single;
807 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
808 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
809 PPC970_DGroup_Single;
810 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
811 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
812 PPC970_DGroup_Single;
814 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
818 let usesCustomInserter = 1 in {
819 let Defs = [CR0] in {
820 def ATOMIC_LOAD_ADD_I8 : Pseudo<
821 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
822 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>;
823 def ATOMIC_LOAD_SUB_I8 : Pseudo<
824 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
825 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>;
826 def ATOMIC_LOAD_AND_I8 : Pseudo<
827 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
828 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>;
829 def ATOMIC_LOAD_OR_I8 : Pseudo<
830 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
831 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>;
832 def ATOMIC_LOAD_XOR_I8 : Pseudo<
833 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
834 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>;
835 def ATOMIC_LOAD_NAND_I8 : Pseudo<
836 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
837 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>;
838 def ATOMIC_LOAD_ADD_I16 : Pseudo<
839 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
840 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>;
841 def ATOMIC_LOAD_SUB_I16 : Pseudo<
842 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
843 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>;
844 def ATOMIC_LOAD_AND_I16 : Pseudo<
845 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
846 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>;
847 def ATOMIC_LOAD_OR_I16 : Pseudo<
848 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
849 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>;
850 def ATOMIC_LOAD_XOR_I16 : Pseudo<
851 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
852 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>;
853 def ATOMIC_LOAD_NAND_I16 : Pseudo<
854 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
855 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>;
856 def ATOMIC_LOAD_ADD_I32 : Pseudo<
857 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
858 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>;
859 def ATOMIC_LOAD_SUB_I32 : Pseudo<
860 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
861 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>;
862 def ATOMIC_LOAD_AND_I32 : Pseudo<
863 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
864 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>;
865 def ATOMIC_LOAD_OR_I32 : Pseudo<
866 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
867 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>;
868 def ATOMIC_LOAD_XOR_I32 : Pseudo<
869 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
870 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>;
871 def ATOMIC_LOAD_NAND_I32 : Pseudo<
872 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
873 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>;
875 def ATOMIC_CMP_SWAP_I8 : Pseudo<
876 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
877 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>;
878 def ATOMIC_CMP_SWAP_I16 : Pseudo<
879 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
880 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>;
881 def ATOMIC_CMP_SWAP_I32 : Pseudo<
882 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
883 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>;
885 def ATOMIC_SWAP_I8 : Pseudo<
886 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
887 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>;
888 def ATOMIC_SWAP_I16 : Pseudo<
889 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
890 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>;
891 def ATOMIC_SWAP_I32 : Pseudo<
892 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
893 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>;
897 // Instructions to support atomic operations
898 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
899 "lwarx $rD, $src", LdStLWARX,
900 [(set i32:$rD, (PPClarx xoaddr:$src))]>;
903 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
904 "stwcx. $rS, $dst", LdStSTWCX,
905 [(PPCstcx i32:$rS, xoaddr:$dst)]>,
908 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
909 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
911 //===----------------------------------------------------------------------===//
912 // PPC32 Load Instructions.
915 // Unindexed (r+i) Loads.
916 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
917 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
918 "lbz $rD, $src", LdStLoad,
919 [(set i32:$rD, (zextloadi8 iaddr:$src))]>;
920 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
921 "lha $rD, $src", LdStLHA,
922 [(set i32:$rD, (sextloadi16 iaddr:$src))]>,
923 PPC970_DGroup_Cracked;
924 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
925 "lhz $rD, $src", LdStLoad,
926 [(set i32:$rD, (zextloadi16 iaddr:$src))]>;
927 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
928 "lwz $rD, $src", LdStLoad,
929 [(set i32:$rD, (load iaddr:$src))]>;
931 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
932 "lfs $rD, $src", LdStLFD,
933 [(set f32:$rD, (load iaddr:$src))]>;
934 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
935 "lfd $rD, $src", LdStLFD,
936 [(set f64:$rD, (load iaddr:$src))]>;
939 // Unindexed (r+i) Loads with Update (preinc).
940 let mayLoad = 1, neverHasSideEffects = 1 in {
941 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
942 "lbzu $rD, $addr", LdStLoadUpd,
943 []>, RegConstraint<"$addr.reg = $ea_result">,
944 NoEncode<"$ea_result">;
946 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
947 "lhau $rD, $addr", LdStLHAU,
948 []>, RegConstraint<"$addr.reg = $ea_result">,
949 NoEncode<"$ea_result">;
951 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
952 "lhzu $rD, $addr", LdStLoadUpd,
953 []>, RegConstraint<"$addr.reg = $ea_result">,
954 NoEncode<"$ea_result">;
956 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
957 "lwzu $rD, $addr", LdStLoadUpd,
958 []>, RegConstraint<"$addr.reg = $ea_result">,
959 NoEncode<"$ea_result">;
961 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
962 "lfsu $rD, $addr", LdStLFDU,
963 []>, RegConstraint<"$addr.reg = $ea_result">,
964 NoEncode<"$ea_result">;
966 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
967 "lfdu $rD, $addr", LdStLFDU,
968 []>, RegConstraint<"$addr.reg = $ea_result">,
969 NoEncode<"$ea_result">;
972 // Indexed (r+r) Loads with Update (preinc).
973 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
975 "lbzux $rD, $addr", LdStLoadUpd,
976 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
977 NoEncode<"$ea_result">;
979 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
981 "lhaux $rD, $addr", LdStLHAU,
982 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
983 NoEncode<"$ea_result">;
985 def LHZUX : XForm_1<31, 311, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
987 "lhzux $rD, $addr", LdStLoadUpd,
988 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
989 NoEncode<"$ea_result">;
991 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc_nor0:$ea_result),
993 "lwzux $rD, $addr", LdStLoadUpd,
994 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
995 NoEncode<"$ea_result">;
997 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc_nor0:$ea_result),
999 "lfsux $rD, $addr", LdStLFDU,
1000 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1001 NoEncode<"$ea_result">;
1003 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc_nor0:$ea_result),
1005 "lfdux $rD, $addr", LdStLFDU,
1006 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
1007 NoEncode<"$ea_result">;
1011 // Indexed (r+r) Loads.
1013 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
1014 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
1015 "lbzx $rD, $src", LdStLoad,
1016 [(set i32:$rD, (zextloadi8 xaddr:$src))]>;
1017 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
1018 "lhax $rD, $src", LdStLHA,
1019 [(set i32:$rD, (sextloadi16 xaddr:$src))]>,
1020 PPC970_DGroup_Cracked;
1021 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
1022 "lhzx $rD, $src", LdStLoad,
1023 [(set i32:$rD, (zextloadi16 xaddr:$src))]>;
1024 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
1025 "lwzx $rD, $src", LdStLoad,
1026 [(set i32:$rD, (load xaddr:$src))]>;
1029 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
1030 "lhbrx $rD, $src", LdStLoad,
1031 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>;
1032 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
1033 "lwbrx $rD, $src", LdStLoad,
1034 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>;
1036 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
1037 "lfsx $frD, $src", LdStLFD,
1038 [(set f32:$frD, (load xaddr:$src))]>;
1039 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
1040 "lfdx $frD, $src", LdStLFD,
1041 [(set f64:$frD, (load xaddr:$src))]>;
1043 def LFIWAX : XForm_25<31, 855, (outs F8RC:$frD), (ins memrr:$src),
1044 "lfiwax $frD, $src", LdStLFD,
1045 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>;
1046 def LFIWZX : XForm_25<31, 887, (outs F8RC:$frD), (ins memrr:$src),
1047 "lfiwzx $frD, $src", LdStLFD,
1048 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>;
1051 //===----------------------------------------------------------------------===//
1052 // PPC32 Store Instructions.
1055 // Unindexed (r+i) Stores.
1056 let PPC970_Unit = 2 in {
1057 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
1058 "stb $rS, $src", LdStStore,
1059 [(truncstorei8 i32:$rS, iaddr:$src)]>;
1060 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
1061 "sth $rS, $src", LdStStore,
1062 [(truncstorei16 i32:$rS, iaddr:$src)]>;
1063 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
1064 "stw $rS, $src", LdStStore,
1065 [(store i32:$rS, iaddr:$src)]>;
1066 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
1067 "stfs $rS, $dst", LdStSTFD,
1068 [(store f32:$rS, iaddr:$dst)]>;
1069 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
1070 "stfd $rS, $dst", LdStSTFD,
1071 [(store f64:$rS, iaddr:$dst)]>;
1074 // Unindexed (r+i) Stores with Update (preinc).
1075 let PPC970_Unit = 2, mayStore = 1 in {
1076 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1077 "stbu $rS, $dst", LdStStoreUpd, []>,
1078 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1079 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1080 "sthu $rS, $dst", LdStStoreUpd, []>,
1081 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1082 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst),
1083 "stwu $rS, $dst", LdStStoreUpd, []>,
1084 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1085 def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst),
1086 "stfsu $rS, $dst", LdStSTFDU, []>,
1087 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1088 def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst),
1089 "stfdu $rS, $dst", LdStSTFDU, []>,
1090 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
1093 // Patterns to match the pre-inc stores. We can't put the patterns on
1094 // the instruction definitions directly as ISel wants the address base
1095 // and offset to be separate operands, not a single complex operand.
1096 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1097 (STBU $rS, iaddroff:$ptroff, $ptrreg)>;
1098 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1099 (STHU $rS, iaddroff:$ptroff, $ptrreg)>;
1100 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1101 (STWU $rS, iaddroff:$ptroff, $ptrreg)>;
1102 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1103 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>;
1104 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1105 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>;
1107 // Indexed (r+r) Stores.
1108 let PPC970_Unit = 2 in {
1109 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
1110 "stbx $rS, $dst", LdStStore,
1111 [(truncstorei8 i32:$rS, xaddr:$dst)]>,
1112 PPC970_DGroup_Cracked;
1113 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
1114 "sthx $rS, $dst", LdStStore,
1115 [(truncstorei16 i32:$rS, xaddr:$dst)]>,
1116 PPC970_DGroup_Cracked;
1117 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
1118 "stwx $rS, $dst", LdStStore,
1119 [(store i32:$rS, xaddr:$dst)]>,
1120 PPC970_DGroup_Cracked;
1122 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
1123 "sthbrx $rS, $dst", LdStStore,
1124 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>,
1125 PPC970_DGroup_Cracked;
1126 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
1127 "stwbrx $rS, $dst", LdStStore,
1128 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>,
1129 PPC970_DGroup_Cracked;
1131 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
1132 "stfiwx $frS, $dst", LdStSTFD,
1133 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>;
1135 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
1136 "stfsx $frS, $dst", LdStSTFD,
1137 [(store f32:$frS, xaddr:$dst)]>;
1138 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
1139 "stfdx $frS, $dst", LdStSTFD,
1140 [(store f64:$frS, xaddr:$dst)]>;
1143 // Indexed (r+r) Stores with Update (preinc).
1144 let PPC970_Unit = 2, mayStore = 1 in {
1145 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1146 "stbux $rS, $dst", LdStStoreUpd, []>,
1147 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1148 PPC970_DGroup_Cracked;
1149 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1150 "sthux $rS, $dst", LdStStoreUpd, []>,
1151 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1152 PPC970_DGroup_Cracked;
1153 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memrr:$dst),
1154 "stwux $rS, $dst", LdStStoreUpd, []>,
1155 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1156 PPC970_DGroup_Cracked;
1157 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memrr:$dst),
1158 "stfsux $rS, $dst", LdStSTFDU, []>,
1159 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1160 PPC970_DGroup_Cracked;
1161 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memrr:$dst),
1162 "stfdux $rS, $dst", LdStSTFDU, []>,
1163 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1164 PPC970_DGroup_Cracked;
1167 // Patterns to match the pre-inc stores. We can't put the patterns on
1168 // the instruction definitions directly as ISel wants the address base
1169 // and offset to be separate operands, not a single complex operand.
1170 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1171 (STBUX $rS, $ptrreg, $ptroff)>;
1172 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1173 (STHUX $rS, $ptrreg, $ptroff)>;
1174 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1175 (STWUX $rS, $ptrreg, $ptroff)>;
1176 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1177 (STFSUX $rS, $ptrreg, $ptroff)>;
1178 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1179 (STFDUX $rS, $ptrreg, $ptroff)>;
1181 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
1185 //===----------------------------------------------------------------------===//
1186 // PPC32 Arithmetic Instructions.
1189 let PPC970_Unit = 1 in { // FXU Operations.
1190 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$imm),
1191 "addi $rD, $rA, $imm", IntSimple,
1192 [(set i32:$rD, (add i32:$rA, immSExt16:$imm))]>;
1193 let Defs = [CARRY], BaseName = "addic" in {
1194 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1195 "addic $rD, $rA, $imm", IntGeneral,
1196 [(set i32:$rD, (addc i32:$rA, immSExt16:$imm))]>,
1197 RecFormRel, PPC970_DGroup_Cracked;
1198 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1199 "addic. $rD, $rA, $imm", IntGeneral,
1200 []>, isDOT, RecFormRel;
1202 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolHi:$imm),
1203 "addis $rD, $rA, $imm", IntSimple,
1204 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
1205 let isCodeGenOnly = 1 in
1206 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC_NOR0:$rA, symbolLo:$sym),
1207 "la $rD, $sym($rA)", IntGeneral,
1208 [(set i32:$rD, (add i32:$rA,
1209 (PPClo tglobaladdr:$sym, 0)))]>;
1210 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1211 "mulli $rD, $rA, $imm", IntMulLI,
1212 [(set i32:$rD, (mul i32:$rA, immSExt16:$imm))]>;
1213 let Defs = [CARRY] in {
1214 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
1215 "subfic $rD, $rA, $imm", IntGeneral,
1216 [(set i32:$rD, (subc immSExt16:$imm, i32:$rA))]>;
1219 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
1220 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
1221 "li $rD, $imm", IntSimple,
1222 [(set i32:$rD, immSExt16:$imm)]>;
1223 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
1224 "lis $rD, $imm", IntSimple,
1225 [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
1229 let PPC970_Unit = 1 in { // FXU Operations.
1230 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1231 "andi. $dst, $src1, $src2", IntGeneral,
1232 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
1234 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1235 "andis. $dst, $src1, $src2", IntGeneral,
1236 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
1238 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1239 "ori $dst, $src1, $src2", IntSimple,
1240 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>;
1241 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1242 "oris $dst, $src1, $src2", IntSimple,
1243 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>;
1244 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1245 "xori $dst, $src1, $src2", IntSimple,
1246 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>;
1247 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1248 "xoris $dst, $src1, $src2", IntSimple,
1249 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>;
1250 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1252 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1253 "cmpwi $crD, $rA, $imm", IntCompare>;
1254 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1255 "cmplwi $dst, $src1, $src2", IntCompare>;
1258 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1259 defm NAND : XForm_6r<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1260 "nand", "$rA, $rS, $rB", IntSimple,
1261 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>;
1262 defm AND : XForm_6r<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1263 "and", "$rA, $rS, $rB", IntSimple,
1264 [(set i32:$rA, (and i32:$rS, i32:$rB))]>;
1265 defm ANDC : XForm_6r<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1266 "andc", "$rA, $rS, $rB", IntSimple,
1267 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>;
1268 defm OR : XForm_6r<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1269 "or", "$rA, $rS, $rB", IntSimple,
1270 [(set i32:$rA, (or i32:$rS, i32:$rB))]>;
1271 defm NOR : XForm_6r<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1272 "nor", "$rA, $rS, $rB", IntSimple,
1273 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>;
1274 defm ORC : XForm_6r<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1275 "orc", "$rA, $rS, $rB", IntSimple,
1276 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>;
1277 defm EQV : XForm_6r<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1278 "eqv", "$rA, $rS, $rB", IntSimple,
1279 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>;
1280 defm XOR : XForm_6r<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1281 "xor", "$rA, $rS, $rB", IntSimple,
1282 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>;
1283 defm SLW : XForm_6r<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1284 "slw", "$rA, $rS, $rB", IntGeneral,
1285 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>;
1286 defm SRW : XForm_6r<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1287 "srw", "$rA, $rS, $rB", IntGeneral,
1288 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
1289 let Defs = [CARRY] in {
1290 defm SRAW : XForm_6r<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1291 "sraw", "$rA, $rS, $rB", IntShift,
1292 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
1296 let PPC970_Unit = 1 in { // FXU Operations.
1297 let neverHasSideEffects = 1 in {
1298 let Defs = [CARRY] in {
1299 defm SRAWI : XForm_10r<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1300 "srawi", "$rA, $rS, $SH", IntShift,
1301 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
1303 defm CNTLZW : XForm_11r<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1304 "cntlzw", "$rA, $rS", IntGeneral,
1305 [(set i32:$rA, (ctlz i32:$rS))]>;
1306 defm EXTSB : XForm_11r<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1307 "extsb", "$rA, $rS", IntSimple,
1308 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>;
1309 defm EXTSH : XForm_11r<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1310 "extsh", "$rA, $rS", IntSimple,
1311 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>;
1313 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1314 "cmpw $crD, $rA, $rB", IntCompare>;
1315 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1316 "cmplw $crD, $rA, $rB", IntCompare>;
1318 let PPC970_Unit = 3 in { // FPU Operations.
1319 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1320 // "fcmpo $crD, $fA, $fB", FPCompare>;
1321 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1322 "fcmpu $crD, $fA, $fB", FPCompare>;
1323 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1324 "fcmpu $crD, $fA, $fB", FPCompare>;
1326 let Uses = [RM] in {
1327 let neverHasSideEffects = 1 in {
1328 defm FCTIWZ : XForm_26r<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1329 "fctiwz", "$frD, $frB", FPGeneral,
1330 [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
1332 defm FRSP : XForm_26r<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1333 "frsp", "$frD, $frB", FPGeneral,
1334 [(set f32:$frD, (fround f64:$frB))]>;
1336 // The frin -> nearbyint mapping is valid only in fast-math mode.
1337 let Interpretation64Bit = 1 in
1338 defm FRIND : XForm_26r<63, 392, (outs F8RC:$frD), (ins F8RC:$frB),
1339 "frin", "$frD, $frB", FPGeneral,
1340 [(set f64:$frD, (fnearbyint f64:$frB))]>;
1341 defm FRINS : XForm_26r<63, 392, (outs F4RC:$frD), (ins F4RC:$frB),
1342 "frin", "$frD, $frB", FPGeneral,
1343 [(set f32:$frD, (fnearbyint f32:$frB))]>;
1346 // These pseudos expand to rint but also set FE_INEXACT when the result does
1347 // not equal the argument.
1348 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR!
1349 def FRINDrint : Pseudo<(outs F8RC:$frD), (ins F8RC:$frB),
1350 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>;
1351 def FRINSrint : Pseudo<(outs F4RC:$frD), (ins F4RC:$frB),
1352 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>;
1355 let neverHasSideEffects = 1 in {
1356 let Interpretation64Bit = 1 in
1357 defm FRIPD : XForm_26r<63, 456, (outs F8RC:$frD), (ins F8RC:$frB),
1358 "frip", "$frD, $frB", FPGeneral,
1359 [(set f64:$frD, (fceil f64:$frB))]>;
1360 defm FRIPS : XForm_26r<63, 456, (outs F4RC:$frD), (ins F4RC:$frB),
1361 "frip", "$frD, $frB", FPGeneral,
1362 [(set f32:$frD, (fceil f32:$frB))]>;
1363 let Interpretation64Bit = 1 in
1364 defm FRIZD : XForm_26r<63, 424, (outs F8RC:$frD), (ins F8RC:$frB),
1365 "friz", "$frD, $frB", FPGeneral,
1366 [(set f64:$frD, (ftrunc f64:$frB))]>;
1367 defm FRIZS : XForm_26r<63, 424, (outs F4RC:$frD), (ins F4RC:$frB),
1368 "friz", "$frD, $frB", FPGeneral,
1369 [(set f32:$frD, (ftrunc f32:$frB))]>;
1370 let Interpretation64Bit = 1 in
1371 defm FRIMD : XForm_26r<63, 488, (outs F8RC:$frD), (ins F8RC:$frB),
1372 "frim", "$frD, $frB", FPGeneral,
1373 [(set f64:$frD, (ffloor f64:$frB))]>;
1374 defm FRIMS : XForm_26r<63, 488, (outs F4RC:$frD), (ins F4RC:$frB),
1375 "frim", "$frD, $frB", FPGeneral,
1376 [(set f32:$frD, (ffloor f32:$frB))]>;
1378 defm FSQRT : XForm_26r<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1379 "fsqrt", "$frD, $frB", FPSqrt,
1380 [(set f64:$frD, (fsqrt f64:$frB))]>;
1381 defm FSQRTS : XForm_26r<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1382 "fsqrts", "$frD, $frB", FPSqrt,
1383 [(set f32:$frD, (fsqrt f32:$frB))]>;
1388 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1389 /// often coalesced away and we don't want the dispatch group builder to think
1390 /// that they will fill slots (which could cause the load of a LSU reject to
1391 /// sneak into a d-group with a store).
1392 let neverHasSideEffects = 1 in
1393 defm FMR : XForm_26r<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1394 "fmr", "$frD, $frB", FPGeneral,
1395 []>, // (set f32:$frD, f32:$frB)
1398 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1399 // These are artificially split into two different forms, for 4/8 byte FP.
1400 defm FABSS : XForm_26r<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1401 "fabs", "$frD, $frB", FPGeneral,
1402 [(set f32:$frD, (fabs f32:$frB))]>;
1403 let Interpretation64Bit = 1 in
1404 defm FABSD : XForm_26r<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1405 "fabs", "$frD, $frB", FPGeneral,
1406 [(set f64:$frD, (fabs f64:$frB))]>;
1407 defm FNABSS : XForm_26r<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1408 "fnabs", "$frD, $frB", FPGeneral,
1409 [(set f32:$frD, (fneg (fabs f32:$frB)))]>;
1410 let Interpretation64Bit = 1 in
1411 defm FNABSD : XForm_26r<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1412 "fnabs", "$frD, $frB", FPGeneral,
1413 [(set f64:$frD, (fneg (fabs f64:$frB)))]>;
1414 defm FNEGS : XForm_26r<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1415 "fneg", "$frD, $frB", FPGeneral,
1416 [(set f32:$frD, (fneg f32:$frB))]>;
1417 let Interpretation64Bit = 1 in
1418 defm FNEGD : XForm_26r<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1419 "fneg", "$frD, $frB", FPGeneral,
1420 [(set f64:$frD, (fneg f64:$frB))]>;
1422 // Reciprocal estimates.
1423 defm FRE : XForm_26r<63, 24, (outs F8RC:$frD), (ins F8RC:$frB),
1424 "fre", "$frD, $frB", FPGeneral,
1425 [(set f64:$frD, (PPCfre f64:$frB))]>;
1426 defm FRES : XForm_26r<59, 24, (outs F4RC:$frD), (ins F4RC:$frB),
1427 "fres", "$frD, $frB", FPGeneral,
1428 [(set f32:$frD, (PPCfre f32:$frB))]>;
1429 defm FRSQRTE : XForm_26r<63, 26, (outs F8RC:$frD), (ins F8RC:$frB),
1430 "frsqrte", "$frD, $frB", FPGeneral,
1431 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>;
1432 defm FRSQRTES : XForm_26r<59, 26, (outs F4RC:$frD), (ins F4RC:$frB),
1433 "frsqrtes", "$frD, $frB", FPGeneral,
1434 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>;
1437 // XL-Form instructions. condition register logical ops.
1439 let neverHasSideEffects = 1 in
1440 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1441 "mcrf $BF, $BFA", BrMCR>,
1442 PPC970_DGroup_First, PPC970_Unit_CRU;
1444 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1445 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1446 "creqv $CRD, $CRA, $CRB", BrCR,
1449 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1450 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1451 "cror $CRD, $CRA, $CRB", BrCR,
1454 let isCodeGenOnly = 1 in {
1455 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1456 "creqv $dst, $dst, $dst", BrCR,
1459 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1460 "crxor $dst, $dst, $dst", BrCR,
1463 let Defs = [CR1EQ], CRD = 6 in {
1464 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins),
1465 "creqv 6, 6, 6", BrCR,
1468 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins),
1469 "crxor 6, 6, 6", BrCR,
1474 // XFX-Form instructions. Instructions that deal with SPRs.
1476 let Uses = [CTR] in {
1477 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1478 "mfctr $rT", SprMFSPR>,
1479 PPC970_DGroup_First, PPC970_Unit_FXU;
1481 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in {
1482 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1483 "mtctr $rS", SprMTSPR>,
1484 PPC970_DGroup_First, PPC970_Unit_FXU;
1487 let Defs = [LR] in {
1488 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1489 "mtlr $rS", SprMTSPR>,
1490 PPC970_DGroup_First, PPC970_Unit_FXU;
1492 let Uses = [LR] in {
1493 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1494 "mflr $rT", SprMFSPR>,
1495 PPC970_DGroup_First, PPC970_Unit_FXU;
1498 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1499 // a GPR on the PPC970. As such, copies in and out have the same performance
1500 // characteristics as an OR instruction.
1501 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1502 "mtspr 256, $rS", IntGeneral>,
1503 PPC970_DGroup_Single, PPC970_Unit_FXU;
1504 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1505 "mfspr $rT, 256", IntGeneral>,
1506 PPC970_DGroup_First, PPC970_Unit_FXU;
1508 let isCodeGenOnly = 1 in {
1509 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256,
1510 (outs VRSAVERC:$reg), (ins GPRC:$rS),
1511 "mtspr 256, $rS", IntGeneral>,
1512 PPC970_DGroup_Single, PPC970_Unit_FXU;
1513 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT),
1514 (ins VRSAVERC:$reg),
1515 "mfspr $rT, 256", IntGeneral>,
1516 PPC970_DGroup_First, PPC970_Unit_FXU;
1519 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register,
1520 // so we'll need to scavenge a register for it.
1522 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1523 "#SPILL_VRSAVE", []>;
1525 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously
1526 // spilled), so we'll need to scavenge a register for it.
1528 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1529 "#RESTORE_VRSAVE", []>;
1531 let neverHasSideEffects = 1 in {
1532 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1533 "mtcrf $FXM, $rS", BrMCRX>,
1534 PPC970_MicroCode, PPC970_Unit_CRU;
1536 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1537 // declaring that here gives the local register allocator problems with this:
1539 // MFCR <kill of whatever preg got assigned to vreg>
1540 // while not declaring it breaks DeadMachineInstructionElimination.
1541 // As it turns out, in all cases where we currently use this,
1542 // we're only interested in one subregister of it. Represent this in the
1543 // instruction to keep the register allocator from becoming confused.
1545 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1546 let isCodeGenOnly = 1 in
1547 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1548 "#MFCRpseud", SprMFCR>,
1549 PPC970_MicroCode, PPC970_Unit_CRU;
1551 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1552 "mfocrf $rT, $FXM", SprMFCR>,
1553 PPC970_DGroup_First, PPC970_Unit_CRU;
1554 } // neverHasSideEffects = 1
1556 // MFCR uses all CR registers, but marking that explicitly causes
1557 // problems because some of them appear to be undefined. Because
1558 // this form is used only in prologue code, just mark it as having
1560 let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in
1561 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1562 "mfcr $rT", SprMFCR>,
1563 PPC970_MicroCode, PPC970_Unit_CRU;
1565 // Pseudo instruction to perform FADD in round-to-zero mode.
1566 let usesCustomInserter = 1, Uses = [RM] in {
1567 def FADDrtz: Pseudo<(outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB), "",
1568 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
1571 // The above pseudo gets expanded to make use of the following instructions
1572 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
1573 let Uses = [RM], Defs = [RM] in {
1574 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1575 "mtfsb0 $FM", IntMTFSB0, []>,
1576 PPC970_DGroup_Single, PPC970_Unit_FPU;
1577 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1578 "mtfsb1 $FM", IntMTFSB0, []>,
1579 PPC970_DGroup_Single, PPC970_Unit_FPU;
1580 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, F8RC:$rT),
1581 "mtfsf $FM, $rT", IntMTFSB0, []>,
1582 PPC970_DGroup_Single, PPC970_Unit_FPU;
1584 let Uses = [RM] in {
1585 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1586 "mffs $rT", IntMFFS,
1587 [(set f64:$rT, (PPCmffs))]>,
1588 PPC970_DGroup_Single, PPC970_Unit_FPU;
1592 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations.
1593 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1595 defm ADD4 : XOForm_1r<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1596 "add", "$rT, $rA, $rB", IntSimple,
1597 [(set i32:$rT, (add i32:$rA, i32:$rB))]>;
1598 let Defs = [CARRY] in {
1599 defm ADDC : XOForm_1r<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1600 "addc", "$rT, $rA, $rB", IntGeneral,
1601 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
1602 PPC970_DGroup_Cracked;
1604 defm DIVW : XOForm_1r<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1605 "divw", "$rT, $rA, $rB", IntDivW,
1606 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
1607 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1608 defm DIVWU : XOForm_1r<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1609 "divwu", "$rT, $rA, $rB", IntDivW,
1610 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
1611 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1612 defm MULHW : XOForm_1r<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1613 "mulhw", "$rT, $rA, $rB", IntMulHW,
1614 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
1615 defm MULHWU : XOForm_1r<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1616 "mulhwu", "$rT, $rA, $rB", IntMulHWU,
1617 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
1618 defm MULLW : XOForm_1r<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1619 "mullw", "$rT, $rA, $rB", IntMulHW,
1620 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>;
1621 defm SUBF : XOForm_1r<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1622 "subf", "$rT, $rA, $rB", IntGeneral,
1623 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>;
1624 let Defs = [CARRY] in {
1625 defm SUBFC : XOForm_1r<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1626 "subfc", "$rT, $rA, $rB", IntGeneral,
1627 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>,
1628 PPC970_DGroup_Cracked;
1630 defm NEG : XOForm_3r<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1631 "neg", "$rT, $rA", IntSimple,
1632 [(set i32:$rT, (ineg i32:$rA))]>;
1633 let Uses = [CARRY], Defs = [CARRY] in {
1634 defm ADDE : XOForm_1r<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1635 "adde", "$rT, $rA, $rB", IntGeneral,
1636 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>;
1637 defm ADDME : XOForm_3r<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1638 "addme", "$rT, $rA", IntGeneral,
1639 [(set i32:$rT, (adde i32:$rA, -1))]>;
1640 defm ADDZE : XOForm_3r<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1641 "addze", "$rT, $rA", IntGeneral,
1642 [(set i32:$rT, (adde i32:$rA, 0))]>;
1643 defm SUBFE : XOForm_1r<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1644 "subfe", "$rT, $rA, $rB", IntGeneral,
1645 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>;
1646 defm SUBFME : XOForm_3r<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1647 "subfme", "$rT, $rA", IntGeneral,
1648 [(set i32:$rT, (sube -1, i32:$rA))]>;
1649 defm SUBFZE : XOForm_3r<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1650 "subfze", "$rT, $rA", IntGeneral,
1651 [(set i32:$rT, (sube 0, i32:$rA))]>;
1655 // A-Form instructions. Most of the instructions executed in the FPU are of
1658 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations.
1659 let Uses = [RM] in {
1660 defm FMADD : AForm_1r<63, 29,
1661 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1662 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1663 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
1664 defm FMADDS : AForm_1r<59, 29,
1665 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1666 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1667 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
1668 defm FMSUB : AForm_1r<63, 28,
1669 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1670 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1672 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
1673 defm FMSUBS : AForm_1r<59, 28,
1674 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1675 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1677 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
1678 defm FNMADD : AForm_1r<63, 31,
1679 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1680 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused,
1682 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
1683 defm FNMADDS : AForm_1r<59, 31,
1684 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1685 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1687 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
1688 defm FNMSUB : AForm_1r<63, 30,
1689 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1690 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused,
1691 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
1692 (fneg f64:$FRB))))]>;
1693 defm FNMSUBS : AForm_1r<59, 30,
1694 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1695 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1696 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
1697 (fneg f32:$FRB))))]>;
1699 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1700 // having 4 of these, force the comparison to always be an 8-byte double (code
1701 // should use an FMRSD if the input comparison value really wants to be a float)
1702 // and 4/8 byte forms for the result and operand type..
1703 let Interpretation64Bit = 1 in
1704 defm FSELD : AForm_1r<63, 23,
1705 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1706 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1707 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>;
1708 defm FSELS : AForm_1r<63, 23,
1709 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1710 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral,
1711 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>;
1712 let Uses = [RM] in {
1713 defm FADD : AForm_2r<63, 21,
1714 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1715 "fadd", "$FRT, $FRA, $FRB", FPAddSub,
1716 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>;
1717 defm FADDS : AForm_2r<59, 21,
1718 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1719 "fadds", "$FRT, $FRA, $FRB", FPGeneral,
1720 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>;
1721 defm FDIV : AForm_2r<63, 18,
1722 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1723 "fdiv", "$FRT, $FRA, $FRB", FPDivD,
1724 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>;
1725 defm FDIVS : AForm_2r<59, 18,
1726 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1727 "fdivs", "$FRT, $FRA, $FRB", FPDivS,
1728 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>;
1729 defm FMUL : AForm_3r<63, 25,
1730 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC),
1731 "fmul", "$FRT, $FRA, $FRC", FPFused,
1732 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>;
1733 defm FMULS : AForm_3r<59, 25,
1734 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC),
1735 "fmuls", "$FRT, $FRA, $FRC", FPGeneral,
1736 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>;
1737 defm FSUB : AForm_2r<63, 20,
1738 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1739 "fsub", "$FRT, $FRA, $FRB", FPAddSub,
1740 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>;
1741 defm FSUBS : AForm_2r<59, 20,
1742 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1743 "fsubs", "$FRT, $FRA, $FRB", FPGeneral,
1744 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>;
1748 let neverHasSideEffects = 1 in {
1749 let PPC970_Unit = 1 in { // FXU Operations.
1751 def ISEL : AForm_4<31, 15,
1752 (outs GPRC:$rT), (ins GPRC_NOR0:$rA, GPRC:$rB, CRBITRC:$cond),
1753 "isel $rT, $rA, $rB, $cond", IntGeneral,
1757 let PPC970_Unit = 1 in { // FXU Operations.
1758 // M-Form instructions. rotate and mask instructions.
1760 let isCommutable = 1 in {
1761 // RLWIMI can be commuted if the rotate amount is zero.
1762 defm RLWIMI : MForm_2r<20, (outs GPRC:$rA),
1763 (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1764 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate,
1765 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1768 let BaseName = "rlwinm" in {
1769 def RLWINM : MForm_2<21,
1770 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1771 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1773 def RLWINMo : MForm_2<21,
1774 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1775 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1776 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
1778 defm RLWNM : MForm_2r<23, (outs GPRC:$rA),
1779 (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1780 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral,
1783 } // neverHasSideEffects = 1
1785 //===----------------------------------------------------------------------===//
1786 // PowerPC Instruction Patterns
1789 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1790 def : Pat<(i32 imm:$imm),
1791 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1793 // Implement the 'not' operation with the NOR instruction.
1794 def NOT : Pat<(not i32:$in),
1797 // ADD an arbitrary immediate.
1798 def : Pat<(add i32:$in, imm:$imm),
1799 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1800 // OR an arbitrary immediate.
1801 def : Pat<(or i32:$in, imm:$imm),
1802 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1803 // XOR an arbitrary immediate.
1804 def : Pat<(xor i32:$in, imm:$imm),
1805 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1807 def : Pat<(sub immSExt16:$imm, i32:$in),
1808 (SUBFIC $in, imm:$imm)>;
1811 def : Pat<(shl i32:$in, (i32 imm:$imm)),
1812 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>;
1813 def : Pat<(srl i32:$in, (i32 imm:$imm)),
1814 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>;
1817 def : Pat<(rotl i32:$in, i32:$sh),
1818 (RLWNM $in, $sh, 0, 31)>;
1819 def : Pat<(rotl i32:$in, (i32 imm:$imm)),
1820 (RLWINM $in, imm:$imm, 0, 31)>;
1823 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm),
1824 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1827 def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
1828 (BL tglobaladdr:$dst)>;
1829 def : Pat<(PPCcall (i32 texternalsym:$dst)),
1830 (BL texternalsym:$dst)>;
1833 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1834 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1836 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1837 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1839 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1840 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1844 // Hi and Lo for Darwin Global Addresses.
1845 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1846 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1847 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1848 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1849 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1850 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1851 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1852 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1853 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in),
1854 (ADDIS $in, tglobaltlsaddr:$g)>;
1855 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in),
1856 (ADDI $in, tglobaltlsaddr:$g)>;
1857 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)),
1858 (ADDIS $in, tglobaladdr:$g)>;
1859 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)),
1860 (ADDIS $in, tconstpool:$g)>;
1861 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)),
1862 (ADDIS $in, tjumptable:$g)>;
1863 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)),
1864 (ADDIS $in, tblockaddress:$g)>;
1866 // Standard shifts. These are represented separately from the real shifts above
1867 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1869 def : Pat<(sra i32:$rS, i32:$rB),
1871 def : Pat<(srl i32:$rS, i32:$rB),
1873 def : Pat<(shl i32:$rS, i32:$rB),
1876 def : Pat<(zextloadi1 iaddr:$src),
1878 def : Pat<(zextloadi1 xaddr:$src),
1880 def : Pat<(extloadi1 iaddr:$src),
1882 def : Pat<(extloadi1 xaddr:$src),
1884 def : Pat<(extloadi8 iaddr:$src),
1886 def : Pat<(extloadi8 xaddr:$src),
1888 def : Pat<(extloadi16 iaddr:$src),
1890 def : Pat<(extloadi16 xaddr:$src),
1892 def : Pat<(f64 (extloadf32 iaddr:$src)),
1893 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1894 def : Pat<(f64 (extloadf32 xaddr:$src)),
1895 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1897 def : Pat<(f64 (fextend f32:$src)),
1898 (COPY_TO_REGCLASS $src, F8RC)>;
1901 def : Pat<(membarrier (i32 imm /*ll*/),
1905 (i32 imm /*device*/)),
1908 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1910 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
1911 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
1912 (FNMSUB $A, $C, $B)>;
1913 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
1914 (FNMSUB $A, $C, $B)>;
1915 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
1916 (FNMSUBS $A, $C, $B)>;
1917 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
1918 (FNMSUBS $A, $C, $B)>;
1920 include "PPCInstrAltivec.td"
1921 include "PPCInstr64Bit.td"