1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific type constraints.
20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
23 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
26 def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
30 def SDT_PPCvcmp : SDTypeProfile<1, 3, [
31 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
34 def SDT_PPCcondbr : SDTypeProfile<0, 3, [
35 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
38 def SDT_PPClbrx : SDTypeProfile<1, 2, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
41 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
45 def SDT_PPClarx : SDTypeProfile<1, 1, [
46 SDTCisInt<0>, SDTCisPtrTy<1>
48 def SDT_PPCstcx : SDTypeProfile<0, 2, [
49 SDTCisInt<0>, SDTCisPtrTy<1>
52 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
53 SDTCisPtrTy<0>, SDTCisVT<1, i32>
56 def SDT_PPCnop : SDTypeProfile<0, 0, []>;
58 //===----------------------------------------------------------------------===//
59 // PowerPC specific DAG Nodes.
62 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
63 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
64 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
65 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
66 [SDNPHasChain, SDNPMayStore]>;
68 // This sequence is used for long double->int conversions. It changes the
69 // bits in the FPSCR which is not modelled.
70 def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
72 def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
73 [SDNPInGlue, SDNPOutGlue]>;
74 def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
75 [SDNPInGlue, SDNPOutGlue]>;
76 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
77 [SDNPInGlue, SDNPOutGlue]>;
78 def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
79 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
83 def PPCfsel : SDNode<"PPCISD::FSEL",
84 // Type constraint for fsel.
85 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
86 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
88 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
89 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
90 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>;
91 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
92 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
94 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
96 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
97 // amounts. These nodes are generated by the multi-precision shift code.
98 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
99 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
100 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
102 def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
103 def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
104 [SDNPHasChain, SDNPMayStore]>;
106 // These are target-independent nodes, but have target-specific formats.
107 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
112 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
113 def PPCcall_Darwin : SDNode<"PPCISD::CALL_Darwin", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
116 def PPCcall_SVR4 : SDNode<"PPCISD::CALL_SVR4", SDT_PPCCall,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def PPCcall_nop_SVR4 : SDNode<"PPCISD::CALL_NOP_SVR4", SDT_PPCCall,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def PPCnop : SDNode<"PPCISD::NOP", SDT_PPCnop, [SDNPInGlue, SDNPOutGlue]>;
123 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
125 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>,
126 [SDNPHasChain, SDNPSideEffect,
127 SDNPInGlue, SDNPOutGlue]>;
128 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>,
129 [SDNPHasChain, SDNPSideEffect,
130 SDNPInGlue, SDNPOutGlue]>;
131 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
133 def PPCbctrl_Darwin : SDNode<"PPCISD::BCTRL_Darwin", SDTNone,
134 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
137 def PPCbctrl_SVR4 : SDNode<"PPCISD::BCTRL_SVR4", SDTNone,
138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
141 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
144 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret,
145 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
147 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
148 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>;
150 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
151 [SDNPHasChain, SDNPOptInGlue]>;
153 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
154 [SDNPHasChain, SDNPMayLoad]>;
155 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
156 [SDNPHasChain, SDNPMayStore]>;
158 // Instructions to support atomic operations
159 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
160 [SDNPHasChain, SDNPMayLoad]>;
161 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
162 [SDNPHasChain, SDNPMayStore]>;
164 // Instructions to support dynamic alloca.
165 def SDTDynOp : SDTypeProfile<1, 2, []>;
166 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
168 //===----------------------------------------------------------------------===//
169 // PowerPC specific transformation functions and pattern fragments.
172 def SHL32 : SDNodeXForm<imm, [{
173 // Transformation function: 31 - imm
174 return getI32Imm(31 - N->getZExtValue());
177 def SRL32 : SDNodeXForm<imm, [{
178 // Transformation function: 32 - imm
179 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0);
182 def LO16 : SDNodeXForm<imm, [{
183 // Transformation function: get the low 16 bits.
184 return getI32Imm((unsigned short)N->getZExtValue());
187 def HI16 : SDNodeXForm<imm, [{
188 // Transformation function: shift the immediate value down into the low bits.
189 return getI32Imm((unsigned)N->getZExtValue() >> 16);
192 def HA16 : SDNodeXForm<imm, [{
193 // Transformation function: shift the immediate value down into the low bits.
194 signed int Val = N->getZExtValue();
195 return getI32Imm((Val - (signed short)Val) >> 16);
197 def MB : SDNodeXForm<imm, [{
198 // Transformation function: get the start bit of a mask
200 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
201 return getI32Imm(mb);
204 def ME : SDNodeXForm<imm, [{
205 // Transformation function: get the end bit of a mask
207 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
208 return getI32Imm(me);
210 def maskimm32 : PatLeaf<(imm), [{
211 // maskImm predicate - True if immediate is a run of ones.
213 if (N->getValueType(0) == MVT::i32)
214 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
219 def immSExt16 : PatLeaf<(imm), [{
220 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
221 // field. Used by instructions like 'addi'.
222 if (N->getValueType(0) == MVT::i32)
223 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
225 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
227 def immZExt16 : PatLeaf<(imm), [{
228 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
229 // field. Used by instructions like 'ori'.
230 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
233 // imm16Shifted* - These match immediates where the low 16-bits are zero. There
234 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
235 // identical in 32-bit mode, but in 64-bit mode, they return true if the
236 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits
238 def imm16ShiftedZExt : PatLeaf<(imm), [{
239 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
240 // immediate are set. Used by instructions like 'xoris'.
241 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0;
244 def imm16ShiftedSExt : PatLeaf<(imm), [{
245 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
246 // immediate are set. Used by instructions like 'addis'. Identical to
247 // imm16ShiftedZExt in 32-bit mode.
248 if (N->getZExtValue() & 0xFFFF) return false;
249 if (N->getValueType(0) == MVT::i32)
251 // For 64-bit, make sure it is sext right.
252 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
256 //===----------------------------------------------------------------------===//
257 // PowerPC Flag Definitions.
259 class isPPC64 { bit PPC64 = 1; }
261 list<Register> Defs = [CR0];
265 class RegConstraint<string C> {
266 string Constraints = C;
268 class NoEncode<string E> {
269 string DisableEncoding = E;
273 //===----------------------------------------------------------------------===//
274 // PowerPC Operand Definitions.
276 def s5imm : Operand<i32> {
277 let PrintMethod = "printS5ImmOperand";
279 def u5imm : Operand<i32> {
280 let PrintMethod = "printU5ImmOperand";
282 def u6imm : Operand<i32> {
283 let PrintMethod = "printU6ImmOperand";
285 def s16imm : Operand<i32> {
286 let PrintMethod = "printS16ImmOperand";
288 def u16imm : Operand<i32> {
289 let PrintMethod = "printU16ImmOperand";
291 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
292 let PrintMethod = "printS16X4ImmOperand";
294 def directbrtarget : Operand<OtherVT> {
295 let PrintMethod = "printBranchOperand";
296 let EncoderMethod = "getDirectBrEncoding";
298 def condbrtarget : Operand<OtherVT> {
299 let PrintMethod = "printBranchOperand";
300 let EncoderMethod = "getCondBrEncoding";
302 def calltarget : Operand<iPTR> {
303 let EncoderMethod = "getDirectBrEncoding";
305 def aaddr : Operand<iPTR> {
306 let PrintMethod = "printAbsAddrOperand";
308 def symbolHi: Operand<i32> {
309 let PrintMethod = "printSymbolHi";
310 let EncoderMethod = "getHA16Encoding";
312 def symbolLo: Operand<i32> {
313 let PrintMethod = "printSymbolLo";
314 let EncoderMethod = "getLO16Encoding";
316 def crbitm: Operand<i8> {
317 let PrintMethod = "printcrbitm";
318 let EncoderMethod = "get_crbitm_encoding";
321 def memri : Operand<iPTR> {
322 let PrintMethod = "printMemRegImm";
323 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
324 let EncoderMethod = "getMemRIEncoding";
326 def memrr : Operand<iPTR> {
327 let PrintMethod = "printMemRegReg";
328 let MIOperandInfo = (ops ptr_rc:$offreg, ptr_rc:$ptrreg);
330 def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
331 let PrintMethod = "printMemRegImmShifted";
332 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
333 let EncoderMethod = "getMemRIXEncoding";
335 def tocentry : Operand<iPTR> {
336 let MIOperandInfo = (ops i32imm:$imm);
339 // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
340 // that doesn't matter.
341 def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
342 (ops (i32 20), (i32 zero_reg))> {
343 let PrintMethod = "printPredicateOperand";
346 // Define PowerPC specific addressing mode.
347 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
348 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
349 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
350 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
352 /// This is just the offset part of iaddr, used for preinc.
353 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
354 def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
356 //===----------------------------------------------------------------------===//
357 // PowerPC Instruction Predicate Definitions.
358 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
359 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
360 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
362 //===----------------------------------------------------------------------===//
363 // PowerPC Instruction Definitions.
365 // Pseudo-instructions:
367 let hasCtrlDep = 1 in {
368 let Defs = [R1], Uses = [R1] in {
369 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
370 [(callseq_start timm:$amt)]>;
371 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
372 [(callseq_end timm:$amt1, timm:$amt2)]>;
375 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
376 "UPDATE_VRSAVE $rD, $rS", []>;
379 let Defs = [R1], Uses = [R1] in
380 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
382 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
384 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
385 // instruction selection into a branch sequence.
386 let usesCustomInserter = 1, // Expanded after instruction selection.
387 PPC970_Single = 1 in {
388 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
391 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
394 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
397 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
400 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
405 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
406 // scavenge a register for it.
408 def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
411 // RESTORE_CR - Indicate that we're restoring the CR register (previously
412 // spilled), so we'll need to scavenge a register for it.
414 def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
417 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
418 let isReturn = 1, Uses = [LR, RM] in
419 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
420 "b${p:cc}lr ${p:reg}", BrB,
422 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in
423 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
427 def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
430 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
431 let isBarrier = 1 in {
432 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst),
437 // BCC represents an arbitrary conditional branch on a predicate.
438 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
439 // a two-value operand where a dag node expects two operands. :(
440 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
441 "b${cond:cc} ${cond:reg}, $dst"
442 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
444 let Defs = [CTR], Uses = [CTR] in {
445 def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
446 "bdz $dst", BrB, []>;
447 def BDNZ : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
448 "bdnz $dst", BrB, []>;
453 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
454 // Convenient aliases for call instructions
456 def BL_Darwin : IForm<18, 0, 1,
457 (outs), (ins calltarget:$func),
458 "bl $func", BrB, []>; // See Pat patterns below.
459 def BLA_Darwin : IForm<18, 1, 1,
460 (outs), (ins aaddr:$func),
461 "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>;
463 let Uses = [CTR, RM] in {
464 def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
467 [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>;
472 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
473 // Convenient aliases for call instructions
475 def BL_SVR4 : IForm<18, 0, 1,
476 (outs), (ins calltarget:$func),
477 "bl $func", BrB, []>; // See Pat patterns below.
478 def BLA_SVR4 : IForm<18, 1, 1,
479 (outs), (ins aaddr:$func),
481 [(PPCcall_SVR4 (i32 imm:$func))]>;
483 let Uses = [CTR, RM] in {
484 def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1,
487 [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>;
492 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
493 def TCRETURNdi :Pseudo< (outs),
494 (ins calltarget:$dst, i32imm:$offset),
495 "#TC_RETURNd $dst $offset",
499 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
500 def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
501 "#TC_RETURNa $func $offset",
502 [(PPCtc_return (i32 imm:$func), imm:$offset)]>;
504 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
505 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
506 "#TC_RETURNr $dst $offset",
510 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
511 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in
512 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
513 Requires<[In32BitMode]>;
517 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
518 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
519 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
524 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
525 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
526 def TAILBA : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
531 // DCB* instructions.
532 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
533 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
534 PPC970_DGroup_Single;
535 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
536 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
537 PPC970_DGroup_Single;
538 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
539 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
540 PPC970_DGroup_Single;
541 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
542 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
543 PPC970_DGroup_Single;
544 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
545 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
546 PPC970_DGroup_Single;
547 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
548 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
549 PPC970_DGroup_Single;
550 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
551 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
552 PPC970_DGroup_Single;
553 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
554 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
555 PPC970_DGroup_Single;
557 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
561 let usesCustomInserter = 1 in {
562 let Defs = [CR0] in {
563 def ATOMIC_LOAD_ADD_I8 : Pseudo<
564 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
565 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
566 def ATOMIC_LOAD_SUB_I8 : Pseudo<
567 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
568 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
569 def ATOMIC_LOAD_AND_I8 : Pseudo<
570 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
571 [(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
572 def ATOMIC_LOAD_OR_I8 : Pseudo<
573 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
574 [(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
575 def ATOMIC_LOAD_XOR_I8 : Pseudo<
576 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
577 [(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
578 def ATOMIC_LOAD_NAND_I8 : Pseudo<
579 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
580 [(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
581 def ATOMIC_LOAD_ADD_I16 : Pseudo<
582 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
583 [(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
584 def ATOMIC_LOAD_SUB_I16 : Pseudo<
585 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
586 [(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
587 def ATOMIC_LOAD_AND_I16 : Pseudo<
588 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
589 [(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
590 def ATOMIC_LOAD_OR_I16 : Pseudo<
591 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
592 [(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
593 def ATOMIC_LOAD_XOR_I16 : Pseudo<
594 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
595 [(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
596 def ATOMIC_LOAD_NAND_I16 : Pseudo<
597 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
598 [(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
599 def ATOMIC_LOAD_ADD_I32 : Pseudo<
600 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
601 [(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
602 def ATOMIC_LOAD_SUB_I32 : Pseudo<
603 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
604 [(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
605 def ATOMIC_LOAD_AND_I32 : Pseudo<
606 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
607 [(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
608 def ATOMIC_LOAD_OR_I32 : Pseudo<
609 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
610 [(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
611 def ATOMIC_LOAD_XOR_I32 : Pseudo<
612 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
613 [(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
614 def ATOMIC_LOAD_NAND_I32 : Pseudo<
615 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
616 [(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
618 def ATOMIC_CMP_SWAP_I8 : Pseudo<
619 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
621 (atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
622 def ATOMIC_CMP_SWAP_I16 : Pseudo<
623 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
625 (atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
626 def ATOMIC_CMP_SWAP_I32 : Pseudo<
627 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
629 (atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
631 def ATOMIC_SWAP_I8 : Pseudo<
632 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
633 [(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
634 def ATOMIC_SWAP_I16 : Pseudo<
635 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
636 [(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
637 def ATOMIC_SWAP_I32 : Pseudo<
638 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
639 [(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
643 // Instructions to support atomic operations
644 def LWARX : XForm_1<31, 20, (outs GPRC:$rD), (ins memrr:$src),
645 "lwarx $rD, $src", LdStLWARX,
646 [(set GPRC:$rD, (PPClarx xoaddr:$src))]>;
649 def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst),
650 "stwcx. $rS, $dst", LdStSTWCX,
651 [(PPCstcx GPRC:$rS, xoaddr:$dst)]>,
654 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
655 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>;
657 //===----------------------------------------------------------------------===//
658 // PPC32 Load Instructions.
661 // Unindexed (r+i) Loads.
662 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
663 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
664 "lbz $rD, $src", LdStLoad,
665 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
666 def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
667 "lha $rD, $src", LdStLHA,
668 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
669 PPC970_DGroup_Cracked;
670 def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
671 "lhz $rD, $src", LdStLoad,
672 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
673 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
674 "lwz $rD, $src", LdStLoad,
675 [(set GPRC:$rD, (load iaddr:$src))]>;
677 def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
678 "lfs $rD, $src", LdStLFDU,
679 [(set F4RC:$rD, (load iaddr:$src))]>;
680 def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
681 "lfd $rD, $src", LdStLFD,
682 [(set F8RC:$rD, (load iaddr:$src))]>;
685 // Unindexed (r+i) Loads with Update (preinc).
687 def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
688 "lbzu $rD, $addr", LdStLoad,
689 []>, RegConstraint<"$addr.reg = $ea_result">,
690 NoEncode<"$ea_result">;
692 def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
693 "lhau $rD, $addr", LdStLoad,
694 []>, RegConstraint<"$addr.reg = $ea_result">,
695 NoEncode<"$ea_result">;
697 def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
698 "lhzu $rD, $addr", LdStLoad,
699 []>, RegConstraint<"$addr.reg = $ea_result">,
700 NoEncode<"$ea_result">;
702 def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
703 "lwzu $rD, $addr", LdStLoad,
704 []>, RegConstraint<"$addr.reg = $ea_result">,
705 NoEncode<"$ea_result">;
707 def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
708 "lfs $rD, $addr", LdStLFDU,
709 []>, RegConstraint<"$addr.reg = $ea_result">,
710 NoEncode<"$ea_result">;
712 def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
713 "lfd $rD, $addr", LdStLFD,
714 []>, RegConstraint<"$addr.reg = $ea_result">,
715 NoEncode<"$ea_result">;
718 // Indexed (r+r) Loads with Update (preinc).
719 def LBZUX : XForm_1<31, 119, (outs GPRC:$rD, ptr_rc:$ea_result),
721 "lbzux $rD, $addr", LdStLoad,
722 []>, RegConstraint<"$addr.offreg = $ea_result">,
723 NoEncode<"$ea_result">;
725 def LHAUX : XForm_1<31, 375, (outs GPRC:$rD, ptr_rc:$ea_result),
727 "lhaux $rD, $addr", LdStLoad,
728 []>, RegConstraint<"$addr.offreg = $ea_result">,
729 NoEncode<"$ea_result">;
731 def LHZUX : XForm_1<31, 331, (outs GPRC:$rD, ptr_rc:$ea_result),
733 "lhzux $rD, $addr", LdStLoad,
734 []>, RegConstraint<"$addr.offreg = $ea_result">,
735 NoEncode<"$ea_result">;
737 def LWZUX : XForm_1<31, 55, (outs GPRC:$rD, ptr_rc:$ea_result),
739 "lwzux $rD, $addr", LdStLoad,
740 []>, RegConstraint<"$addr.offreg = $ea_result">,
741 NoEncode<"$ea_result">;
743 def LFSUX : XForm_1<31, 567, (outs F4RC:$rD, ptr_rc:$ea_result),
745 "lfsux $rD, $addr", LdStLoad,
746 []>, RegConstraint<"$addr.offreg = $ea_result">,
747 NoEncode<"$ea_result">;
749 def LFDUX : XForm_1<31, 631, (outs F8RC:$rD, ptr_rc:$ea_result),
751 "lfdux $rD, $addr", LdStLoad,
752 []>, RegConstraint<"$addr.offreg = $ea_result">,
753 NoEncode<"$ea_result">;
757 // Indexed (r+r) Loads.
759 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
760 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
761 "lbzx $rD, $src", LdStLoad,
762 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
763 def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
764 "lhax $rD, $src", LdStLHA,
765 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
766 PPC970_DGroup_Cracked;
767 def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
768 "lhzx $rD, $src", LdStLoad,
769 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
770 def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
771 "lwzx $rD, $src", LdStLoad,
772 [(set GPRC:$rD, (load xaddr:$src))]>;
775 def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
776 "lhbrx $rD, $src", LdStLoad,
777 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i16))]>;
778 def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
779 "lwbrx $rD, $src", LdStLoad,
780 [(set GPRC:$rD, (PPClbrx xoaddr:$src, i32))]>;
782 def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
783 "lfsx $frD, $src", LdStLFDU,
784 [(set F4RC:$frD, (load xaddr:$src))]>;
785 def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
786 "lfdx $frD, $src", LdStLFDU,
787 [(set F8RC:$frD, (load xaddr:$src))]>;
790 //===----------------------------------------------------------------------===//
791 // PPC32 Store Instructions.
794 // Unindexed (r+i) Stores.
795 let PPC970_Unit = 2 in {
796 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
797 "stb $rS, $src", LdStStore,
798 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
799 def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
800 "sth $rS, $src", LdStStore,
801 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
802 def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
803 "stw $rS, $src", LdStStore,
804 [(store GPRC:$rS, iaddr:$src)]>;
805 def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
806 "stfs $rS, $dst", LdStUX,
807 [(store F4RC:$rS, iaddr:$dst)]>;
808 def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
809 "stfd $rS, $dst", LdStUX,
810 [(store F8RC:$rS, iaddr:$dst)]>;
813 // Unindexed (r+i) Stores with Update (preinc).
814 let PPC970_Unit = 2 in {
815 def STBU : DForm_1a<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
816 symbolLo:$ptroff, ptr_rc:$ptrreg),
817 "stbu $rS, $ptroff($ptrreg)", LdStStore,
818 [(set ptr_rc:$ea_res,
819 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
820 iaddroff:$ptroff))]>,
821 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
822 def STHU : DForm_1a<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
823 symbolLo:$ptroff, ptr_rc:$ptrreg),
824 "sthu $rS, $ptroff($ptrreg)", LdStStore,
825 [(set ptr_rc:$ea_res,
826 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
827 iaddroff:$ptroff))]>,
828 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
829 def STWU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
830 symbolLo:$ptroff, ptr_rc:$ptrreg),
831 "stwu $rS, $ptroff($ptrreg)", LdStStore,
832 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
833 iaddroff:$ptroff))]>,
834 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
835 def STFSU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
836 symbolLo:$ptroff, ptr_rc:$ptrreg),
837 "stfsu $rS, $ptroff($ptrreg)", LdStStore,
838 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
839 iaddroff:$ptroff))]>,
840 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
841 def STFDU : DForm_1a<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
842 symbolLo:$ptroff, ptr_rc:$ptrreg),
843 "stfdu $rS, $ptroff($ptrreg)", LdStStore,
844 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
845 iaddroff:$ptroff))]>,
846 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
850 // Indexed (r+r) Stores.
852 let PPC970_Unit = 2 in {
853 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
854 "stbx $rS, $dst", LdStStore,
855 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
856 PPC970_DGroup_Cracked;
857 def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
858 "sthx $rS, $dst", LdStStore,
859 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
860 PPC970_DGroup_Cracked;
861 def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
862 "stwx $rS, $dst", LdStStore,
863 [(store GPRC:$rS, xaddr:$dst)]>,
864 PPC970_DGroup_Cracked;
866 def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
867 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
868 "stbux $rS, $ptroff, $ptrreg", LdStStore,
869 [(set ptr_rc:$ea_res,
870 (pre_truncsti8 GPRC:$rS,
871 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
872 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
873 PPC970_DGroup_Cracked;
875 def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
876 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
877 "sthux $rS, $ptroff, $ptrreg", LdStStore,
878 [(set ptr_rc:$ea_res,
879 (pre_truncsti16 GPRC:$rS,
880 ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
881 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
882 PPC970_DGroup_Cracked;
884 def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
885 (ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
886 "stwux $rS, $ptroff, $ptrreg", LdStStore,
887 [(set ptr_rc:$ea_res,
888 (pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
889 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
890 PPC970_DGroup_Cracked;
892 def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
893 (ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
894 "stfsux $rS, $ptroff, $ptrreg", LdStStore,
895 [(set ptr_rc:$ea_res,
896 (pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
897 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
898 PPC970_DGroup_Cracked;
900 def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
901 (ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
902 "stfdux $rS, $ptroff, $ptrreg", LdStStore,
903 [(set ptr_rc:$ea_res,
904 (pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
905 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
906 PPC970_DGroup_Cracked;
908 def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
909 "sthbrx $rS, $dst", LdStStore,
910 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
911 PPC970_DGroup_Cracked;
912 def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
913 "stwbrx $rS, $dst", LdStStore,
914 [(PPCstbrx GPRC:$rS, xoaddr:$dst, i32)]>,
915 PPC970_DGroup_Cracked;
917 def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
918 "stfiwx $frS, $dst", LdStUX,
919 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
921 def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
922 "stfsx $frS, $dst", LdStUX,
923 [(store F4RC:$frS, xaddr:$dst)]>;
924 def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
925 "stfdx $frS, $dst", LdStUX,
926 [(store F8RC:$frS, xaddr:$dst)]>;
929 def SYNC : XForm_24_sync<31, 598, (outs), (ins),
933 //===----------------------------------------------------------------------===//
934 // PPC32 Arithmetic Instructions.
937 let PPC970_Unit = 1 in { // FXU Operations.
938 def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
939 "addi $rD, $rA, $imm", IntSimple,
940 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
941 def ADDIL : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$imm),
942 "addi $rD, $rA, $imm", IntSimple,
943 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
944 let Defs = [CARRY] in {
945 def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
946 "addic $rD, $rA, $imm", IntGeneral,
947 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
948 PPC970_DGroup_Cracked;
949 def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
950 "addic. $rD, $rA, $imm", IntGeneral,
953 def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
954 "addis $rD, $rA, $imm", IntSimple,
955 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
956 def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
957 "la $rD, $sym($rA)", IntGeneral,
958 [(set GPRC:$rD, (add GPRC:$rA,
959 (PPClo tglobaladdr:$sym, 0)))]>;
960 def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
961 "mulli $rD, $rA, $imm", IntMulLI,
962 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
963 let Defs = [CARRY] in {
964 def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
965 "subfic $rD, $rA, $imm", IntGeneral,
966 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
969 let isReMaterializable = 1 in {
970 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
971 "li $rD, $imm", IntSimple,
972 [(set GPRC:$rD, immSExt16:$imm)]>;
973 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
974 "lis $rD, $imm", IntSimple,
975 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
979 let PPC970_Unit = 1 in { // FXU Operations.
980 def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
981 "andi. $dst, $src1, $src2", IntGeneral,
982 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
984 def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
985 "andis. $dst, $src1, $src2", IntGeneral,
986 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
988 def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
989 "ori $dst, $src1, $src2", IntSimple,
990 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
991 def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
992 "oris $dst, $src1, $src2", IntSimple,
993 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
994 def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
995 "xori $dst, $src1, $src2", IntSimple,
996 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
997 def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
998 "xoris $dst, $src1, $src2", IntSimple,
999 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
1000 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple,
1002 def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
1003 "cmpwi $crD, $rA, $imm", IntCompare>;
1004 def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
1005 "cmplwi $dst, $src1, $src2", IntCompare>;
1009 let PPC970_Unit = 1 in { // FXU Operations.
1010 def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1011 "nand $rA, $rS, $rB", IntSimple,
1012 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
1013 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1014 "and $rA, $rS, $rB", IntSimple,
1015 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
1016 def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1017 "andc $rA, $rS, $rB", IntSimple,
1018 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
1019 def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1020 "or $rA, $rS, $rB", IntSimple,
1021 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
1022 def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1023 "nor $rA, $rS, $rB", IntSimple,
1024 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
1025 def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1026 "orc $rA, $rS, $rB", IntSimple,
1027 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
1028 def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1029 "eqv $rA, $rS, $rB", IntSimple,
1030 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
1031 def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1032 "xor $rA, $rS, $rB", IntSimple,
1033 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
1034 def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1035 "slw $rA, $rS, $rB", IntGeneral,
1036 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
1037 def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1038 "srw $rA, $rS, $rB", IntGeneral,
1039 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
1040 let Defs = [CARRY] in {
1041 def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1042 "sraw $rA, $rS, $rB", IntShift,
1043 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
1047 let PPC970_Unit = 1 in { // FXU Operations.
1048 let Defs = [CARRY] in {
1049 def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
1050 "srawi $rA, $rS, $SH", IntShift,
1051 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
1053 def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
1054 "cntlzw $rA, $rS", IntGeneral,
1055 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
1056 def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
1057 "extsb $rA, $rS", IntSimple,
1058 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
1059 def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
1060 "extsh $rA, $rS", IntSimple,
1061 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
1063 def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1064 "cmpw $crD, $rA, $rB", IntCompare>;
1065 def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
1066 "cmplw $crD, $rA, $rB", IntCompare>;
1068 let PPC970_Unit = 3 in { // FPU Operations.
1069 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
1070 // "fcmpo $crD, $fA, $fB", FPCompare>;
1071 def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
1072 "fcmpu $crD, $fA, $fB", FPCompare>;
1073 def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
1074 "fcmpu $crD, $fA, $fB", FPCompare>;
1076 let Uses = [RM] in {
1077 def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
1078 "fctiwz $frD, $frB", FPGeneral,
1079 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
1080 def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
1081 "frsp $frD, $frB", FPGeneral,
1082 [(set F4RC:$frD, (fround F8RC:$frB))]>;
1083 def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
1084 "fsqrt $frD, $frB", FPSqrt,
1085 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
1086 def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
1087 "fsqrts $frD, $frB", FPSqrt,
1088 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
1092 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1093 /// often coalesced away and we don't want the dispatch group builder to think
1094 /// that they will fill slots (which could cause the load of a LSU reject to
1095 /// sneak into a d-group with a store).
1096 def FMR : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
1097 "fmr $frD, $frB", FPGeneral,
1098 []>, // (set F4RC:$frD, F4RC:$frB)
1101 let PPC970_Unit = 3 in { // FPU Operations.
1102 // These are artificially split into two different forms, for 4/8 byte FP.
1103 def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
1104 "fabs $frD, $frB", FPGeneral,
1105 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
1106 def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
1107 "fabs $frD, $frB", FPGeneral,
1108 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
1109 def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
1110 "fnabs $frD, $frB", FPGeneral,
1111 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
1112 def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
1113 "fnabs $frD, $frB", FPGeneral,
1114 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
1115 def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
1116 "fneg $frD, $frB", FPGeneral,
1117 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
1118 def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
1119 "fneg $frD, $frB", FPGeneral,
1120 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
1124 // XL-Form instructions. condition register logical ops.
1126 def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
1127 "mcrf $BF, $BFA", BrMCR>,
1128 PPC970_DGroup_First, PPC970_Unit_CRU;
1130 def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
1131 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1132 "creqv $CRD, $CRA, $CRB", BrCR,
1135 def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
1136 (ins CRBITRC:$CRA, CRBITRC:$CRB),
1137 "cror $CRD, $CRA, $CRB", BrCR,
1140 def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
1141 "creqv $dst, $dst, $dst", BrCR,
1144 def CRUNSET: XLForm_1_ext<19, 193, (outs CRBITRC:$dst), (ins),
1145 "crxor $dst, $dst, $dst", BrCR,
1148 // XFX-Form instructions. Instructions that deal with SPRs.
1150 let Uses = [CTR] in {
1151 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
1152 "mfctr $rT", SprMFSPR>,
1153 PPC970_DGroup_First, PPC970_Unit_FXU;
1155 let Defs = [CTR], Pattern = [(PPCmtctr GPRC:$rS)] in {
1156 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
1157 "mtctr $rS", SprMTSPR>,
1158 PPC970_DGroup_First, PPC970_Unit_FXU;
1161 let Defs = [LR] in {
1162 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
1163 "mtlr $rS", SprMTSPR>,
1164 PPC970_DGroup_First, PPC970_Unit_FXU;
1166 let Uses = [LR] in {
1167 def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
1168 "mflr $rT", SprMFSPR>,
1169 PPC970_DGroup_First, PPC970_Unit_FXU;
1172 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
1173 // a GPR on the PPC970. As such, copies in and out have the same performance
1174 // characteristics as an OR instruction.
1175 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
1176 "mtspr 256, $rS", IntGeneral>,
1177 PPC970_DGroup_Single, PPC970_Unit_FXU;
1178 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
1179 "mfspr $rT, 256", IntGeneral>,
1180 PPC970_DGroup_First, PPC970_Unit_FXU;
1182 def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
1183 "mtcrf $FXM, $rS", BrMCRX>,
1184 PPC970_MicroCode, PPC970_Unit_CRU;
1186 // This is a pseudo for MFCR, which implicitly uses all 8 of its subregisters;
1187 // declaring that here gives the local register allocator problems with this:
1189 // MFCR <kill of whatever preg got assigned to vreg>
1190 // while not declaring it breaks DeadMachineInstructionElimination.
1191 // As it turns out, in all cases where we currently use this,
1192 // we're only interested in one subregister of it. Represent this in the
1193 // instruction to keep the register allocator from becoming confused.
1195 // FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
1196 def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1198 PPC970_MicroCode, PPC970_Unit_CRU;
1200 def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
1201 "mfcr $rT", SprMFCR>,
1202 PPC970_MicroCode, PPC970_Unit_CRU;
1204 def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
1205 "mfocrf $rT, $FXM", SprMFCR>,
1206 PPC970_DGroup_First, PPC970_Unit_CRU;
1208 // Instructions to manipulate FPSCR. Only long double handling uses these.
1209 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1211 let Uses = [RM], Defs = [RM] in {
1212 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
1213 "mtfsb0 $FM", IntMTFSB0,
1214 [(PPCmtfsb0 (i32 imm:$FM))]>,
1215 PPC970_DGroup_Single, PPC970_Unit_FPU;
1216 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
1217 "mtfsb1 $FM", IntMTFSB0,
1218 [(PPCmtfsb1 (i32 imm:$FM))]>,
1219 PPC970_DGroup_Single, PPC970_Unit_FPU;
1220 // MTFSF does not actually produce an FP result. We pretend it copies
1221 // input reg B to the output. If we didn't do this it would look like the
1222 // instruction had no outputs (because we aren't modelling the FPSCR) and
1223 // it would be deleted.
1224 def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
1225 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
1226 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
1227 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
1228 F8RC:$rT, F8RC:$FRB))]>,
1229 PPC970_DGroup_Single, PPC970_Unit_FPU;
1231 let Uses = [RM] in {
1232 def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
1233 "mffs $rT", IntMFFS,
1234 [(set F8RC:$rT, (PPCmffs))]>,
1235 PPC970_DGroup_Single, PPC970_Unit_FPU;
1236 def FADDrtz: AForm_2<63, 21,
1237 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1238 "fadd $FRT, $FRA, $FRB", FPGeneral,
1239 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
1240 PPC970_DGroup_Single, PPC970_Unit_FPU;
1244 let PPC970_Unit = 1 in { // FXU Operations.
1246 // XO-Form instructions. Arithmetic instructions that can set overflow bit
1248 def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1249 "add $rT, $rA, $rB", IntSimple,
1250 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
1251 let Defs = [CARRY] in {
1252 def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1253 "addc $rT, $rA, $rB", IntGeneral,
1254 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
1255 PPC970_DGroup_Cracked;
1257 def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1258 "divw $rT, $rA, $rB", IntDivW,
1259 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
1260 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1261 def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1262 "divwu $rT, $rA, $rB", IntDivW,
1263 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
1264 PPC970_DGroup_First, PPC970_DGroup_Cracked;
1265 def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1266 "mulhw $rT, $rA, $rB", IntMulHW,
1267 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
1268 def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1269 "mulhwu $rT, $rA, $rB", IntMulHWU,
1270 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
1271 def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1272 "mullw $rT, $rA, $rB", IntMulHW,
1273 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
1274 def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1275 "subf $rT, $rA, $rB", IntGeneral,
1276 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
1277 let Defs = [CARRY] in {
1278 def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1279 "subfc $rT, $rA, $rB", IntGeneral,
1280 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1281 PPC970_DGroup_Cracked;
1283 def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1284 "neg $rT, $rA", IntSimple,
1285 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
1286 let Uses = [CARRY], Defs = [CARRY] in {
1287 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1288 "adde $rT, $rA, $rB", IntGeneral,
1289 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
1290 def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1291 "addme $rT, $rA", IntGeneral,
1292 [(set GPRC:$rT, (adde GPRC:$rA, -1))]>;
1293 def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1294 "addze $rT, $rA", IntGeneral,
1295 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
1296 def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1297 "subfe $rT, $rA, $rB", IntGeneral,
1298 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
1299 def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1300 "subfme $rT, $rA", IntGeneral,
1301 [(set GPRC:$rT, (sube -1, GPRC:$rA))]>;
1302 def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
1303 "subfze $rT, $rA", IntGeneral,
1304 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
1308 // A-Form instructions. Most of the instructions executed in the FPU are of
1311 let PPC970_Unit = 3 in { // FPU Operations.
1312 let Uses = [RM] in {
1313 def FMADD : AForm_1<63, 29,
1314 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1315 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1317 (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB))]>;
1318 def FMADDS : AForm_1<59, 29,
1319 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1320 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1322 (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB))]>;
1323 def FMSUB : AForm_1<63, 28,
1324 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1325 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1327 (fma F8RC:$FRA, F8RC:$FRC, (fneg F8RC:$FRB)))]>;
1328 def FMSUBS : AForm_1<59, 28,
1329 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1330 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1332 (fma F4RC:$FRA, F4RC:$FRC, (fneg F4RC:$FRB)))]>;
1333 def FNMADD : AForm_1<63, 31,
1334 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1335 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1337 (fneg (fma F8RC:$FRA, F8RC:$FRC, F8RC:$FRB)))]>;
1338 def FNMADDS : AForm_1<59, 31,
1339 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1340 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1342 (fneg (fma F4RC:$FRA, F4RC:$FRC, F4RC:$FRB)))]>;
1343 def FNMSUB : AForm_1<63, 30,
1344 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1345 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1346 [(set F8RC:$FRT, (fneg (fma F8RC:$FRA, F8RC:$FRC,
1347 (fneg F8RC:$FRB))))]>;
1348 def FNMSUBS : AForm_1<59, 30,
1349 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1350 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
1351 [(set F4RC:$FRT, (fneg (fma F4RC:$FRA, F4RC:$FRC,
1352 (fneg F4RC:$FRB))))]>;
1354 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1355 // having 4 of these, force the comparison to always be an 8-byte double (code
1356 // should use an FMRSD if the input comparison value really wants to be a float)
1357 // and 4/8 byte forms for the result and operand type..
1358 def FSELD : AForm_1<63, 23,
1359 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1360 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1361 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
1362 def FSELS : AForm_1<63, 23,
1363 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1364 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
1365 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
1366 let Uses = [RM] in {
1367 def FADD : AForm_2<63, 21,
1368 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1369 "fadd $FRT, $FRA, $FRB", FPGeneral,
1370 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
1371 def FADDS : AForm_2<59, 21,
1372 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1373 "fadds $FRT, $FRA, $FRB", FPGeneral,
1374 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
1375 def FDIV : AForm_2<63, 18,
1376 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1377 "fdiv $FRT, $FRA, $FRB", FPDivD,
1378 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
1379 def FDIVS : AForm_2<59, 18,
1380 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1381 "fdivs $FRT, $FRA, $FRB", FPDivS,
1382 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
1383 def FMUL : AForm_3<63, 25,
1384 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1385 "fmul $FRT, $FRA, $FRB", FPFused,
1386 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
1387 def FMULS : AForm_3<59, 25,
1388 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1389 "fmuls $FRT, $FRA, $FRB", FPGeneral,
1390 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
1391 def FSUB : AForm_2<63, 20,
1392 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
1393 "fsub $FRT, $FRA, $FRB", FPGeneral,
1394 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
1395 def FSUBS : AForm_2<59, 20,
1396 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
1397 "fsubs $FRT, $FRA, $FRB", FPGeneral,
1398 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
1402 let PPC970_Unit = 1 in { // FXU Operations.
1403 def ISEL : AForm_1<31, 15,
1404 (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB, pred:$cond),
1405 "isel $rT, $rA, $rB, $cond", IntGeneral,
1409 let PPC970_Unit = 1 in { // FXU Operations.
1410 // M-Form instructions. rotate and mask instructions.
1412 let isCommutable = 1 in {
1413 // RLWIMI can be commuted if the rotate amount is zero.
1414 def RLWIMI : MForm_2<20,
1415 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
1416 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
1417 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1420 def RLWINM : MForm_2<21,
1421 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1422 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
1424 def RLWINMo : MForm_2<21,
1425 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
1426 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
1427 []>, isDOT, PPC970_DGroup_Cracked;
1428 def RLWNM : MForm_2<23,
1429 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
1430 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
1435 //===----------------------------------------------------------------------===//
1436 // PowerPC Instruction Patterns
1439 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1440 def : Pat<(i32 imm:$imm),
1441 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1443 // Implement the 'not' operation with the NOR instruction.
1444 def NOT : Pat<(not GPRC:$in),
1445 (NOR GPRC:$in, GPRC:$in)>;
1447 // ADD an arbitrary immediate.
1448 def : Pat<(add GPRC:$in, imm:$imm),
1449 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1450 // OR an arbitrary immediate.
1451 def : Pat<(or GPRC:$in, imm:$imm),
1452 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1453 // XOR an arbitrary immediate.
1454 def : Pat<(xor GPRC:$in, imm:$imm),
1455 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
1457 def : Pat<(sub immSExt16:$imm, GPRC:$in),
1458 (SUBFIC GPRC:$in, imm:$imm)>;
1461 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
1462 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
1463 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
1464 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
1467 def : Pat<(rotl GPRC:$in, GPRC:$sh),
1468 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1469 def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1470 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
1473 def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1474 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1477 def : Pat<(PPCcall_Darwin (i32 tglobaladdr:$dst)),
1478 (BL_Darwin tglobaladdr:$dst)>;
1479 def : Pat<(PPCcall_Darwin (i32 texternalsym:$dst)),
1480 (BL_Darwin texternalsym:$dst)>;
1481 def : Pat<(PPCcall_SVR4 (i32 tglobaladdr:$dst)),
1482 (BL_SVR4 tglobaladdr:$dst)>;
1483 def : Pat<(PPCcall_SVR4 (i32 texternalsym:$dst)),
1484 (BL_SVR4 texternalsym:$dst)>;
1487 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm),
1488 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
1490 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
1491 (TCRETURNdi texternalsym:$dst, imm:$imm)>;
1493 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
1494 (TCRETURNri CTRRC:$dst, imm:$imm)>;
1498 // Hi and Lo for Darwin Global Addresses.
1499 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1500 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1501 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1502 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
1503 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1504 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
1505 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>;
1506 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>;
1507 def : Pat<(PPChi tglobaltlsaddr:$g, GPRC:$in),
1508 (ADDIS GPRC:$in, tglobaltlsaddr:$g)>;
1509 def : Pat<(PPClo tglobaltlsaddr:$g, GPRC:$in),
1510 (ADDIL GPRC:$in, tglobaltlsaddr:$g)>;
1511 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1512 (ADDIS GPRC:$in, tglobaladdr:$g)>;
1513 def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1514 (ADDIS GPRC:$in, tconstpool:$g)>;
1515 def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1516 (ADDIS GPRC:$in, tjumptable:$g)>;
1517 def : Pat<(add GPRC:$in, (PPChi tblockaddress:$g, 0)),
1518 (ADDIS GPRC:$in, tblockaddress:$g)>;
1520 // Standard shifts. These are represented separately from the real shifts above
1521 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1523 def : Pat<(sra GPRC:$rS, GPRC:$rB),
1524 (SRAW GPRC:$rS, GPRC:$rB)>;
1525 def : Pat<(srl GPRC:$rS, GPRC:$rB),
1526 (SRW GPRC:$rS, GPRC:$rB)>;
1527 def : Pat<(shl GPRC:$rS, GPRC:$rB),
1528 (SLW GPRC:$rS, GPRC:$rB)>;
1530 def : Pat<(zextloadi1 iaddr:$src),
1532 def : Pat<(zextloadi1 xaddr:$src),
1534 def : Pat<(extloadi1 iaddr:$src),
1536 def : Pat<(extloadi1 xaddr:$src),
1538 def : Pat<(extloadi8 iaddr:$src),
1540 def : Pat<(extloadi8 xaddr:$src),
1542 def : Pat<(extloadi16 iaddr:$src),
1544 def : Pat<(extloadi16 xaddr:$src),
1546 def : Pat<(f64 (extloadf32 iaddr:$src)),
1547 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
1548 def : Pat<(f64 (extloadf32 xaddr:$src)),
1549 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
1551 def : Pat<(f64 (fextend F4RC:$src)),
1552 (COPY_TO_REGCLASS F4RC:$src, F8RC)>;
1555 def : Pat<(membarrier (i32 imm /*ll*/),
1559 (i32 imm /*device*/)),
1562 def : Pat<(atomic_fence (imm), (imm)), (SYNC)>;
1564 include "PPCInstrAltivec.td"
1565 include "PPCInstr64Bit.td"