1 //===- PowerPCInstrInfo.td - The PowerPC Instruction Set -----*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PowerPCInstrFormats.td"
17 class SDNode<string opcode, string sdclass = "SDNode"> {
18 string Opcode = opcode;
19 string SDClass = sdclass;
25 def imm : SDNode<"ISD::Constant", "ConstantSDNode">;
26 def vt : SDNode<"ISD::VALUETYPE", "VTSDNode">;
27 def and : SDNode<"ISD::AND">;
28 def or : SDNode<"ISD::OR">;
29 def xor : SDNode<"ISD::XOR">;
30 def add : SDNode<"ISD::ADD">;
31 def sub : SDNode<"ISD::SUB">;
32 def mul : SDNode<"ISD::MUL">;
33 def sdiv : SDNode<"ISD::SDIV">;
34 def udiv : SDNode<"ISD::UDIV">;
35 def mulhs : SDNode<"ISD::MULHS">;
36 def mulhu : SDNode<"ISD::MULHU">;
37 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG">;
38 def ctlz : SDNode<"ISD::CTLZ">;
40 /// PatFrag - Represents a pattern fragment. This can match something on the
41 /// DAG, frame a single node to multiply nested other fragments.
43 class PatFrag<dag ops, dag frag, code pred = [{}]> {
46 code Predicate = pred;
48 class PatLeaf<dag frag, code pred = [{}]> : PatFrag<(ops), frag, pred>;
52 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
53 def immZero : PatLeaf<(imm), [{ return N->isNullValue(); }]>;
55 def vtInt : PatLeaf<(vt), [{ return MVT::isInteger(N->getVT()); }]>;
56 def vtFP : PatLeaf<(vt), [{ return MVT::isFloatingPoint(N->getVT()); }]>;
58 // Other helper fragments.
60 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
61 def ineg : PatFrag<(ops node:$in), (sub immZero, node:$in)>;
63 class isPPC64 { bit PPC64 = 1; }
64 class isVMX { bit VMX = 1; }
66 list<Register> Defs = [CR0];
70 let isTerminator = 1 in {
72 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
73 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
76 def u5imm : Operand<i8> {
77 let PrintMethod = "printU5ImmOperand";
79 def u6imm : Operand<i8> {
80 let PrintMethod = "printU6ImmOperand";
82 def s16imm : Operand<i16> {
83 let PrintMethod = "printS16ImmOperand";
85 def u16imm : Operand<i16> {
86 let PrintMethod = "printU16ImmOperand";
88 def target : Operand<i32> {
89 let PrintMethod = "printBranchOperand";
91 def piclabel: Operand<i32> {
92 let PrintMethod = "printPICLabel";
94 def symbolHi: Operand<i32> {
95 let PrintMethod = "printSymbolHi";
97 def symbolLo: Operand<i32> {
98 let PrintMethod = "printSymbolLo";
100 def crbitm: Operand<i8> {
101 let PrintMethod = "printcrbitm";
104 // Pseudo-instructions:
105 def PHI : Pseudo<(ops variable_ops), "; PHI">;
107 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
108 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
110 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
111 def IMPLICIT_DEF_FP : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
113 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
114 // scheduler into a branch sequence.
115 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
116 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
117 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
118 def SELECT_CC_FP : Pseudo<(ops FPRC:$dst, CRRC:$cond, FPRC:$T, FPRC:$F,
119 i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
124 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
126 let isBranch = 1, isTerminator = 1 in {
127 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm, target:$true, target:$false),
129 def B : IForm<18, 0, 0, (ops target:$func), "b $func">;
130 //def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">;
131 def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">;
132 //def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">;
134 // FIXME: 4*CR# needs to be added to the BI field!
135 // This will only work for CR0 as it stands now
136 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
138 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
140 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
142 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
144 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
146 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
151 // All calls clobber the non-callee saved registers...
152 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
153 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
155 CR0,CR1,CR5,CR6,CR7] in {
156 // Convenient aliases for call instructions
157 def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">;
158 def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1,
159 (ops variable_ops), "bctrl">;
162 // D-Form instructions. Most instructions that perform an operation on a
163 // register and an immediate are of this type.
166 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
167 "lbz $rD, $disp($rA)">;
168 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
169 "lha $rD, $disp($rA)">;
170 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
171 "lhz $rD, $disp($rA)">;
172 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
173 "lmw $rD, $disp($rA)">;
174 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
175 "lwz $rD, $disp($rA)">;
176 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
177 "lwzu $rD, $disp($rA)">;
179 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
180 "addi $rD, $rA, $imm">;
181 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
182 "addic $rD, $rA, $imm">;
183 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
184 "addic. $rD, $rA, $imm">;
185 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
186 "addis $rD, $rA, $imm">;
187 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
188 "la $rD, $sym($rA)">;
189 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
190 "mulli $rD, $rA, $imm">;
191 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
192 "subfic $rD, $rA, $imm">;
193 def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm),
195 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
198 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
199 "stmw $rS, $disp($rA)">;
200 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
201 "stb $rS, $disp($rA)">;
202 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
203 "sth $rS, $disp($rA)">;
204 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
205 "stw $rS, $disp($rA)">;
206 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
207 "stwu $rS, $disp($rA)">;
209 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
210 "andi. $dst, $src1, $src2">, isDOT;
211 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
212 "andis. $dst, $src1, $src2">, isDOT;
213 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
214 "ori $dst, $src1, $src2">;
215 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
216 "oris $dst, $src1, $src2">;
217 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
218 "xori $dst, $src1, $src2">;
219 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
220 "xoris $dst, $src1, $src2">;
221 def NOP : DForm_4_zero<24, (ops), "nop">;
222 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
223 "cmpi $crD, $L, $rA, $imm">;
224 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
225 "cmpwi $crD, $rA, $imm">;
226 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
227 "cmpdi $crD, $rA, $imm">, isPPC64;
228 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
229 "cmpli $dst, $size, $src1, $src2">;
230 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
231 "cmplwi $dst, $src1, $src2">;
232 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
233 "cmpldi $dst, $src1, $src2">, isPPC64;
235 def LFS : DForm_8<48, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
236 "lfs $rD, $disp($rA)">;
237 def LFD : DForm_8<50, (ops FPRC:$rD, symbolLo:$disp, GPRC:$rA),
238 "lfd $rD, $disp($rA)">;
241 def STFS : DForm_9<52, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
242 "stfs $rS, $disp($rA)">;
243 def STFD : DForm_9<54, (ops FPRC:$rS, symbolLo:$disp, GPRC:$rA),
244 "stfd $rS, $disp($rA)">;
247 // DS-Form instructions. Load/Store instructions available in PPC-64
250 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
251 "lwa $rT, $DS($rA)">, isPPC64;
252 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
253 "ld $rT, $DS($rA)">, isPPC64;
256 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
257 "std $rT, $DS($rA)">, isPPC64;
258 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16imm:$DS, GPRC:$rA),
259 "stdu $rT, $DS($rA)">, isPPC64;
262 // X-Form instructions. Most instructions that perform an operation on a
263 // register and another register are of this type.
266 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
267 "lbzx $dst, $base, $index">;
268 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
269 "lhax $dst, $base, $index">;
270 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
271 "lhzx $dst, $base, $index">;
272 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
273 "lwax $dst, $base, $index">, isPPC64;
274 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
275 "lwzx $dst, $base, $index">;
276 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
277 "ldx $dst, $base, $index">, isPPC64;
279 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
280 "nand $rA, $rS, $rB",
281 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
282 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
284 [(set GPRC:$rT, (and GPRC:$rA, GPRC:$rB))]>;
285 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
286 "and. $rA, $rS, $rB",
288 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
289 "andc $rA, $rS, $rB",
290 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
291 def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
293 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
294 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
296 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
297 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
300 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
302 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
303 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
305 [(set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))]>;
306 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
308 [(set GPRC:$rT, (xor GPRC:$rA, GPRC:$rB))]>;
309 def SLD : XForm_6<31, 27, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
312 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
315 def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
318 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
321 def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
322 "srad $rA, $rS, $rB",
324 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
325 "sraw $rA, $rS, $rB",
328 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
329 "stbx $rS, $rA, $rB">;
330 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
331 "sthx $rS, $rA, $rB">;
332 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
333 "stwx $rS, $rA, $rB">;
334 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
335 "stwux $rS, $rA, $rB">;
336 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
337 "stdx $rS, $rA, $rB">, isPPC64;
338 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
339 "stdux $rS, $rA, $rB">, isPPC64;
341 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
342 "srawi $rA, $rS, $SH">;
343 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
345 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
346 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
348 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
349 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
351 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
352 def EXTSW : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
355 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
356 "cmp $crD, $long, $rA, $rB">;
357 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
358 "cmpl $crD, $long, $rA, $rB">;
359 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
360 "cmpw $crD, $rA, $rB">;
361 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
362 "cmpd $crD, $rA, $rB">, isPPC64;
363 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
364 "cmplw $crD, $rA, $rB">;
365 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
366 "cmpld $crD, $rA, $rB">, isPPC64;
367 def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
368 "fcmpo $crD, $fA, $fB">;
369 def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
370 "fcmpu $crD, $fA, $fB">;
372 def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
373 "lfsx $dst, $base, $index">;
374 def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
375 "lfdx $dst, $base, $index">;
377 def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
378 "fcfid $frD, $frB">, isPPC64;
379 def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
380 "fctidz $frD, $frB">, isPPC64;
381 def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
382 "fctiwz $frD, $frB">;
383 def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
385 def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
387 def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
389 def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
391 def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
393 def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
395 def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
396 "fsqrts $frD, $frB">;
399 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
400 "stfsx $frS, $rA, $rB">;
401 def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
402 "stfdx $frS, $rA, $rB">;
405 // XL-Form instructions. condition register logical ops.
407 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
410 // XFX-Form instructions. Instructions that deal with SPRs
412 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
413 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
414 // which means the SPR value needs to be multiplied by a factor of 32.
415 def MFCTR : XFXForm_1_ext<31, 339, 288, (ops GPRC:$rT), "mfctr $rT">;
416 def MFLR : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT), "mflr $rT">;
417 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
418 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
420 def MFOCRF : XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
422 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
423 def MTLR : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;
425 // XS-Form instructions. Just 'sradi'
427 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
428 "sradi $rA, $rS, $SH">, isPPC64;
430 // XO-Form instructions. Arithmetic instructions that can set overflow bit
432 def ADD : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
434 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
435 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
436 "addc $rT, $rA, $rB",
438 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
439 "adde $rT, $rA, $rB",
441 def DIVD : XOForm_1<31, 489, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
442 "divd $rT, $rA, $rB",
444 def DIVDU : XOForm_1<31, 457, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
445 "divdu $rT, $rA, $rB",
447 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
448 "divw $rT, $rA, $rB",
449 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
450 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
451 "divwu $rT, $rA, $rB",
452 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
453 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
454 "mulhw $rT, $rA, $rB",
455 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
456 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
457 "mulhwu $rT, $rA, $rB",
458 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
459 def MULLD : XOForm_1<31, 233, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
460 "mulld $rT, $rA, $rB",
462 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
463 "mullw $rT, $rA, $rB",
464 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
465 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
466 "subf $rT, $rA, $rB",
467 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
468 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
469 "subfc $rT, $rA, $rB",
471 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
472 "subfe $rT, $rA, $rB",
474 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
477 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
480 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
482 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
483 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
487 // A-Form instructions. Most of the instructions executed in the FPU are of
490 def FMADD : AForm_1<63, 29,
491 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
492 "fmadd $FRT, $FRA, $FRC, $FRB">;
493 def FMADDS : AForm_1<59, 29,
494 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
495 "fmadds $FRT, $FRA, $FRC, $FRB">;
496 def FMSUB : AForm_1<63, 28,
497 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
498 "fmsub $FRT, $FRA, $FRC, $FRB">;
499 def FMSUBS : AForm_1<59, 28,
500 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
501 "fmsubs $FRT, $FRA, $FRC, $FRB">;
502 def FNMADD : AForm_1<63, 31,
503 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
504 "fnmadd $FRT, $FRA, $FRC, $FRB">;
505 def FNMADDS : AForm_1<59, 31,
506 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
507 "fnmadds $FRT, $FRA, $FRC, $FRB">;
508 def FNMSUB : AForm_1<63, 30,
509 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
510 "fnmsub $FRT, $FRA, $FRC, $FRB">;
511 def FNMSUBS : AForm_1<59, 30,
512 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
513 "fnmsubs $FRT, $FRA, $FRC, $FRB">;
514 def FSEL : AForm_1<63, 23,
515 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
516 "fsel $FRT, $FRA, $FRC, $FRB">;
517 def FADD : AForm_2<63, 21,
518 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
519 "fadd $FRT, $FRA, $FRB">;
520 def FADDS : AForm_2<59, 21,
521 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
522 "fadds $FRT, $FRA, $FRB">;
523 def FDIV : AForm_2<63, 18,
524 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
525 "fdiv $FRT, $FRA, $FRB">;
526 def FDIVS : AForm_2<59, 18,
527 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
528 "fdivs $FRT, $FRA, $FRB">;
529 def FMUL : AForm_3<63, 25,
530 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
531 "fmul $FRT, $FRA, $FRB">;
532 def FMULS : AForm_3<59, 25,
533 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
534 "fmuls $FRT, $FRA, $FRB">;
535 def FSUB : AForm_2<63, 20,
536 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
537 "fsub $FRT, $FRA, $FRB">;
538 def FSUBS : AForm_2<59, 20,
539 (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
540 "fsubs $FRT, $FRA, $FRB">;
542 // M-Form instructions. rotate and mask instructions.
544 let isTwoAddress = 1 in {
545 def RLWIMI : MForm_2<20,
546 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
547 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
549 def RLWINM : MForm_2<21,
550 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
551 "rlwinm $rA, $rS, $SH, $MB, $ME">;
552 def RLWINMo : MForm_2<21,
553 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
554 "rlwinm. $rA, $rS, $SH, $MB, $ME">, isDOT;
555 def RLWNM : MForm_2<23,
556 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
557 "rlwnm $rA, $rS, $rB, $MB, $ME">;
559 // MD-Form instructions. 64 bit rotate instructions.
561 def RLDICL : MDForm_1<30, 0,
562 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB),
563 "rldicl $rA, $rS, $SH, $MB">, isPPC64;
564 def RLDICR : MDForm_1<30, 1,
565 (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME),
566 "rldicr $rA, $rS, $SH, $ME">, isPPC64;
568 def PowerPCInstrInfo : InstrInfo {
571 let TSFlagsFields = [ "VMX", "PPC64" ];
572 let TSFlagsShifts = [ 0, 1 ];
574 let isLittleEndianEncoding = 1;