1 //===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subset of the 32-bit PowerPC instruction set, as used
11 // by the PowerPC instruction selector.
13 //===----------------------------------------------------------------------===//
15 include "PPCInstrFormats.td"
17 //===----------------------------------------------------------------------===//
18 // PowerPC specific DAG Nodes.
21 def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
22 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
23 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
25 def PPCfsel : SDNode<"PPCISD::FSEL",
26 // Type constraint for fsel.
27 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
28 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
30 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
31 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
33 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
34 // amounts. These nodes are generated by the multi-precision shift code.
35 def SDT_PPCShiftOp : SDTypeProfile<1, 2, [ // PPCshl, PPCsra, PPCsrl
36 SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
38 def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
39 def PPCsra : SDNode<"PPCISD::SRA" , SDT_PPCShiftOp>;
40 def PPCshl : SDNode<"PPCISD::SHL" , SDT_PPCShiftOp>;
42 // These are target-independent nodes, but have target-specific formats.
43 def SDT_PPCCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
44 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
45 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
47 //===----------------------------------------------------------------------===//
48 // PowerPC specific transformation functions and pattern fragments.
51 def SHL32 : SDNodeXForm<imm, [{
52 // Transformation function: 31 - imm
53 return getI32Imm(31 - N->getValue());
56 def SHL64 : SDNodeXForm<imm, [{
57 // Transformation function: 63 - imm
58 return getI32Imm(63 - N->getValue());
61 def SRL32 : SDNodeXForm<imm, [{
62 // Transformation function: 32 - imm
63 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
66 def SRL64 : SDNodeXForm<imm, [{
67 // Transformation function: 64 - imm
68 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
71 def LO16 : SDNodeXForm<imm, [{
72 // Transformation function: get the low 16 bits.
73 return getI32Imm((unsigned short)N->getValue());
76 def HI16 : SDNodeXForm<imm, [{
77 // Transformation function: shift the immediate value down into the low bits.
78 return getI32Imm((unsigned)N->getValue() >> 16);
81 def HA16 : SDNodeXForm<imm, [{
82 // Transformation function: shift the immediate value down into the low bits.
83 signed int Val = N->getValue();
84 return getI32Imm((Val - (signed short)Val) >> 16);
88 def immSExt16 : PatLeaf<(imm), [{
89 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
90 // field. Used by instructions like 'addi'.
91 return (int)N->getValue() == (short)N->getValue();
93 def immZExt16 : PatLeaf<(imm), [{
94 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
95 // field. Used by instructions like 'ori'.
96 return (unsigned)N->getValue() == (unsigned short)N->getValue();
99 def imm16Shifted : PatLeaf<(imm), [{
100 // imm16Shifted predicate - True if only bits in the top 16-bits of the
101 // immediate are set. Used by instructions like 'addis'.
102 return ((unsigned)N->getValue() & 0xFFFF0000U) == (unsigned)N->getValue();
106 // Example of a legalize expander: Only for PPC64.
107 def : Expander<(set i64:$dst, (fp_to_sint f64:$src)),
108 [(set f64:$tmp , (FCTIDZ f64:$src)),
109 (set i32:$tmpFI, (CreateNewFrameIndex 8, 8)),
110 (store f64:$tmp, i32:$tmpFI),
111 (set i64:$dst, (load i32:$tmpFI))],
115 //===----------------------------------------------------------------------===//
116 // PowerPC Flag Definitions.
118 class isPPC64 { bit PPC64 = 1; }
119 class isVMX { bit VMX = 1; }
121 list<Register> Defs = [CR0];
127 //===----------------------------------------------------------------------===//
128 // PowerPC Operand Definitions.
130 def u5imm : Operand<i32> {
131 let PrintMethod = "printU5ImmOperand";
133 def u6imm : Operand<i32> {
134 let PrintMethod = "printU6ImmOperand";
136 def s16imm : Operand<i32> {
137 let PrintMethod = "printS16ImmOperand";
139 def u16imm : Operand<i32> {
140 let PrintMethod = "printU16ImmOperand";
142 def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
143 let PrintMethod = "printS16X4ImmOperand";
145 def target : Operand<OtherVT> {
146 let PrintMethod = "printBranchOperand";
148 def calltarget : Operand<i32> {
149 let PrintMethod = "printCallOperand";
151 def aaddr : Operand<i32> {
152 let PrintMethod = "printAbsAddrOperand";
154 def piclabel: Operand<i32> {
155 let PrintMethod = "printPICLabel";
157 def symbolHi: Operand<i32> {
158 let PrintMethod = "printSymbolHi";
160 def symbolLo: Operand<i32> {
161 let PrintMethod = "printSymbolLo";
163 def crbitm: Operand<i8> {
164 let PrintMethod = "printcrbitm";
169 //===----------------------------------------------------------------------===//
170 // PowerPC Instruction Definitions.
172 // Pseudo-instructions:
173 def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
175 let isLoad = 1, hasCtrlDep = 1 in {
176 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
177 "; ADJCALLSTACKDOWN",
178 [(callseq_start imm:$amt)]>;
179 def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
181 [(callseq_end imm:$amt)]>;
183 def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
184 [(set GPRC:$rD, (undef))]>;
185 def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8",
186 [(set F8RC:$rD, (undef))]>;
187 def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4",
188 [(set F4RC:$rD, (undef))]>;
190 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
191 // scheduler into a branch sequence.
192 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
193 def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
194 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
195 def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
196 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
197 def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
198 i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
202 let isTerminator = 1 in {
204 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>;
205 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>;
209 def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
211 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
212 def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
213 target:$true, target:$false),
214 "; COND_BRANCH", []>;
215 def B : IForm<18, 0, 0, (ops target:$dst),
219 // FIXME: 4*CR# needs to be added to the BI field!
220 // This will only work for CR0 as it stands now
221 def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
222 "blt $crS, $block", BrB>;
223 def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block),
224 "ble $crS, $block", BrB>;
225 def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block),
226 "beq $crS, $block", BrB>;
227 def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block),
228 "bge $crS, $block", BrB>;
229 def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block),
230 "bgt $crS, $block", BrB>;
231 def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block),
232 "bne $crS, $block", BrB>;
233 def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
234 "bun $crS, $block", BrB>;
235 def BNU : BForm<16, 0, 0, 4, 3, (ops CRRC:$crS, target:$block),
236 "bnu $crS, $block", BrB>;
240 // All calls clobber the non-callee saved registers...
241 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
242 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
244 CR0,CR1,CR5,CR6,CR7] in {
245 // Convenient aliases for call instructions
246 def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
247 "bl $func", BrB, []>;
248 def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
249 "bla $func", BrB, []>;
250 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB>;
253 // D-Form instructions. Most instructions that perform an operation on a
254 // register and an immediate are of this type.
257 def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
258 "lbz $rD, $disp($rA)", LdStGeneral,
260 def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
261 "lha $rD, $disp($rA)", LdStLHA,
263 def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
264 "lhz $rD, $disp($rA)", LdStGeneral,
266 def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
267 "lmw $rD, $disp($rA)", LdStLMW,
269 def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA),
270 "lwz $rD, $disp($rA)", LdStGeneral,
272 def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA),
273 "lwzu $rD, $disp($rA)", LdStGeneral,
276 def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
277 "addi $rD, $rA, $imm", IntGeneral,
278 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
279 def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
280 "addic $rD, $rA, $imm", IntGeneral,
282 def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
283 "addic. $rD, $rA, $imm", IntGeneral,
285 def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
286 "addis $rD, $rA, $imm", IntGeneral,
287 [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
288 def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
289 "la $rD, $sym($rA)", IntGeneral,
290 [(set GPRC:$rD, (add GPRC:$rA,
291 (PPClo tglobaladdr:$sym, 0)))]>;
292 def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
293 "mulli $rD, $rA, $imm", IntMulLI,
294 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
295 def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm),
296 "subfic $rD, $rA, $imm", IntGeneral,
297 [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>;
298 def LI : DForm_2_r0<14, (ops GPRC:$rD, symbolLo:$imm),
299 "li $rD, $imm", IntGeneral,
300 [(set GPRC:$rD, immSExt16:$imm)]>;
301 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
302 "lis $rD, $imm", IntGeneral,
303 [(set GPRC:$rD, imm16Shifted:$imm)]>;
305 def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
306 "stmw $rS, $disp($rA)", LdStLMW,
308 def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
309 "stb $rS, $disp($rA)", LdStGeneral,
311 def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
312 "sth $rS, $disp($rA)", LdStGeneral,
314 def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA),
315 "stw $rS, $disp($rA)", LdStGeneral,
317 def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
318 "stwu $rS, $disp($rA)", LdStGeneral,
321 def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
322 "andi. $dst, $src1, $src2", IntGeneral,
324 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
325 "andis. $dst, $src1, $src2", IntGeneral,
327 def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
328 "ori $dst, $src1, $src2", IntGeneral,
329 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
330 def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
331 "oris $dst, $src1, $src2", IntGeneral,
332 [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
333 def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
334 "xori $dst, $src1, $src2", IntGeneral,
335 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
336 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
337 "xoris $dst, $src1, $src2", IntGeneral,
338 [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
339 def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
341 def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
342 "cmpi $crD, $L, $rA, $imm", IntCompare>;
343 def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
344 "cmpwi $crD, $rA, $imm", IntCompare>;
345 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
346 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
347 def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
348 "cmpli $dst, $size, $src1, $src2", IntCompare>;
349 def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
350 "cmplwi $dst, $src1, $src2", IntCompare>;
351 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
352 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
354 def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA),
355 "lfs $rD, $disp($rA)", LdStLFDU,
357 def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA),
358 "lfd $rD, $disp($rA)", LdStLFD,
362 def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA),
363 "stfs $rS, $disp($rA)", LdStUX,
365 def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA),
366 "stfd $rS, $disp($rA)", LdStUX,
370 // DS-Form instructions. Load/Store instructions available in PPC-64
373 def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
374 "lwa $rT, $DS($rA)", LdStLWA,
376 def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
377 "ld $rT, $DS($rA)", LdStLD,
381 def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
382 "std $rT, $DS($rA)", LdStSTD,
384 def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA),
385 "stdu $rT, $DS($rA)", LdStSTD,
389 // X-Form instructions. Most instructions that perform an operation on a
390 // register and another register are of this type.
393 def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
394 "lbzx $dst, $base, $index", LdStGeneral,
396 def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
397 "lhax $dst, $base, $index", LdStLHA,
399 def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
400 "lhzx $dst, $base, $index", LdStGeneral,
402 def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
403 "lwax $dst, $base, $index", LdStLHA,
405 def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
406 "lwzx $dst, $base, $index", LdStGeneral,
408 def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
409 "ldx $dst, $base, $index", LdStLD,
411 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
412 "lvebx $vD, $base, $rA", LdStGeneral,
414 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
415 "lvehx $vD, $base, $rA", LdStGeneral,
417 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
418 "lvewx $vD, $base, $rA", LdStGeneral,
420 def LVX : XForm_1<31, 103, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
421 "lvx $vD, $base, $rA", LdStGeneral,
424 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
425 "lvsl $vD, $base, $rA", LdStGeneral,
427 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
428 "lvsl $vD, $base, $rA", LdStGeneral,
430 def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
431 "nand $rA, $rS, $rB", IntGeneral,
432 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
433 def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
434 "and $rA, $rS, $rB", IntGeneral,
435 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
436 def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
437 "and. $rA, $rS, $rB", IntGeneral,
439 def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
440 "andc $rA, $rS, $rB", IntGeneral,
441 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
442 def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
443 "or $rA, $rS, $rB", IntGeneral,
444 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
445 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
446 "or $rA, $rS, $rB", IntGeneral,
447 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
448 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
449 "or $rA, $rS, $rB", IntGeneral,
451 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
452 "or $rA, $rS, $rB", IntGeneral,
454 def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
455 "nor $rA, $rS, $rB", IntGeneral,
456 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
457 def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
458 "or. $rA, $rS, $rB", IntGeneral,
460 def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
461 "orc $rA, $rS, $rB", IntGeneral,
462 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
463 def EQV : XForm_6<31, 284, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
464 "eqv $rA, $rS, $rB", IntGeneral,
465 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
466 def XOR : XForm_6<31, 316, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
467 "xor $rA, $rS, $rB", IntGeneral,
468 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
469 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
470 "sld $rA, $rS, $rB", IntRotateD,
471 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
472 def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
473 "slw $rA, $rS, $rB", IntGeneral,
474 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
475 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
476 "srd $rA, $rS, $rB", IntRotateD,
477 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
478 def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
479 "srw $rA, $rS, $rB", IntGeneral,
480 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
481 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
482 "srad $rA, $rS, $rB", IntRotateD,
483 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
484 def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
485 "sraw $rA, $rS, $rB", IntShift,
486 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
488 def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
489 "stbx $rS, $rA, $rB", LdStGeneral,
491 def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
492 "sthx $rS, $rA, $rB", LdStGeneral,
494 def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
495 "stwx $rS, $rA, $rB", LdStGeneral,
497 def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
498 "stwux $rS, $rA, $rB", LdStGeneral,
500 def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
501 "stdx $rS, $rA, $rB", LdStSTD,
503 def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
504 "stdux $rS, $rA, $rB", LdStSTD,
506 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
507 "stvebx $rS, $rA, $rB", LdStGeneral,
509 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
510 "stvehx $rS, $rA, $rB", LdStGeneral,
512 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
513 "stvewx $rS, $rA, $rB", LdStGeneral,
515 def STVX : XForm_8<31, 231, (ops VRRC:$rS, GPRC:$rA, GPRC:$rB),
516 "stvx $rS, $rA, $rB", LdStGeneral,
519 def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
520 "srawi $rA, $rS, $SH", IntShift,
521 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
522 def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
523 "cntlzw $rA, $rS", IntGeneral,
524 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
525 def EXTSB : XForm_11<31, 954, (ops GPRC:$rA, GPRC:$rS),
526 "extsb $rA, $rS", IntGeneral,
527 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
528 def EXTSH : XForm_11<31, 922, (ops GPRC:$rA, GPRC:$rS),
529 "extsh $rA, $rS", IntGeneral,
530 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
531 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
532 "extsw $rA, $rS", IntGeneral,
533 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
534 def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
535 "cmp $crD, $long, $rA, $rB", IntCompare>;
536 def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
537 "cmpl $crD, $long, $rA, $rB", IntCompare>;
538 def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
539 "cmpw $crD, $rA, $rB", IntCompare>;
540 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
541 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
542 def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
543 "cmplw $crD, $rA, $rB", IntCompare>;
544 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
545 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
546 //def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
547 // "fcmpo $crD, $fA, $fB", FPCompare>;
548 def FCMPUS : XForm_17<63, 0, (ops CRRC:$crD, F4RC:$fA, F4RC:$fB),
549 "fcmpu $crD, $fA, $fB", FPCompare>;
550 def FCMPUD : XForm_17<63, 0, (ops CRRC:$crD, F8RC:$fA, F8RC:$fB),
551 "fcmpu $crD, $fA, $fB", FPCompare>;
554 def LFSX : XForm_25<31, 535, (ops F4RC:$dst, GPRC:$base, GPRC:$index),
555 "lfsx $dst, $base, $index", LdStLFDU,
557 def LFDX : XForm_25<31, 599, (ops F8RC:$dst, GPRC:$base, GPRC:$index),
558 "lfdx $dst, $base, $index", LdStLFDU,
561 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
562 "fcfid $frD, $frB", FPGeneral,
563 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
564 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
565 "fctidz $frD, $frB", FPGeneral,
566 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
567 def FCTIWZ : XForm_26<63, 15, (ops F8RC:$frD, F8RC:$frB),
568 "fctiwz $frD, $frB", FPGeneral,
569 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
570 def FRSP : XForm_26<63, 12, (ops F4RC:$frD, F8RC:$frB),
571 "frsp $frD, $frB", FPGeneral,
572 [(set F4RC:$frD, (fround F8RC:$frB))]>;
573 def FSQRT : XForm_26<63, 22, (ops F8RC:$frD, F8RC:$frB),
574 "fsqrt $frD, $frB", FPSqrt,
575 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
576 def FSQRTS : XForm_26<59, 22, (ops F4RC:$frD, F4RC:$frB),
577 "fsqrts $frD, $frB", FPSqrt,
578 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
580 /// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
581 def FMRS : XForm_26<63, 72, (ops F4RC:$frD, F4RC:$frB),
582 "fmr $frD, $frB", FPGeneral,
583 []>; // (set F4RC:$frD, F4RC:$frB)
584 def FMRD : XForm_26<63, 72, (ops F8RC:$frD, F8RC:$frB),
585 "fmr $frD, $frB", FPGeneral,
586 []>; // (set F8RC:$frD, F8RC:$frB)
587 def FMRSD : XForm_26<63, 72, (ops F8RC:$frD, F4RC:$frB),
588 "fmr $frD, $frB", FPGeneral,
589 [(set F8RC:$frD, (fextend F4RC:$frB))]>;
591 // These are artificially split into two different forms, for 4/8 byte FP.
592 def FABSS : XForm_26<63, 264, (ops F4RC:$frD, F4RC:$frB),
593 "fabs $frD, $frB", FPGeneral,
594 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
595 def FABSD : XForm_26<63, 264, (ops F8RC:$frD, F8RC:$frB),
596 "fabs $frD, $frB", FPGeneral,
597 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
598 def FNABSS : XForm_26<63, 136, (ops F4RC:$frD, F4RC:$frB),
599 "fnabs $frD, $frB", FPGeneral,
600 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
601 def FNABSD : XForm_26<63, 136, (ops F8RC:$frD, F8RC:$frB),
602 "fnabs $frD, $frB", FPGeneral,
603 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
604 def FNEGS : XForm_26<63, 40, (ops F4RC:$frD, F4RC:$frB),
605 "fneg $frD, $frB", FPGeneral,
606 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
607 def FNEGD : XForm_26<63, 40, (ops F8RC:$frD, F8RC:$frB),
608 "fneg $frD, $frB", FPGeneral,
609 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
613 def STFSX : XForm_28<31, 663, (ops F4RC:$frS, GPRC:$rA, GPRC:$rB),
614 "stfsx $frS, $rA, $rB", LdStUX,
616 def STFDX : XForm_28<31, 727, (ops F8RC:$frS, GPRC:$rA, GPRC:$rB),
617 "stfdx $frS, $rA, $rB", LdStUX,
621 // XL-Form instructions. condition register logical ops.
623 def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
624 "mcrf $BF, $BFA", BrMCR>;
626 // XFX-Form instructions. Instructions that deal with SPRs
628 // Note that although LR should be listed as `8' and CTR as `9' in the SPR
629 // field, the manual lists the groups of bits as [5-9] = 0, [0-4] = 8 or 9
630 // which means the SPR value needs to be multiplied by a factor of 32.
631 def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>;
632 def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>;
633 def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>;
634 def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
635 "mtcrf $FXM, $rS", BrMCRX>;
636 def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
637 "mfcr $rT, $FXM", SprMFCR>;
638 def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>;
639 def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>;
640 def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
643 // XS-Form instructions. Just 'sradi'
645 def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
646 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
648 // XO-Form instructions. Arithmetic instructions that can set overflow bit
650 def ADD4 : XOForm_1<31, 266, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
651 "add $rT, $rA, $rB", IntGeneral,
652 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
653 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
654 "add $rT, $rA, $rB", IntGeneral,
655 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
656 def ADDC : XOForm_1<31, 10, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
657 "addc $rT, $rA, $rB", IntGeneral,
659 def ADDE : XOForm_1<31, 138, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
660 "adde $rT, $rA, $rB", IntGeneral,
662 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
663 "divd $rT, $rA, $rB", IntDivD,
664 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
665 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
666 "divdu $rT, $rA, $rB", IntDivD,
667 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64;
668 def DIVW : XOForm_1<31, 491, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
669 "divw $rT, $rA, $rB", IntDivW,
670 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>;
671 def DIVWU : XOForm_1<31, 459, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
672 "divwu $rT, $rA, $rB", IntDivW,
673 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>;
674 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
675 "mulhd $rT, $rA, $rB", IntMulHW,
676 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
677 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
678 "mulhdu $rT, $rA, $rB", IntMulHWU,
679 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
680 def MULHW : XOForm_1<31, 75, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
681 "mulhw $rT, $rA, $rB", IntMulHW,
682 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
683 def MULHWU : XOForm_1<31, 11, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
684 "mulhwu $rT, $rA, $rB", IntMulHWU,
685 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
686 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
687 "mulld $rT, $rA, $rB", IntMulHD,
688 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
689 def MULLW : XOForm_1<31, 235, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
690 "mullw $rT, $rA, $rB", IntMulHW,
691 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
692 def SUBF : XOForm_1<31, 40, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
693 "subf $rT, $rA, $rB", IntGeneral,
694 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
695 def SUBFC : XOForm_1<31, 8, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
696 "subfc $rT, $rA, $rB", IntGeneral,
698 def SUBFE : XOForm_1<31, 136, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
699 "subfe $rT, $rA, $rB", IntGeneral,
701 def ADDME : XOForm_3<31, 234, 0, (ops GPRC:$rT, GPRC:$rA),
702 "addme $rT, $rA", IntGeneral,
704 def ADDZE : XOForm_3<31, 202, 0, (ops GPRC:$rT, GPRC:$rA),
705 "addze $rT, $rA", IntGeneral,
707 def NEG : XOForm_3<31, 104, 0, (ops GPRC:$rT, GPRC:$rA),
708 "neg $rT, $rA", IntGeneral,
709 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
710 def SUBFZE : XOForm_3<31, 200, 0, (ops GPRC:$rT, GPRC:$rA),
711 "subfze $rT, $rA", IntGeneral,
714 // A-Form instructions. Most of the instructions executed in the FPU are of
717 def FMADD : AForm_1<63, 29,
718 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
719 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
720 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
722 def FMADDS : AForm_1<59, 29,
723 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
724 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
725 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
727 def FMSUB : AForm_1<63, 28,
728 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
729 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
730 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
732 def FMSUBS : AForm_1<59, 28,
733 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
734 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
735 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
737 def FNMADD : AForm_1<63, 31,
738 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
739 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
740 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
742 def FNMADDS : AForm_1<59, 31,
743 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
744 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
745 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
747 def FNMSUB : AForm_1<63, 30,
748 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
749 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
750 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
752 def FNMSUBS : AForm_1<59, 30,
753 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
754 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
755 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
757 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
758 // having 4 of these, force the comparison to always be an 8-byte double (code
759 // should use an FMRSD if the input comparison value really wants to be a float)
760 // and 4/8 byte forms for the result and operand type..
761 def FSELD : AForm_1<63, 23,
762 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
763 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
764 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
765 def FSELS : AForm_1<63, 23,
766 (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
767 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
768 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
769 def FADD : AForm_2<63, 21,
770 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
771 "fadd $FRT, $FRA, $FRB", FPGeneral,
772 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
773 def FADDS : AForm_2<59, 21,
774 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
775 "fadds $FRT, $FRA, $FRB", FPGeneral,
776 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
777 def FDIV : AForm_2<63, 18,
778 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
779 "fdiv $FRT, $FRA, $FRB", FPDivD,
780 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
781 def FDIVS : AForm_2<59, 18,
782 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
783 "fdivs $FRT, $FRA, $FRB", FPDivS,
784 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
785 def FMUL : AForm_3<63, 25,
786 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
787 "fmul $FRT, $FRA, $FRB", FPFused,
788 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
789 def FMULS : AForm_3<59, 25,
790 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
791 "fmuls $FRT, $FRA, $FRB", FPGeneral,
792 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
793 def FSUB : AForm_2<63, 20,
794 (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
795 "fsub $FRT, $FRA, $FRB", FPGeneral,
796 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
797 def FSUBS : AForm_2<59, 20,
798 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
799 "fsubs $FRT, $FRA, $FRB", FPGeneral,
800 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
802 // M-Form instructions. rotate and mask instructions.
804 let isTwoAddress = 1, isCommutable = 1 in {
805 // RLWIMI can be commuted if the rotate amount is zero.
806 def RLWIMI : MForm_2<20,
807 (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
808 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
810 def RLDIMI : MDForm_1<30, 3,
811 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
812 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
815 def RLWINM : MForm_2<21,
816 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
817 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
819 def RLWINMo : MForm_2<21,
820 (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
821 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
823 def RLWNM : MForm_2<23,
824 (ops GPRC:$rA, GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
825 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
828 // MD-Form instructions. 64 bit rotate instructions.
830 def RLDICL : MDForm_1<30, 0,
831 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
832 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
834 def RLDICR : MDForm_1<30, 1,
835 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
836 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
839 // VA-Form instructions. 3-input AltiVec ops.
840 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
841 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
842 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
844 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
845 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
846 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA,
850 // VX-Form instructions. AltiVec arithmetic ops.
851 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
852 "vaddfp $vD, $vA, $vB", VecFP,
853 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
854 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
855 "vcfsx $vD, $vB, $UIMM", VecFP,
857 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
858 "vcfux $vD, $vB, $UIMM", VecFP,
860 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
861 "vctsxs $vD, $vB, $UIMM", VecFP,
863 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
864 "vctuxs $vD, $vB, $UIMM", VecFP,
866 def VEXPTEFP : VXForm_2<394, (ops VRRC:$vD, VRRC:$vB),
867 "vexptefp $vD, $vB", VecFP,
869 def VLOGEFP : VXForm_2<458, (ops VRRC:$vD, VRRC:$vB),
870 "vlogefp $vD, $vB", VecFP,
872 def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
873 "vmaxfp $vD, $vA, $vB", VecFP,
875 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
876 "vminfp $vD, $vA, $vB", VecFP,
878 def VREFP : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
879 "vrefp $vD, $vB", VecFP,
881 def VRFIM : VXForm_2<714, (ops VRRC:$vD, VRRC:$vB),
882 "vrfim $vD, $vB", VecFP,
884 def VRFIN : VXForm_2<522, (ops VRRC:$vD, VRRC:$vB),
885 "vrfin $vD, $vB", VecFP,
887 def VRFIP : VXForm_2<650, (ops VRRC:$vD, VRRC:$vB),
888 "vrfip $vD, $vB", VecFP,
890 def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
891 "vrfiz $vD, $vB", VecFP,
893 def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
894 "vrsqrtefp $vD, $vB", VecFP,
896 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
897 "vsubfp $vD, $vA, $vB", VecFP,
898 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
900 //===----------------------------------------------------------------------===//
901 // PowerPC Instruction Patterns
904 // Arbitrary immediate support. Implement in terms of LIS/ORI.
905 def : Pat<(i32 imm:$imm),
906 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
908 // Implement the 'not' operation with the NOR instruction.
909 def NOT : Pat<(not GPRC:$in),
910 (NOR GPRC:$in, GPRC:$in)>;
912 // ADD an arbitrary immediate.
913 def : Pat<(add GPRC:$in, imm:$imm),
914 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
915 // OR an arbitrary immediate.
916 def : Pat<(or GPRC:$in, imm:$imm),
917 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
918 // XOR an arbitrary immediate.
919 def : Pat<(xor GPRC:$in, imm:$imm),
920 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
921 def : Pat<(or (shl GPRC:$rS, GPRC:$rB),
922 (srl GPRC:$rS, (sub 32, GPRC:$rB))),
923 (RLWNM GPRC:$rS, GPRC:$rB, 0, 31)>;
925 def : Pat<(zext GPRC:$in),
926 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
927 def : Pat<(anyext GPRC:$in),
928 (OR4To8 GPRC:$in, GPRC:$in)>;
929 def : Pat<(trunc G8RC:$in),
930 (OR8To4 G8RC:$in, G8RC:$in)>;
933 def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
934 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
935 def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
936 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
938 def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
939 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
940 def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
941 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
943 // Hi and Lo for Darwin Global Addresses.
944 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS tglobaladdr:$in)>;
945 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI tglobaladdr:$in)>;
946 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
947 (ADDIS GPRC:$in, tglobaladdr:$g)>;
949 // Standard shifts. These are represented separately from the real shifts above
950 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
952 def : Pat<(sra GPRC:$rS, GPRC:$rB),
953 (SRAW GPRC:$rS, GPRC:$rB)>;
954 def : Pat<(srl GPRC:$rS, GPRC:$rB),
955 (SRW GPRC:$rS, GPRC:$rB)>;
956 def : Pat<(shl GPRC:$rS, GPRC:$rB),
957 (SLW GPRC:$rS, GPRC:$rB)>;
959 // Same as above, but using a temporary. FIXME: implement temporaries :)
961 def : Pattern<(xor GPRC:$in, imm:$imm),
962 [(set GPRC:$tmp, (XORI GPRC:$in, (LO16 imm:$imm))),
963 (XORIS GPRC:$tmp, (HI16 imm:$imm))]>;
966 //===----------------------------------------------------------------------===//
967 // PowerPCInstrInfo Definition
969 def PowerPCInstrInfo : InstrInfo {
972 let TSFlagsFields = [ "VMX", "PPC64" ];
973 let TSFlagsShifts = [ 0, 1 ];
975 let isLittleEndianEncoding = 1;