1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
18 #include "PPCRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33 // raw machine instructions.
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
36 /// always be the first one in the group.
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44 /// two dispatch pipes to be available to issue.
47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48 /// an instruction is issued to.
50 PPC970_Mask = 0x07 << PPC970_Shift
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 } // end namespace PPCII
67 class PPCInstrInfo : public PPCGenInstrInfo {
68 PPCSubtarget &Subtarget;
69 const PPCRegisterInfo RI;
71 bool StoreRegToStackSlot(MachineFunction &MF,
72 unsigned SrcReg, bool isKill, int FrameIdx,
73 const TargetRegisterClass *RC,
74 SmallVectorImpl<MachineInstr*> &NewMIs,
75 bool &NonRI, bool &SpillsVRS) const;
76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
77 unsigned DestReg, int FrameIdx,
78 const TargetRegisterClass *RC,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
80 bool &NonRI, bool &SpillsVRS) const;
81 virtual void anchor();
83 explicit PPCInstrInfo(PPCSubtarget &STI);
85 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
86 /// such, whenever a client has an instance of instruction info, it should
87 /// always be able to get register info as well (through this method).
89 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
91 ScheduleHazardRecognizer *
92 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
93 const ScheduleDAG *DAG) const override;
94 ScheduleHazardRecognizer *
95 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
96 const ScheduleDAG *DAG) const override;
98 unsigned getInstrLatency(const InstrItineraryData *ItinData,
99 const MachineInstr *MI,
100 unsigned *PredCost = nullptr) const override;
102 int getOperandLatency(const InstrItineraryData *ItinData,
103 const MachineInstr *DefMI, unsigned DefIdx,
104 const MachineInstr *UseMI,
105 unsigned UseIdx) const override;
106 int getOperandLatency(const InstrItineraryData *ItinData,
107 SDNode *DefNode, unsigned DefIdx,
108 SDNode *UseNode, unsigned UseIdx) const override {
109 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
113 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
114 const MachineInstr *DefMI,
115 unsigned DefIdx) const override {
116 // Machine LICM should hoist all instructions in low-register-pressure
117 // situations; none are sufficiently free to justify leaving in a loop
122 bool useMachineCombiner() const override {
126 /// Return true when there is potentially a faster code sequence
127 /// for an instruction chain ending in <Root>. All potential patterns are
128 /// output in the <Pattern> array.
129 bool getMachineCombinerPatterns(
131 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
133 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
135 bool isCoalescableExtInstr(const MachineInstr &MI,
136 unsigned &SrcReg, unsigned &DstReg,
137 unsigned &SubIdx) const override;
138 unsigned isLoadFromStackSlot(const MachineInstr *MI,
139 int &FrameIndex) const override;
140 unsigned isStoreToStackSlot(const MachineInstr *MI,
141 int &FrameIndex) const override;
143 // commuteInstruction - We can commute rlwimi instructions, but only if the
144 // rotate amt is zero. We also have to munge the immediates a bit.
145 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
147 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
148 unsigned &SrcOpIdx2) const override;
150 void insertNoop(MachineBasicBlock &MBB,
151 MachineBasicBlock::iterator MI) const override;
155 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
156 MachineBasicBlock *&FBB,
157 SmallVectorImpl<MachineOperand> &Cond,
158 bool AllowModify) const override;
159 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
160 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
161 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
162 DebugLoc DL) const override;
165 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
166 unsigned, unsigned, int &, int &, int &) const override;
167 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
168 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
169 unsigned TrueReg, unsigned FalseReg) const override;
171 void copyPhysReg(MachineBasicBlock &MBB,
172 MachineBasicBlock::iterator I, DebugLoc DL,
173 unsigned DestReg, unsigned SrcReg,
174 bool KillSrc) const override;
176 void storeRegToStackSlot(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator MBBI,
178 unsigned SrcReg, bool isKill, int FrameIndex,
179 const TargetRegisterClass *RC,
180 const TargetRegisterInfo *TRI) const override;
182 void loadRegFromStackSlot(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator MBBI,
184 unsigned DestReg, int FrameIndex,
185 const TargetRegisterClass *RC,
186 const TargetRegisterInfo *TRI) const override;
189 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
191 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
192 unsigned Reg, MachineRegisterInfo *MRI) const override;
194 // If conversion by predication (only supported by some branch instructions).
195 // All of the profitability checks always return true; it is always
196 // profitable to use the predicated branches.
197 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
198 unsigned NumCycles, unsigned ExtraPredCycles,
199 BranchProbability Probability) const override {
203 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
204 unsigned NumT, unsigned ExtraT,
205 MachineBasicBlock &FMBB,
206 unsigned NumF, unsigned ExtraF,
207 BranchProbability Probability) const override;
209 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
210 BranchProbability Probability) const override {
214 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
215 MachineBasicBlock &FMBB) const override {
219 // Predication support.
220 bool isPredicated(const MachineInstr *MI) const override;
222 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
224 bool PredicateInstruction(MachineInstr *MI,
225 ArrayRef<MachineOperand> Pred) const override;
227 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
228 ArrayRef<MachineOperand> Pred2) const override;
230 bool DefinesPredicate(MachineInstr *MI,
231 std::vector<MachineOperand> &Pred) const override;
233 bool isPredicable(MachineInstr *MI) const override;
235 // Comparison optimization.
238 bool analyzeCompare(const MachineInstr *MI,
239 unsigned &SrcReg, unsigned &SrcReg2,
240 int &Mask, int &Value) const override;
242 bool optimizeCompareInstr(MachineInstr *CmpInstr,
243 unsigned SrcReg, unsigned SrcReg2,
245 const MachineRegisterInfo *MRI) const override;
247 /// GetInstSize - Return the number of bytes of code the specified
248 /// instruction may be. This returns the maximum number of bytes.
250 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
252 void getNoopForMachoTarget(MCInst &NopInst) const override;
254 std::pair<unsigned, unsigned>
255 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
257 ArrayRef<std::pair<unsigned, const char *>>
258 getSerializableDirectMachineOperandTargetFlags() const override;
260 ArrayRef<std::pair<unsigned, const char *>>
261 getSerializableBitmaskMachineOperandTargetFlags() const override;