1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPC32_INSTRUCTIONINFO_H
15 #define POWERPC32_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "PPCRegisterInfo.h"
23 class PPCInstrInfo : public TargetInstrInfo {
24 const PPCRegisterInfo RI;
28 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
29 /// such, whenever a client has an instance of instruction info, it should
30 /// always be able to get register info as well (through this method).
32 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
35 // Return true if the instruction is a register to register move and
36 // leave the source and dest operands in the passed parameters.
38 virtual bool isMoveInstr(const MachineInstr& MI,
40 unsigned& destReg) const;
42 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
43 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
45 // commuteInstruction - We can commute rlwimi instructions, but only if the
46 // rotate amt is zero. We also have to munge the immediates a bit.
47 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
49 static unsigned invertPPCBranchOpcode(unsigned Opcode) {
51 default: assert(0 && "Unknown PPC branch opcode!");
52 case PPC::BEQ: return PPC::BNE;
53 case PPC::BNE: return PPC::BEQ;
54 case PPC::BLT: return PPC::BGE;
55 case PPC::BGE: return PPC::BLT;
56 case PPC::BGT: return PPC::BLE;
57 case PPC::BLE: return PPC::BGT;
58 case PPC::BNU: return PPC::BUN;
59 case PPC::BUN: return PPC::BNU;