1 //===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef POWERPC32_INSTRUCTIONINFO_H
15 #define POWERPC32_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "PPCRegisterInfo.h"
23 /// PPCII - This namespace holds all of the PowerPC target-specific
24 /// per-instruction flags. These must match the corresponding definitions in
25 /// PPC.td and PPCInstrFormats.td.
28 // PPC970 Instruction Flags. These flags describe the characteristics of the
29 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
30 // raw machine instructions.
32 /// PPC970_First - This instruction starts a new dispatch group, so it will
33 /// always be the first one in the group.
36 /// PPC970_Single - This instruction starts a new dispatch group and
37 /// terminates it, so it will be the sole instruction in the group.
40 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
41 /// two dispatch pipes to be available to issue.
44 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
45 /// an instruction is issued to.
47 PPC970_Mask = 0x07 << PPC970_Shift
50 /// These are the various PPC970 execution unit pipelines. Each instruction
52 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
53 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
54 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
55 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
56 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
57 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
58 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
59 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 class PPCInstrInfo : public TargetInstrInfoImpl {
66 const PPCRegisterInfo RI;
68 PPCInstrInfo(PPCTargetMachine &TM);
70 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
71 /// such, whenever a client has an instance of instruction info, it should
72 /// always be able to get register info as well (through this method).
74 virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
76 /// getPointerRegClass - Return the register class to use to hold pointers.
77 /// This is used for addressing modes.
78 virtual const TargetRegisterClass *getPointerRegClass() const;
80 // Return true if the instruction is a register to register move and
81 // leave the source and dest operands in the passed parameters.
83 virtual bool isMoveInstr(const MachineInstr& MI,
85 unsigned& destReg) const;
87 unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
88 unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
90 // commuteInstruction - We can commute rlwimi instructions, but only if the
91 // rotate amt is zero. We also have to munge the immediates a bit.
92 virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
94 virtual void insertNoop(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MI) const;
99 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
100 MachineBasicBlock *&FBB,
101 std::vector<MachineOperand> &Cond) const;
102 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
103 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
104 MachineBasicBlock *FBB,
105 const std::vector<MachineOperand> &Cond) const;
106 virtual void copyRegToReg(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MI,
108 unsigned DestReg, unsigned SrcReg,
109 const TargetRegisterClass *DestRC,
110 const TargetRegisterClass *SrcRC) const;
112 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MBBI,
114 unsigned SrcReg, bool isKill, int FrameIndex,
115 const TargetRegisterClass *RC) const;
117 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
118 SmallVectorImpl<MachineOperand> &Addr,
119 const TargetRegisterClass *RC,
120 SmallVectorImpl<MachineInstr*> &NewMIs) const;
122 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator MBBI,
124 unsigned DestReg, int FrameIndex,
125 const TargetRegisterClass *RC) const;
127 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
128 SmallVectorImpl<MachineOperand> &Addr,
129 const TargetRegisterClass *RC,
130 SmallVectorImpl<MachineInstr*> &NewMIs) const;
132 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
133 /// copy instructions, turning them into load/store instructions.
134 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
136 SmallVectorImpl<unsigned> &Ops,
137 int FrameIndex) const;
139 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
141 SmallVectorImpl<unsigned> &Ops,
142 MachineInstr* LoadMI) const {
146 virtual bool canFoldMemoryOperand(MachineInstr *MI,
147 SmallVectorImpl<unsigned> &Ops) const;
149 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
150 virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;