1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
18 #include "PPCRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "PPCGenInstrInfo.inc"
26 /// PPCII - This namespace holds all of the PowerPC target-specific
27 /// per-instruction flags. These must match the corresponding definitions in
28 /// PPC.td and PPCInstrFormats.td.
31 // PPC970 Instruction Flags. These flags describe the characteristics of the
32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of
33 // raw machine instructions.
35 /// PPC970_First - This instruction starts a new dispatch group, so it will
36 /// always be the first one in the group.
39 /// PPC970_Single - This instruction starts a new dispatch group and
40 /// terminates it, so it will be the sole instruction in the group.
43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring
44 /// two dispatch pipes to be available to issue.
47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that
48 /// an instruction is issued to.
50 PPC970_Mask = 0x07 << PPC970_Shift
53 /// These are the various PPC970 execution unit pipelines. Each instruction
55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction
56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit
57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit
58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit
59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit
60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU
61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit
62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit
64 } // end namespace PPCII
66 namespace MachineCombinerPattern {
67 enum MC_PATTERN : int {
68 // These are commutative variants for reassociating a computation chain
77 } // end namespace MachineCombinerPattern
80 class PPCInstrInfo : public PPCGenInstrInfo {
81 PPCSubtarget &Subtarget;
82 const PPCRegisterInfo RI;
84 bool StoreRegToStackSlot(MachineFunction &MF,
85 unsigned SrcReg, bool isKill, int FrameIdx,
86 const TargetRegisterClass *RC,
87 SmallVectorImpl<MachineInstr*> &NewMIs,
88 bool &NonRI, bool &SpillsVRS) const;
89 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
90 unsigned DestReg, int FrameIdx,
91 const TargetRegisterClass *RC,
92 SmallVectorImpl<MachineInstr*> &NewMIs,
93 bool &NonRI, bool &SpillsVRS) const;
94 virtual void anchor();
96 explicit PPCInstrInfo(PPCSubtarget &STI);
98 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
99 /// such, whenever a client has an instance of instruction info, it should
100 /// always be able to get register info as well (through this method).
102 const PPCRegisterInfo &getRegisterInfo() const { return RI; }
104 ScheduleHazardRecognizer *
105 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
106 const ScheduleDAG *DAG) const override;
107 ScheduleHazardRecognizer *
108 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
109 const ScheduleDAG *DAG) const override;
111 unsigned getInstrLatency(const InstrItineraryData *ItinData,
112 const MachineInstr *MI,
113 unsigned *PredCost = nullptr) const override;
115 int getOperandLatency(const InstrItineraryData *ItinData,
116 const MachineInstr *DefMI, unsigned DefIdx,
117 const MachineInstr *UseMI,
118 unsigned UseIdx) const override;
119 int getOperandLatency(const InstrItineraryData *ItinData,
120 SDNode *DefNode, unsigned DefIdx,
121 SDNode *UseNode, unsigned UseIdx) const override {
122 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx,
126 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
127 const MachineInstr *DefMI,
128 unsigned DefIdx) const override {
129 // Machine LICM should hoist all instructions in low-register-pressure
130 // situations; none are sufficiently free to justify leaving in a loop
135 bool useMachineCombiner() const override {
139 /// Return true when there is potentially a faster code sequence
140 /// for an instruction chain ending in <Root>. All potential patterns are
141 /// output in the <Pattern> array.
142 bool getMachineCombinerPatterns(
144 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
146 /// When getMachineCombinerPatterns() finds a pattern, this function generates
147 /// the instructions that could replace the original code sequence.
148 void genAlternativeCodeSequence(
149 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
150 SmallVectorImpl<MachineInstr *> &InsInstrs,
151 SmallVectorImpl<MachineInstr *> &DelInstrs,
152 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
154 bool isCoalescableExtInstr(const MachineInstr &MI,
155 unsigned &SrcReg, unsigned &DstReg,
156 unsigned &SubIdx) const override;
157 unsigned isLoadFromStackSlot(const MachineInstr *MI,
158 int &FrameIndex) const override;
159 unsigned isStoreToStackSlot(const MachineInstr *MI,
160 int &FrameIndex) const override;
162 // commuteInstruction - We can commute rlwimi instructions, but only if the
163 // rotate amt is zero. We also have to munge the immediates a bit.
164 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
166 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
167 unsigned &SrcOpIdx2) const override;
169 void insertNoop(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI) const override;
174 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
175 MachineBasicBlock *&FBB,
176 SmallVectorImpl<MachineOperand> &Cond,
177 bool AllowModify) const override;
178 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
179 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
180 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
181 DebugLoc DL) const override;
184 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
185 unsigned, unsigned, int &, int &, int &) const override;
186 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
187 DebugLoc DL, unsigned DstReg, ArrayRef<MachineOperand> Cond,
188 unsigned TrueReg, unsigned FalseReg) const override;
190 void copyPhysReg(MachineBasicBlock &MBB,
191 MachineBasicBlock::iterator I, DebugLoc DL,
192 unsigned DestReg, unsigned SrcReg,
193 bool KillSrc) const override;
195 void storeRegToStackSlot(MachineBasicBlock &MBB,
196 MachineBasicBlock::iterator MBBI,
197 unsigned SrcReg, bool isKill, int FrameIndex,
198 const TargetRegisterClass *RC,
199 const TargetRegisterInfo *TRI) const override;
201 void loadRegFromStackSlot(MachineBasicBlock &MBB,
202 MachineBasicBlock::iterator MBBI,
203 unsigned DestReg, int FrameIndex,
204 const TargetRegisterClass *RC,
205 const TargetRegisterInfo *TRI) const override;
208 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
210 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
211 unsigned Reg, MachineRegisterInfo *MRI) const override;
213 // If conversion by predication (only supported by some branch instructions).
214 // All of the profitability checks always return true; it is always
215 // profitable to use the predicated branches.
216 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
217 unsigned NumCycles, unsigned ExtraPredCycles,
218 const BranchProbability &Probability) const override {
222 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
223 unsigned NumT, unsigned ExtraT,
224 MachineBasicBlock &FMBB,
225 unsigned NumF, unsigned ExtraF,
226 const BranchProbability &Probability) const override;
228 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
230 const BranchProbability
231 &Probability) const override {
235 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
236 MachineBasicBlock &FMBB) const override {
240 // Predication support.
241 bool isPredicated(const MachineInstr *MI) const override;
243 bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
245 bool PredicateInstruction(MachineInstr *MI,
246 ArrayRef<MachineOperand> Pred) const override;
248 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
249 ArrayRef<MachineOperand> Pred2) const override;
251 bool DefinesPredicate(MachineInstr *MI,
252 std::vector<MachineOperand> &Pred) const override;
254 bool isPredicable(MachineInstr *MI) const override;
256 // Comparison optimization.
259 bool analyzeCompare(const MachineInstr *MI,
260 unsigned &SrcReg, unsigned &SrcReg2,
261 int &Mask, int &Value) const override;
263 bool optimizeCompareInstr(MachineInstr *CmpInstr,
264 unsigned SrcReg, unsigned SrcReg2,
266 const MachineRegisterInfo *MRI) const override;
268 /// GetInstSize - Return the number of bytes of code the specified
269 /// instruction may be. This returns the maximum number of bytes.
271 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
273 void getNoopForMachoTarget(MCInst &NopInst) const override;
275 std::pair<unsigned, unsigned>
276 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
278 ArrayRef<std::pair<unsigned, const char *>>
279 getSerializableDirectMachineOperandTargetFlags() const override;
281 ArrayRef<std::pair<unsigned, const char *>>
282 getSerializableBitmaskMachineOperandTargetFlags() const override;