1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCPredicates.h"
17 #include "PPCGenInstrInfo.inc"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
24 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
25 RI(*TM.getSubtargetImpl(), *this) {}
27 /// getPointerRegClass - Return the register class to use to hold pointers.
28 /// This is used for addressing modes.
29 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
30 if (TM.getSubtargetImpl()->isPPC64())
31 return &PPC::G8RCRegClass;
33 return &PPC::GPRCRegClass;
37 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
39 unsigned& destReg) const {
40 unsigned oc = MI.getOpcode();
41 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
43 assert(MI.getNumOperands() >= 3 &&
44 MI.getOperand(0).isRegister() &&
45 MI.getOperand(1).isRegister() &&
46 MI.getOperand(2).isRegister() &&
47 "invalid PPC OR instruction!");
48 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49 sourceReg = MI.getOperand(1).getReg();
50 destReg = MI.getOperand(0).getReg();
53 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
54 assert(MI.getNumOperands() >= 3 &&
55 MI.getOperand(0).isRegister() &&
56 MI.getOperand(2).isImmediate() &&
57 "invalid PPC ADDI instruction!");
58 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
59 sourceReg = MI.getOperand(1).getReg();
60 destReg = MI.getOperand(0).getReg();
63 } else if (oc == PPC::ORI) { // ori r1, r2, 0
64 assert(MI.getNumOperands() >= 3 &&
65 MI.getOperand(0).isRegister() &&
66 MI.getOperand(1).isRegister() &&
67 MI.getOperand(2).isImmediate() &&
68 "invalid PPC ORI instruction!");
69 if (MI.getOperand(2).getImm() == 0) {
70 sourceReg = MI.getOperand(1).getReg();
71 destReg = MI.getOperand(0).getReg();
74 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75 oc == PPC::FMRSD) { // fmr r1, r2
76 assert(MI.getNumOperands() >= 2 &&
77 MI.getOperand(0).isRegister() &&
78 MI.getOperand(1).isRegister() &&
79 "invalid PPC FMR instruction");
80 sourceReg = MI.getOperand(1).getReg();
81 destReg = MI.getOperand(0).getReg();
83 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
84 assert(MI.getNumOperands() >= 2 &&
85 MI.getOperand(0).isRegister() &&
86 MI.getOperand(1).isRegister() &&
87 "invalid PPC MCRF instruction");
88 sourceReg = MI.getOperand(1).getReg();
89 destReg = MI.getOperand(0).getReg();
95 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
113 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
114 int &FrameIndex) const {
115 switch (MI->getOpcode()) {
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI()) {
123 FrameIndex = MI->getOperand(2).getIndex();
124 return MI->getOperand(0).getReg();
131 // commuteInstruction - We can commute rlwimi instructions, but only if the
132 // rotate amt is zero. We also have to munge the immediates a bit.
133 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
134 // Normal instructions can be commuted the obvious way.
135 if (MI->getOpcode() != PPC::RLWIMI)
136 return TargetInstrInfoImpl::commuteInstruction(MI);
138 // Cannot commute if it has a non-zero rotate count.
139 if (MI->getOperand(3).getImm() != 0)
142 // If we have a zero rotate count, we have:
144 // Op0 = (Op1 & ~M) | (Op2 & M)
146 // M = mask((ME+1)&31, (MB-1)&31)
147 // Op0 = (Op2 & ~M) | (Op1 & M)
150 unsigned Reg1 = MI->getOperand(1).getReg();
151 unsigned Reg2 = MI->getOperand(2).getReg();
152 bool Reg1IsKill = MI->getOperand(1).isKill();
153 bool Reg2IsKill = MI->getOperand(2).isKill();
154 MI->getOperand(2).setReg(Reg1);
155 MI->getOperand(1).setReg(Reg2);
156 MI->getOperand(2).setIsKill(Reg1IsKill);
157 MI->getOperand(1).setIsKill(Reg2IsKill);
159 // Swap the mask around.
160 unsigned MB = MI->getOperand(4).getImm();
161 unsigned ME = MI->getOperand(5).getImm();
162 MI->getOperand(4).setImm((ME+1) & 31);
163 MI->getOperand(5).setImm((MB-1) & 31);
167 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
168 MachineBasicBlock::iterator MI) const {
169 BuildMI(MBB, MI, get(PPC::NOP));
174 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
175 MachineBasicBlock *&FBB,
176 std::vector<MachineOperand> &Cond) const {
177 // If the block has no terminators, it just falls into the block after it.
178 MachineBasicBlock::iterator I = MBB.end();
179 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
182 // Get the last instruction in the block.
183 MachineInstr *LastInst = I;
185 // If there is only one terminator instruction, process it.
186 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
187 if (LastInst->getOpcode() == PPC::B) {
188 TBB = LastInst->getOperand(0).getMBB();
190 } else if (LastInst->getOpcode() == PPC::BCC) {
191 // Block ends with fall-through condbranch.
192 TBB = LastInst->getOperand(2).getMBB();
193 Cond.push_back(LastInst->getOperand(0));
194 Cond.push_back(LastInst->getOperand(1));
197 // Otherwise, don't know what this is.
201 // Get the instruction before it if it's a terminator.
202 MachineInstr *SecondLastInst = I;
204 // If there are three terminators, we don't know what sort of block this is.
205 if (SecondLastInst && I != MBB.begin() &&
206 isUnpredicatedTerminator(--I))
209 // If the block ends with PPC::B and PPC:BCC, handle it.
210 if (SecondLastInst->getOpcode() == PPC::BCC &&
211 LastInst->getOpcode() == PPC::B) {
212 TBB = SecondLastInst->getOperand(2).getMBB();
213 Cond.push_back(SecondLastInst->getOperand(0));
214 Cond.push_back(SecondLastInst->getOperand(1));
215 FBB = LastInst->getOperand(0).getMBB();
219 // If the block ends with two PPC:Bs, handle it. The second one is not
220 // executed, so remove it.
221 if (SecondLastInst->getOpcode() == PPC::B &&
222 LastInst->getOpcode() == PPC::B) {
223 TBB = SecondLastInst->getOperand(0).getMBB();
225 I->eraseFromParent();
229 // Otherwise, can't handle this.
233 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
234 MachineBasicBlock::iterator I = MBB.end();
235 if (I == MBB.begin()) return 0;
237 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
240 // Remove the branch.
241 I->eraseFromParent();
245 if (I == MBB.begin()) return 1;
247 if (I->getOpcode() != PPC::BCC)
250 // Remove the branch.
251 I->eraseFromParent();
256 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
257 MachineBasicBlock *FBB,
258 const std::vector<MachineOperand> &Cond) const {
259 // Shouldn't be a fall through.
260 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
261 assert((Cond.size() == 2 || Cond.size() == 0) &&
262 "PPC branch conditions have two components!");
266 if (Cond.empty()) // Unconditional branch
267 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
268 else // Conditional branch
269 BuildMI(&MBB, get(PPC::BCC))
270 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
274 // Two-way Conditional Branch.
275 BuildMI(&MBB, get(PPC::BCC))
276 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
277 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
281 void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator MI,
283 unsigned DestReg, unsigned SrcReg,
284 const TargetRegisterClass *DestRC,
285 const TargetRegisterClass *SrcRC) const {
286 if (DestRC != SrcRC) {
287 cerr << "Not yet supported!";
291 if (DestRC == PPC::GPRCRegisterClass) {
292 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
293 } else if (DestRC == PPC::G8RCRegisterClass) {
294 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
295 } else if (DestRC == PPC::F4RCRegisterClass) {
296 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
297 } else if (DestRC == PPC::F8RCRegisterClass) {
298 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
299 } else if (DestRC == PPC::CRRCRegisterClass) {
300 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
301 } else if (DestRC == PPC::VRRCRegisterClass) {
302 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
304 cerr << "Attempt to copy register that is not GPR or FPR";
309 static void StoreRegToStackSlot(const TargetInstrInfo &TII,
310 unsigned SrcReg, bool isKill, int FrameIdx,
311 const TargetRegisterClass *RC,
312 SmallVectorImpl<MachineInstr*> &NewMIs) {
313 if (RC == PPC::GPRCRegisterClass) {
314 if (SrcReg != PPC::LR) {
315 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
316 .addReg(SrcReg, false, false, isKill), FrameIdx));
318 // FIXME: this spills LR immediately to memory in one step. To do this,
319 // we use R11, which we know cannot be used in the prolog/epilog. This is
321 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
322 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
323 .addReg(PPC::R11, false, false, isKill), FrameIdx));
325 } else if (RC == PPC::G8RCRegisterClass) {
326 if (SrcReg != PPC::LR8) {
327 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
328 .addReg(SrcReg, false, false, isKill), FrameIdx));
330 // FIXME: this spills LR immediately to memory in one step. To do this,
331 // we use R11, which we know cannot be used in the prolog/epilog. This is
333 NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
334 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
335 .addReg(PPC::X11, false, false, isKill), FrameIdx));
337 } else if (RC == PPC::F8RCRegisterClass) {
338 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
339 .addReg(SrcReg, false, false, isKill), FrameIdx));
340 } else if (RC == PPC::F4RCRegisterClass) {
341 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
342 .addReg(SrcReg, false, false, isKill), FrameIdx));
343 } else if (RC == PPC::CRRCRegisterClass) {
344 // FIXME: We use R0 here, because it isn't available for RA.
345 // We need to store the CR in the low 4-bits of the saved value. First,
346 // issue a MFCR to save all of the CRBits.
347 NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
349 // If the saved register wasn't CR0, shift the bits left so that they are in
351 if (SrcReg != PPC::CR0) {
352 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
353 // rlwinm r0, r0, ShiftBits, 0, 31.
354 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
355 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
358 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
359 .addReg(PPC::R0, false, false, isKill), FrameIdx));
360 } else if (RC == PPC::VRRCRegisterClass) {
361 // We don't have indexed addressing for vector loads. Emit:
365 // FIXME: We use R0 here, because it isn't available for RA.
366 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
368 NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
369 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
371 assert(0 && "Unknown regclass!");
377 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator MI,
379 unsigned SrcReg, bool isKill, int FrameIdx,
380 const TargetRegisterClass *RC) const {
381 SmallVector<MachineInstr*, 4> NewMIs;
382 StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs);
383 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
384 MBB.insert(MI, NewMIs[i]);
387 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
389 SmallVectorImpl<MachineOperand> &Addr,
390 const TargetRegisterClass *RC,
391 SmallVectorImpl<MachineInstr*> &NewMIs) const {
392 if (Addr[0].isFrameIndex()) {
393 StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
398 if (RC == PPC::GPRCRegisterClass) {
400 } else if (RC == PPC::G8RCRegisterClass) {
402 } else if (RC == PPC::F8RCRegisterClass) {
404 } else if (RC == PPC::F4RCRegisterClass) {
406 } else if (RC == PPC::VRRCRegisterClass) {
409 assert(0 && "Unknown regclass!");
412 MachineInstrBuilder MIB = BuildMI(get(Opc))
413 .addReg(SrcReg, false, false, isKill);
414 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
415 MachineOperand &MO = Addr[i];
417 MIB.addReg(MO.getReg());
418 else if (MO.isImmediate())
419 MIB.addImm(MO.getImm());
421 MIB.addFrameIndex(MO.getIndex());
423 NewMIs.push_back(MIB);
427 static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
428 unsigned DestReg, int FrameIdx,
429 const TargetRegisterClass *RC,
430 SmallVectorImpl<MachineInstr*> &NewMIs) {
431 if (RC == PPC::GPRCRegisterClass) {
432 if (DestReg != PPC::LR) {
433 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
436 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
438 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
440 } else if (RC == PPC::G8RCRegisterClass) {
441 if (DestReg != PPC::LR8) {
442 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
445 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
447 NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
449 } else if (RC == PPC::F8RCRegisterClass) {
450 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
452 } else if (RC == PPC::F4RCRegisterClass) {
453 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
455 } else if (RC == PPC::CRRCRegisterClass) {
456 // FIXME: We use R0 here, because it isn't available for RA.
457 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
460 // If the reloaded register isn't CR0, shift the bits right so that they are
461 // in the right CR's slot.
462 if (DestReg != PPC::CR0) {
463 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
464 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
465 NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
466 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
469 NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
470 } else if (RC == PPC::VRRCRegisterClass) {
471 // We don't have indexed addressing for vector loads. Emit:
475 // FIXME: We use R0 here, because it isn't available for RA.
476 NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
478 NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
481 assert(0 && "Unknown regclass!");
487 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator MI,
489 unsigned DestReg, int FrameIdx,
490 const TargetRegisterClass *RC) const {
491 SmallVector<MachineInstr*, 4> NewMIs;
492 LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs);
493 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
494 MBB.insert(MI, NewMIs[i]);
497 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
498 SmallVectorImpl<MachineOperand> &Addr,
499 const TargetRegisterClass *RC,
500 SmallVectorImpl<MachineInstr*> &NewMIs) const{
501 if (Addr[0].isFrameIndex()) {
502 LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs);
507 if (RC == PPC::GPRCRegisterClass) {
508 assert(DestReg != PPC::LR && "Can't handle this yet!");
510 } else if (RC == PPC::G8RCRegisterClass) {
511 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
513 } else if (RC == PPC::F8RCRegisterClass) {
515 } else if (RC == PPC::F4RCRegisterClass) {
517 } else if (RC == PPC::VRRCRegisterClass) {
520 assert(0 && "Unknown regclass!");
523 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
524 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
525 MachineOperand &MO = Addr[i];
527 MIB.addReg(MO.getReg());
528 else if (MO.isImmediate())
529 MIB.addImm(MO.getImm());
531 MIB.addFrameIndex(MO.getIndex());
533 NewMIs.push_back(MIB);
537 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
538 /// copy instructions, turning them into load/store instructions.
539 MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineInstr *MI,
540 SmallVectorImpl<unsigned> &Ops,
541 int FrameIndex) const {
542 if (Ops.size() != 1) return NULL;
544 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
545 // it takes more than one instruction to store it.
546 unsigned Opc = MI->getOpcode();
547 unsigned OpNum = Ops[0];
549 MachineInstr *NewMI = NULL;
550 if ((Opc == PPC::OR &&
551 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
552 if (OpNum == 0) { // move -> store
553 unsigned InReg = MI->getOperand(1).getReg();
554 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
556 } else { // move -> load
557 unsigned OutReg = MI->getOperand(0).getReg();
558 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
561 } else if ((Opc == PPC::OR8 &&
562 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
563 if (OpNum == 0) { // move -> store
564 unsigned InReg = MI->getOperand(1).getReg();
565 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
567 } else { // move -> load
568 unsigned OutReg = MI->getOperand(0).getReg();
569 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
571 } else if (Opc == PPC::FMRD) {
572 if (OpNum == 0) { // move -> store
573 unsigned InReg = MI->getOperand(1).getReg();
574 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
576 } else { // move -> load
577 unsigned OutReg = MI->getOperand(0).getReg();
578 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
580 } else if (Opc == PPC::FMRS) {
581 if (OpNum == 0) { // move -> store
582 unsigned InReg = MI->getOperand(1).getReg();
583 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
585 } else { // move -> load
586 unsigned OutReg = MI->getOperand(0).getReg();
587 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
592 NewMI->copyKillDeadInfo(MI);
596 bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
597 SmallVectorImpl<unsigned> &Ops) const {
598 if (Ops.size() != 1) return false;
600 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
601 // it takes more than one instruction to store it.
602 unsigned Opc = MI->getOpcode();
604 if ((Opc == PPC::OR &&
605 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
607 else if ((Opc == PPC::OR8 &&
608 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
610 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
617 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
618 if (MBB.empty()) return false;
620 switch (MBB.back().getOpcode()) {
621 case PPC::BLR: // Return.
622 case PPC::B: // Uncond branch.
623 case PPC::BCTR: // Indirect branch.
625 default: return false;
630 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
631 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
632 // Leave the CR# the same, but invert the condition.
633 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));