1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCGenInstrInfo.inc"
16 #include "PPCTargetMachine.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
22 : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm) {}
24 /// getPointerRegClass - Return the register class to use to hold pointers.
25 /// This is used for addressing modes.
26 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
27 if (TM.getSubtargetImpl()->isPPC64())
28 return &PPC::G8RCRegClass;
30 return &PPC::GPRCRegClass;
34 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
36 unsigned& destReg) const {
37 MachineOpCode oc = MI.getOpcode();
38 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
39 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
40 assert(MI.getNumOperands() == 3 &&
41 MI.getOperand(0).isRegister() &&
42 MI.getOperand(1).isRegister() &&
43 MI.getOperand(2).isRegister() &&
44 "invalid PPC OR instruction!");
45 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
46 sourceReg = MI.getOperand(1).getReg();
47 destReg = MI.getOperand(0).getReg();
50 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
51 assert(MI.getNumOperands() == 3 &&
52 MI.getOperand(0).isRegister() &&
53 MI.getOperand(2).isImmediate() &&
54 "invalid PPC ADDI instruction!");
55 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
56 sourceReg = MI.getOperand(1).getReg();
57 destReg = MI.getOperand(0).getReg();
60 } else if (oc == PPC::ORI) { // ori r1, r2, 0
61 assert(MI.getNumOperands() == 3 &&
62 MI.getOperand(0).isRegister() &&
63 MI.getOperand(1).isRegister() &&
64 MI.getOperand(2).isImmediate() &&
65 "invalid PPC ORI instruction!");
66 if (MI.getOperand(2).getImmedValue()==0) {
67 sourceReg = MI.getOperand(1).getReg();
68 destReg = MI.getOperand(0).getReg();
71 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
72 oc == PPC::FMRSD) { // fmr r1, r2
73 assert(MI.getNumOperands() == 2 &&
74 MI.getOperand(0).isRegister() &&
75 MI.getOperand(1).isRegister() &&
76 "invalid PPC FMR instruction");
77 sourceReg = MI.getOperand(1).getReg();
78 destReg = MI.getOperand(0).getReg();
80 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
81 assert(MI.getNumOperands() == 2 &&
82 MI.getOperand(0).isRegister() &&
83 MI.getOperand(1).isRegister() &&
84 "invalid PPC MCRF instruction");
85 sourceReg = MI.getOperand(1).getReg();
86 destReg = MI.getOperand(0).getReg();
92 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
93 int &FrameIndex) const {
94 switch (MI->getOpcode()) {
100 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
101 MI->getOperand(2).isFrameIndex()) {
102 FrameIndex = MI->getOperand(2).getFrameIndex();
103 return MI->getOperand(0).getReg();
110 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
111 int &FrameIndex) const {
112 switch (MI->getOpcode()) {
118 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
119 MI->getOperand(2).isFrameIndex()) {
120 FrameIndex = MI->getOperand(2).getFrameIndex();
121 return MI->getOperand(0).getReg();
128 // commuteInstruction - We can commute rlwimi instructions, but only if the
129 // rotate amt is zero. We also have to munge the immediates a bit.
130 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
131 // Normal instructions can be commuted the obvious way.
132 if (MI->getOpcode() != PPC::RLWIMI)
133 return TargetInstrInfo::commuteInstruction(MI);
135 // Cannot commute if it has a non-zero rotate count.
136 if (MI->getOperand(3).getImmedValue() != 0)
139 // If we have a zero rotate count, we have:
141 // Op0 = (Op1 & ~M) | (Op2 & M)
143 // M = mask((ME+1)&31, (MB-1)&31)
144 // Op0 = (Op2 & ~M) | (Op1 & M)
147 unsigned Reg1 = MI->getOperand(1).getReg();
148 unsigned Reg2 = MI->getOperand(2).getReg();
149 MI->getOperand(2).setReg(Reg1);
150 MI->getOperand(1).setReg(Reg2);
152 // Swap the mask around.
153 unsigned MB = MI->getOperand(4).getImmedValue();
154 unsigned ME = MI->getOperand(5).getImmedValue();
155 MI->getOperand(4).setImmedValue((ME+1) & 31);
156 MI->getOperand(5).setImmedValue((MB-1) & 31);
160 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
161 MachineBasicBlock::iterator MI) const {
162 BuildMI(MBB, MI, PPC::NOP, 0);