1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
33 #define GET_INSTRINFO_CTOR
34 #include "PPCGenInstrInfo.inc"
39 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
40 cl::desc("Disable analysis for CTR loops"));
42 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
43 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
44 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
46 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
47 /// this target when scheduling the DAG.
48 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
49 const TargetMachine *TM,
50 const ScheduleDAG *DAG) const {
51 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
52 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
53 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
54 const InstrItineraryData *II = TM->getInstrItineraryData();
55 return new PPCScoreboardHazardRecognizer(II, DAG);
58 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
61 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
62 /// to use for this target when scheduling the DAG.
63 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
64 const InstrItineraryData *II,
65 const ScheduleDAG *DAG) const {
66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
68 // Most subtargets use a PPC970 recognizer.
69 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
70 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
71 const TargetInstrInfo *TII = TM.getInstrInfo();
72 assert(TII && "No InstrInfo?");
74 return new PPCHazardRecognizer970(*TII);
77 return new PPCScoreboardHazardRecognizer(II, DAG);
80 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
81 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
82 unsigned &SrcReg, unsigned &DstReg,
83 unsigned &SubIdx) const {
84 switch (MI.getOpcode()) {
85 default: return false;
87 case PPC::EXTSW_32_64:
88 SrcReg = MI.getOperand(1).getReg();
89 DstReg = MI.getOperand(0).getReg();
95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
113 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114 int &FrameIndex) const {
115 switch (MI->getOpcode()) {
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI()) {
123 FrameIndex = MI->getOperand(2).getIndex();
124 return MI->getOperand(0).getReg();
131 // commuteInstruction - We can commute rlwimi instructions, but only if the
132 // rotate amt is zero. We also have to munge the immediates a bit.
134 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135 MachineFunction &MF = *MI->getParent()->getParent();
137 // Normal instructions can be commuted the obvious way.
138 if (MI->getOpcode() != PPC::RLWIMI)
139 return TargetInstrInfo::commuteInstruction(MI, NewMI);
141 // Cannot commute if it has a non-zero rotate count.
142 if (MI->getOperand(3).getImm() != 0)
145 // If we have a zero rotate count, we have:
147 // Op0 = (Op1 & ~M) | (Op2 & M)
149 // M = mask((ME+1)&31, (MB-1)&31)
150 // Op0 = (Op2 & ~M) | (Op1 & M)
153 unsigned Reg0 = MI->getOperand(0).getReg();
154 unsigned Reg1 = MI->getOperand(1).getReg();
155 unsigned Reg2 = MI->getOperand(2).getReg();
156 bool Reg1IsKill = MI->getOperand(1).isKill();
157 bool Reg2IsKill = MI->getOperand(2).isKill();
158 bool ChangeReg0 = false;
159 // If machine instrs are no longer in two-address forms, update
160 // destination register as well.
162 // Must be two address instruction!
163 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
164 "Expecting a two-address instruction!");
170 unsigned MB = MI->getOperand(4).getImm();
171 unsigned ME = MI->getOperand(5).getImm();
174 // Create a new instruction.
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176 bool Reg0IsDead = MI->getOperand(0).isDead();
177 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
179 .addReg(Reg2, getKillRegState(Reg2IsKill))
180 .addReg(Reg1, getKillRegState(Reg1IsKill))
182 .addImm((MB-1) & 31);
186 MI->getOperand(0).setReg(Reg2);
187 MI->getOperand(2).setReg(Reg1);
188 MI->getOperand(1).setReg(Reg2);
189 MI->getOperand(2).setIsKill(Reg1IsKill);
190 MI->getOperand(1).setIsKill(Reg2IsKill);
192 // Swap the mask around.
193 MI->getOperand(4).setImm((ME+1) & 31);
194 MI->getOperand(5).setImm((MB-1) & 31);
198 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator MI) const {
201 BuildMI(MBB, MI, DL, get(PPC::NOP));
206 // Note: If the condition register is set to CTR or CTR8 then this is a
207 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
208 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209 MachineBasicBlock *&FBB,
210 SmallVectorImpl<MachineOperand> &Cond,
211 bool AllowModify) const {
212 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
214 // If the block has no terminators, it just falls into the block after it.
215 MachineBasicBlock::iterator I = MBB.end();
216 if (I == MBB.begin())
219 while (I->isDebugValue()) {
220 if (I == MBB.begin())
224 if (!isUnpredicatedTerminator(I))
227 // Get the last instruction in the block.
228 MachineInstr *LastInst = I;
230 // If there is only one terminator instruction, process it.
231 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
232 if (LastInst->getOpcode() == PPC::B) {
233 if (!LastInst->getOperand(0).isMBB())
235 TBB = LastInst->getOperand(0).getMBB();
237 } else if (LastInst->getOpcode() == PPC::BCC) {
238 if (!LastInst->getOperand(2).isMBB())
240 // Block ends with fall-through condbranch.
241 TBB = LastInst->getOperand(2).getMBB();
242 Cond.push_back(LastInst->getOperand(0));
243 Cond.push_back(LastInst->getOperand(1));
245 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
246 LastInst->getOpcode() == PPC::BDNZ) {
247 if (!LastInst->getOperand(0).isMBB())
249 if (DisableCTRLoopAnal)
251 TBB = LastInst->getOperand(0).getMBB();
252 Cond.push_back(MachineOperand::CreateImm(1));
253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
256 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
257 LastInst->getOpcode() == PPC::BDZ) {
258 if (!LastInst->getOperand(0).isMBB())
260 if (DisableCTRLoopAnal)
262 TBB = LastInst->getOperand(0).getMBB();
263 Cond.push_back(MachineOperand::CreateImm(0));
264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
269 // Otherwise, don't know what this is.
273 // Get the instruction before it if it's a terminator.
274 MachineInstr *SecondLastInst = I;
276 // If there are three terminators, we don't know what sort of block this is.
277 if (SecondLastInst && I != MBB.begin() &&
278 isUnpredicatedTerminator(--I))
281 // If the block ends with PPC::B and PPC:BCC, handle it.
282 if (SecondLastInst->getOpcode() == PPC::BCC &&
283 LastInst->getOpcode() == PPC::B) {
284 if (!SecondLastInst->getOperand(2).isMBB() ||
285 !LastInst->getOperand(0).isMBB())
287 TBB = SecondLastInst->getOperand(2).getMBB();
288 Cond.push_back(SecondLastInst->getOperand(0));
289 Cond.push_back(SecondLastInst->getOperand(1));
290 FBB = LastInst->getOperand(0).getMBB();
292 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
293 SecondLastInst->getOpcode() == PPC::BDNZ) &&
294 LastInst->getOpcode() == PPC::B) {
295 if (!SecondLastInst->getOperand(0).isMBB() ||
296 !LastInst->getOperand(0).isMBB())
298 if (DisableCTRLoopAnal)
300 TBB = SecondLastInst->getOperand(0).getMBB();
301 Cond.push_back(MachineOperand::CreateImm(1));
302 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
304 FBB = LastInst->getOperand(0).getMBB();
306 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
307 SecondLastInst->getOpcode() == PPC::BDZ) &&
308 LastInst->getOpcode() == PPC::B) {
309 if (!SecondLastInst->getOperand(0).isMBB() ||
310 !LastInst->getOperand(0).isMBB())
312 if (DisableCTRLoopAnal)
314 TBB = SecondLastInst->getOperand(0).getMBB();
315 Cond.push_back(MachineOperand::CreateImm(0));
316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
318 FBB = LastInst->getOperand(0).getMBB();
322 // If the block ends with two PPC:Bs, handle it. The second one is not
323 // executed, so remove it.
324 if (SecondLastInst->getOpcode() == PPC::B &&
325 LastInst->getOpcode() == PPC::B) {
326 if (!SecondLastInst->getOperand(0).isMBB())
328 TBB = SecondLastInst->getOperand(0).getMBB();
331 I->eraseFromParent();
335 // Otherwise, can't handle this.
339 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
340 MachineBasicBlock::iterator I = MBB.end();
341 if (I == MBB.begin()) return 0;
343 while (I->isDebugValue()) {
344 if (I == MBB.begin())
348 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
349 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
350 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
353 // Remove the branch.
354 I->eraseFromParent();
358 if (I == MBB.begin()) return 1;
360 if (I->getOpcode() != PPC::BCC &&
361 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
362 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
365 // Remove the branch.
366 I->eraseFromParent();
371 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
372 MachineBasicBlock *FBB,
373 const SmallVectorImpl<MachineOperand> &Cond,
375 // Shouldn't be a fall through.
376 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
377 assert((Cond.size() == 2 || Cond.size() == 0) &&
378 "PPC branch conditions have two components!");
380 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
384 if (Cond.empty()) // Unconditional branch
385 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
386 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
387 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
388 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
389 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
390 else // Conditional branch
391 BuildMI(&MBB, DL, get(PPC::BCC))
392 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
396 // Two-way Conditional Branch.
397 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
398 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
399 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
400 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
402 BuildMI(&MBB, DL, get(PPC::BCC))
403 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
404 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
408 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
409 MachineBasicBlock::iterator I, DebugLoc DL,
410 unsigned DestReg, unsigned SrcReg,
411 bool KillSrc) const {
413 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
415 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
417 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
419 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
421 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
423 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
426 llvm_unreachable("Impossible reg-to-reg copy");
428 const MCInstrDesc &MCID = get(Opc);
429 if (MCID.getNumOperands() == 3)
430 BuildMI(MBB, I, DL, MCID, DestReg)
431 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
433 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
436 // This function returns true if a CR spill is necessary and false otherwise.
438 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
439 unsigned SrcReg, bool isKill,
441 const TargetRegisterClass *RC,
442 SmallVectorImpl<MachineInstr*> &NewMIs,
443 bool &NonRI, bool &SpillsVRS) const{
445 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
446 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
448 getKillRegState(isKill)),
450 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
451 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
453 getKillRegState(isKill)),
455 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
456 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
458 getKillRegState(isKill)),
460 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
461 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
463 getKillRegState(isKill)),
465 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
466 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
468 getKillRegState(isKill)),
471 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
472 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
473 // backend currently only uses CR1EQ as an individual bit, this should
474 // not cause any bug. If we need other uses of CR bits, the following
475 // code may be invalid.
477 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
478 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
480 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
481 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
483 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
484 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
486 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
487 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
489 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
490 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
492 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
493 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
495 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
496 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
498 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
499 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
502 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
503 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
505 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
506 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
508 getKillRegState(isKill)),
511 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
512 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
514 getKillRegState(isKill)),
518 llvm_unreachable("Unknown regclass!");
525 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
526 MachineBasicBlock::iterator MI,
527 unsigned SrcReg, bool isKill, int FrameIdx,
528 const TargetRegisterClass *RC,
529 const TargetRegisterInfo *TRI) const {
530 MachineFunction &MF = *MBB.getParent();
531 SmallVector<MachineInstr*, 4> NewMIs;
533 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
534 FuncInfo->setHasSpills();
536 bool NonRI = false, SpillsVRS = false;
537 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
539 FuncInfo->setSpillsCR();
542 FuncInfo->setSpillsVRSAVE();
545 FuncInfo->setHasNonRISpills();
547 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
548 MBB.insert(MI, NewMIs[i]);
550 const MachineFrameInfo &MFI = *MF.getFrameInfo();
551 MachineMemOperand *MMO =
552 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
553 MachineMemOperand::MOStore,
554 MFI.getObjectSize(FrameIdx),
555 MFI.getObjectAlignment(FrameIdx));
556 NewMIs.back()->addMemOperand(MF, MMO);
560 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
561 unsigned DestReg, int FrameIdx,
562 const TargetRegisterClass *RC,
563 SmallVectorImpl<MachineInstr*> &NewMIs,
564 bool &NonRI, bool &SpillsVRS) const{
565 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
566 if (DestReg != PPC::LR) {
567 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
568 DestReg), FrameIdx));
570 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
571 PPC::R11), FrameIdx));
572 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
574 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
575 if (DestReg != PPC::LR8) {
576 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
579 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
580 PPC::X11), FrameIdx));
581 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
583 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
584 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
586 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
587 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
589 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
590 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
591 get(PPC::RESTORE_CR), DestReg),
594 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
597 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
598 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
600 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
601 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
603 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
604 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
606 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
607 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
609 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
610 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
612 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
613 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
615 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
616 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
618 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
619 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
622 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
623 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
625 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
626 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
629 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
630 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
631 get(PPC::RESTORE_VRSAVE),
636 llvm_unreachable("Unknown regclass!");
643 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
644 MachineBasicBlock::iterator MI,
645 unsigned DestReg, int FrameIdx,
646 const TargetRegisterClass *RC,
647 const TargetRegisterInfo *TRI) const {
648 MachineFunction &MF = *MBB.getParent();
649 SmallVector<MachineInstr*, 4> NewMIs;
651 if (MI != MBB.end()) DL = MI->getDebugLoc();
653 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
654 FuncInfo->setHasSpills();
656 bool NonRI = false, SpillsVRS = false;
657 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
659 FuncInfo->setSpillsCR();
662 FuncInfo->setSpillsVRSAVE();
665 FuncInfo->setHasNonRISpills();
667 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
668 MBB.insert(MI, NewMIs[i]);
670 const MachineFrameInfo &MFI = *MF.getFrameInfo();
671 MachineMemOperand *MMO =
672 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
673 MachineMemOperand::MOLoad,
674 MFI.getObjectSize(FrameIdx),
675 MFI.getObjectAlignment(FrameIdx));
676 NewMIs.back()->addMemOperand(MF, MMO);
680 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
681 int FrameIx, uint64_t Offset,
684 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
685 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
690 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
691 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
692 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
693 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
695 // Leave the CR# the same, but invert the condition.
696 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
700 /// GetInstSize - Return the number of bytes of code the specified
701 /// instruction may be. This returns the maximum number of bytes.
703 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
704 switch (MI->getOpcode()) {
705 case PPC::INLINEASM: { // Inline Asm: Variable size.
706 const MachineFunction *MF = MI->getParent()->getParent();
707 const char *AsmStr = MI->getOperand(0).getSymbolName();
708 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
710 case PPC::PROLOG_LABEL:
719 return 4; // PowerPC instructions are all 4 bytes