1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62 cl::desc("Use the old (incorrect) instruction latency calculation"));
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
67 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
73 ScheduleHazardRecognizer *
74 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75 const ScheduleDAG *DAG) const {
77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80 const InstrItineraryData *II =
81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return new ScoreboardHazardRecognizer(II, DAG);
85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
90 ScheduleHazardRecognizer *
91 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92 const ScheduleDAG *DAG) const {
94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
99 // Most subtargets use a PPC970 recognizer.
100 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102 assert(DAG->TII && "No InstrInfo?");
104 return new PPCHazardRecognizer970(*DAG);
107 return new ScoreboardHazardRecognizer(II, DAG);
110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111 const MachineInstr *MI,
112 unsigned *PredCost) const {
113 if (!ItinData || UseOldLatencyCalc)
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 // The default implementation of getInstrLatency calls getStageLatency, but
117 // getStageLatency does not do the right thing for us. While we have
118 // itinerary, most cores are fully pipelined, and so the itineraries only
119 // express the first part of the pipeline, not every stage. Instead, we need
120 // to use the listed output operand cycle number (using operand 0 here, which
123 unsigned Latency = 1;
124 unsigned DefClass = MI->getDesc().getSchedClass();
125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126 const MachineOperand &MO = MI->getOperand(i);
127 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
130 int Cycle = ItinData->getOperandCycle(DefClass, i);
134 Latency = std::max(Latency, (unsigned) Cycle);
140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
141 const MachineInstr *DefMI, unsigned DefIdx,
142 const MachineInstr *UseMI,
143 unsigned UseIdx) const {
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
147 if (!DefMI->getParent())
150 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
151 unsigned Reg = DefMO.getReg();
154 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
155 const MachineRegisterInfo *MRI =
156 &DefMI->getParent()->getParent()->getRegInfo();
157 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
158 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
160 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
161 PPC::CRBITRCRegClass.contains(Reg);
164 if (UseMI->isBranch() && IsRegCR) {
166 Latency = getInstrLatency(ItinData, DefMI);
168 // On some cores, there is an additional delay between writing to a condition
169 // register, and using it from a branch.
170 unsigned Directive = Subtarget.getDarwinDirective();
192 // This function does not list all associative and commutative operations, but
193 // only those worth feeding through the machine combiner in an attempt to
194 // reduce the critical path. Mostly, this means floating-point operations,
195 // because they have high latencies (compared to other operations, such and
196 // and/or, which are also associative and commutative, but have low latencies).
197 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
198 switch (Inst.getOpcode()) {
231 bool PPCInstrInfo::getMachineCombinerPatterns(
233 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
234 // Using the machine combiner in this way is potentially expensive, so
235 // restrict to when aggressive optimizations are desired.
236 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
239 // FP reassociation is only legal when we don't need strict IEEE semantics.
240 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
243 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
246 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
247 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
248 unsigned &SrcReg, unsigned &DstReg,
249 unsigned &SubIdx) const {
250 switch (MI.getOpcode()) {
251 default: return false;
253 case PPC::EXTSW_32_64:
254 SrcReg = MI.getOperand(1).getReg();
255 DstReg = MI.getOperand(0).getReg();
256 SubIdx = PPC::sub_32;
261 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
262 int &FrameIndex) const {
263 // Note: This list must be kept consistent with LoadRegFromStackSlot.
264 switch (MI->getOpcode()) {
270 case PPC::RESTORE_CR:
271 case PPC::RESTORE_CRBIT:
277 case PPC::RESTORE_VRSAVE:
278 // Check for the operands added by addFrameReference (the immediate is the
279 // offset which defaults to 0).
280 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
281 MI->getOperand(2).isFI()) {
282 FrameIndex = MI->getOperand(2).getIndex();
283 return MI->getOperand(0).getReg();
290 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
291 int &FrameIndex) const {
292 // Note: This list must be kept consistent with StoreRegToStackSlot.
293 switch (MI->getOpcode()) {
300 case PPC::SPILL_CRBIT:
306 case PPC::SPILL_VRSAVE:
307 // Check for the operands added by addFrameReference (the immediate is the
308 // offset which defaults to 0).
309 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
310 MI->getOperand(2).isFI()) {
311 FrameIndex = MI->getOperand(2).getIndex();
312 return MI->getOperand(0).getReg();
319 // commuteInstruction - We can commute rlwimi instructions, but only if the
320 // rotate amt is zero. We also have to munge the immediates a bit.
322 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
323 MachineFunction &MF = *MI->getParent()->getParent();
325 // Normal instructions can be commuted the obvious way.
326 if (MI->getOpcode() != PPC::RLWIMI &&
327 MI->getOpcode() != PPC::RLWIMIo)
328 return TargetInstrInfo::commuteInstruction(MI, NewMI);
329 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
330 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
331 // changing the relative order of the mask operands might change what happens
332 // to the high-bits of the mask (and, thus, the result).
334 // Cannot commute if it has a non-zero rotate count.
335 if (MI->getOperand(3).getImm() != 0)
338 // If we have a zero rotate count, we have:
340 // Op0 = (Op1 & ~M) | (Op2 & M)
342 // M = mask((ME+1)&31, (MB-1)&31)
343 // Op0 = (Op2 & ~M) | (Op1 & M)
346 unsigned Reg0 = MI->getOperand(0).getReg();
347 unsigned Reg1 = MI->getOperand(1).getReg();
348 unsigned Reg2 = MI->getOperand(2).getReg();
349 unsigned SubReg1 = MI->getOperand(1).getSubReg();
350 unsigned SubReg2 = MI->getOperand(2).getSubReg();
351 bool Reg1IsKill = MI->getOperand(1).isKill();
352 bool Reg2IsKill = MI->getOperand(2).isKill();
353 bool ChangeReg0 = false;
354 // If machine instrs are no longer in two-address forms, update
355 // destination register as well.
357 // Must be two address instruction!
358 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
359 "Expecting a two-address instruction!");
360 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
366 unsigned MB = MI->getOperand(4).getImm();
367 unsigned ME = MI->getOperand(5).getImm();
369 // We can't commute a trivial mask (there is no way to represent an all-zero
371 if (MB == 0 && ME == 31)
375 // Create a new instruction.
376 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
377 bool Reg0IsDead = MI->getOperand(0).isDead();
378 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
379 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
380 .addReg(Reg2, getKillRegState(Reg2IsKill))
381 .addReg(Reg1, getKillRegState(Reg1IsKill))
383 .addImm((MB-1) & 31);
387 MI->getOperand(0).setReg(Reg2);
388 MI->getOperand(0).setSubReg(SubReg2);
390 MI->getOperand(2).setReg(Reg1);
391 MI->getOperand(1).setReg(Reg2);
392 MI->getOperand(2).setSubReg(SubReg1);
393 MI->getOperand(1).setSubReg(SubReg2);
394 MI->getOperand(2).setIsKill(Reg1IsKill);
395 MI->getOperand(1).setIsKill(Reg2IsKill);
397 // Swap the mask around.
398 MI->getOperand(4).setImm((ME+1) & 31);
399 MI->getOperand(5).setImm((MB-1) & 31);
403 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
404 unsigned &SrcOpIdx2) const {
405 // For VSX A-Type FMA instructions, it is the first two operands that can be
406 // commuted, however, because the non-encoded tied input operand is listed
407 // first, the operands to swap are actually the second and third.
409 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
411 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
418 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
419 MachineBasicBlock::iterator MI) const {
420 // This function is used for scheduling, and the nop wanted here is the type
421 // that terminates dispatch groups on the POWER cores.
422 unsigned Directive = Subtarget.getDarwinDirective();
425 default: Opcode = PPC::NOP; break;
426 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
427 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
428 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
432 BuildMI(MBB, MI, DL, get(Opcode));
435 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
436 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
437 NopInst.setOpcode(PPC::NOP);
441 // Note: If the condition register is set to CTR or CTR8 then this is a
442 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
443 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
444 MachineBasicBlock *&FBB,
445 SmallVectorImpl<MachineOperand> &Cond,
446 bool AllowModify) const {
447 bool isPPC64 = Subtarget.isPPC64();
449 // If the block has no terminators, it just falls into the block after it.
450 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
454 if (!isUnpredicatedTerminator(I))
457 // Get the last instruction in the block.
458 MachineInstr *LastInst = I;
460 // If there is only one terminator instruction, process it.
461 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
462 if (LastInst->getOpcode() == PPC::B) {
463 if (!LastInst->getOperand(0).isMBB())
465 TBB = LastInst->getOperand(0).getMBB();
467 } else if (LastInst->getOpcode() == PPC::BCC) {
468 if (!LastInst->getOperand(2).isMBB())
470 // Block ends with fall-through condbranch.
471 TBB = LastInst->getOperand(2).getMBB();
472 Cond.push_back(LastInst->getOperand(0));
473 Cond.push_back(LastInst->getOperand(1));
475 } else if (LastInst->getOpcode() == PPC::BC) {
476 if (!LastInst->getOperand(1).isMBB())
478 // Block ends with fall-through condbranch.
479 TBB = LastInst->getOperand(1).getMBB();
480 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
481 Cond.push_back(LastInst->getOperand(0));
483 } else if (LastInst->getOpcode() == PPC::BCn) {
484 if (!LastInst->getOperand(1).isMBB())
486 // Block ends with fall-through condbranch.
487 TBB = LastInst->getOperand(1).getMBB();
488 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
489 Cond.push_back(LastInst->getOperand(0));
491 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
492 LastInst->getOpcode() == PPC::BDNZ) {
493 if (!LastInst->getOperand(0).isMBB())
495 if (DisableCTRLoopAnal)
497 TBB = LastInst->getOperand(0).getMBB();
498 Cond.push_back(MachineOperand::CreateImm(1));
499 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
502 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
503 LastInst->getOpcode() == PPC::BDZ) {
504 if (!LastInst->getOperand(0).isMBB())
506 if (DisableCTRLoopAnal)
508 TBB = LastInst->getOperand(0).getMBB();
509 Cond.push_back(MachineOperand::CreateImm(0));
510 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
515 // Otherwise, don't know what this is.
519 // Get the instruction before it if it's a terminator.
520 MachineInstr *SecondLastInst = I;
522 // If there are three terminators, we don't know what sort of block this is.
523 if (SecondLastInst && I != MBB.begin() &&
524 isUnpredicatedTerminator(--I))
527 // If the block ends with PPC::B and PPC:BCC, handle it.
528 if (SecondLastInst->getOpcode() == PPC::BCC &&
529 LastInst->getOpcode() == PPC::B) {
530 if (!SecondLastInst->getOperand(2).isMBB() ||
531 !LastInst->getOperand(0).isMBB())
533 TBB = SecondLastInst->getOperand(2).getMBB();
534 Cond.push_back(SecondLastInst->getOperand(0));
535 Cond.push_back(SecondLastInst->getOperand(1));
536 FBB = LastInst->getOperand(0).getMBB();
538 } else if (SecondLastInst->getOpcode() == PPC::BC &&
539 LastInst->getOpcode() == PPC::B) {
540 if (!SecondLastInst->getOperand(1).isMBB() ||
541 !LastInst->getOperand(0).isMBB())
543 TBB = SecondLastInst->getOperand(1).getMBB();
544 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
545 Cond.push_back(SecondLastInst->getOperand(0));
546 FBB = LastInst->getOperand(0).getMBB();
548 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
549 LastInst->getOpcode() == PPC::B) {
550 if (!SecondLastInst->getOperand(1).isMBB() ||
551 !LastInst->getOperand(0).isMBB())
553 TBB = SecondLastInst->getOperand(1).getMBB();
554 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
555 Cond.push_back(SecondLastInst->getOperand(0));
556 FBB = LastInst->getOperand(0).getMBB();
558 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
559 SecondLastInst->getOpcode() == PPC::BDNZ) &&
560 LastInst->getOpcode() == PPC::B) {
561 if (!SecondLastInst->getOperand(0).isMBB() ||
562 !LastInst->getOperand(0).isMBB())
564 if (DisableCTRLoopAnal)
566 TBB = SecondLastInst->getOperand(0).getMBB();
567 Cond.push_back(MachineOperand::CreateImm(1));
568 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
570 FBB = LastInst->getOperand(0).getMBB();
572 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
573 SecondLastInst->getOpcode() == PPC::BDZ) &&
574 LastInst->getOpcode() == PPC::B) {
575 if (!SecondLastInst->getOperand(0).isMBB() ||
576 !LastInst->getOperand(0).isMBB())
578 if (DisableCTRLoopAnal)
580 TBB = SecondLastInst->getOperand(0).getMBB();
581 Cond.push_back(MachineOperand::CreateImm(0));
582 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
584 FBB = LastInst->getOperand(0).getMBB();
588 // If the block ends with two PPC:Bs, handle it. The second one is not
589 // executed, so remove it.
590 if (SecondLastInst->getOpcode() == PPC::B &&
591 LastInst->getOpcode() == PPC::B) {
592 if (!SecondLastInst->getOperand(0).isMBB())
594 TBB = SecondLastInst->getOperand(0).getMBB();
597 I->eraseFromParent();
601 // Otherwise, can't handle this.
605 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
606 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
610 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
611 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
612 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
613 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
616 // Remove the branch.
617 I->eraseFromParent();
621 if (I == MBB.begin()) return 1;
623 if (I->getOpcode() != PPC::BCC &&
624 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
625 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
626 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
629 // Remove the branch.
630 I->eraseFromParent();
635 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
636 MachineBasicBlock *FBB,
637 ArrayRef<MachineOperand> Cond,
639 // Shouldn't be a fall through.
640 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
641 assert((Cond.size() == 2 || Cond.size() == 0) &&
642 "PPC branch conditions have two components!");
644 bool isPPC64 = Subtarget.isPPC64();
648 if (Cond.empty()) // Unconditional branch
649 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
650 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
651 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
652 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
653 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
654 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
655 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
656 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
657 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
658 else // Conditional branch
659 BuildMI(&MBB, DL, get(PPC::BCC))
660 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
664 // Two-way Conditional Branch.
665 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
666 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
667 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
668 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
669 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
670 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
671 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
672 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
674 BuildMI(&MBB, DL, get(PPC::BCC))
675 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
676 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
681 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
682 ArrayRef<MachineOperand> Cond,
683 unsigned TrueReg, unsigned FalseReg,
684 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
685 if (!Subtarget.hasISEL())
688 if (Cond.size() != 2)
691 // If this is really a bdnz-like condition, then it cannot be turned into a
693 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
696 // Check register classes.
697 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
698 const TargetRegisterClass *RC =
699 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
703 // isel is for regular integer GPRs only.
704 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
705 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
706 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
707 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
710 // FIXME: These numbers are for the A2, how well they work for other cores is
711 // an open question. On the A2, the isel instruction has a 2-cycle latency
712 // but single-cycle throughput. These numbers are used in combination with
713 // the MispredictPenalty setting from the active SchedMachineModel.
721 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
722 MachineBasicBlock::iterator MI, DebugLoc dl,
723 unsigned DestReg, ArrayRef<MachineOperand> Cond,
724 unsigned TrueReg, unsigned FalseReg) const {
725 assert(Cond.size() == 2 &&
726 "PPC branch conditions have two components!");
728 assert(Subtarget.hasISEL() &&
729 "Cannot insert select on target without ISEL support");
731 // Get the register classes.
732 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
733 const TargetRegisterClass *RC =
734 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
735 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
737 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
738 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
740 PPC::GPRCRegClass.hasSubClassEq(RC) ||
741 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
742 "isel is for regular integer GPRs only");
744 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
745 unsigned SelectPred = Cond[0].getImm();
749 switch (SelectPred) {
750 default: llvm_unreachable("invalid predicate for isel");
751 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
752 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
753 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
754 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
755 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
756 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
757 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
758 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
759 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
760 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
763 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
764 SecondReg = SwapOps ? TrueReg : FalseReg;
766 // The first input register of isel cannot be r0. If it is a member
767 // of a register class that can be r0, then copy it first (the
768 // register allocator should eliminate the copy).
769 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
770 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
771 const TargetRegisterClass *FirstRC =
772 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
773 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
774 unsigned OldFirstReg = FirstReg;
775 FirstReg = MRI.createVirtualRegister(FirstRC);
776 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
777 .addReg(OldFirstReg);
780 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
781 .addReg(FirstReg).addReg(SecondReg)
782 .addReg(Cond[1].getReg(), 0, SubIdx);
785 static unsigned getCRBitValue(unsigned CRBit) {
787 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
788 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
789 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
790 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
792 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
793 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
794 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
795 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
797 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
798 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
799 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
800 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
802 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
803 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
804 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
805 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
808 assert(Ret != 4 && "Invalid CR bit register");
812 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
813 MachineBasicBlock::iterator I, DebugLoc DL,
814 unsigned DestReg, unsigned SrcReg,
815 bool KillSrc) const {
816 // We can end up with self copies and similar things as a result of VSX copy
817 // legalization. Promote them here.
818 const TargetRegisterInfo *TRI = &getRegisterInfo();
819 if (PPC::F8RCRegClass.contains(DestReg) &&
820 PPC::VSRCRegClass.contains(SrcReg)) {
822 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
824 if (VSXSelfCopyCrash && SrcReg == SuperReg)
825 llvm_unreachable("nop VSX copy");
828 } else if (PPC::VRRCRegClass.contains(DestReg) &&
829 PPC::VSRCRegClass.contains(SrcReg)) {
831 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
833 if (VSXSelfCopyCrash && SrcReg == SuperReg)
834 llvm_unreachable("nop VSX copy");
837 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
838 PPC::VSRCRegClass.contains(DestReg)) {
840 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
842 if (VSXSelfCopyCrash && DestReg == SuperReg)
843 llvm_unreachable("nop VSX copy");
846 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
847 PPC::VSRCRegClass.contains(DestReg)) {
849 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
851 if (VSXSelfCopyCrash && DestReg == SuperReg)
852 llvm_unreachable("nop VSX copy");
857 // Different class register copy
858 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
859 PPC::GPRCRegClass.contains(DestReg)) {
860 unsigned CRReg = getCRFromCRBit(SrcReg);
861 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
862 .addReg(CRReg), getKillRegState(KillSrc);
863 // Rotate the CR bit in the CR fields to be the least significant bit and
864 // then mask with 0x1 (MB = ME = 31).
865 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
866 .addReg(DestReg, RegState::Kill)
867 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
871 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
872 PPC::G8RCRegClass.contains(DestReg)) {
873 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
874 .addReg(SrcReg), getKillRegState(KillSrc);
876 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
877 PPC::GPRCRegClass.contains(DestReg)) {
878 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
879 .addReg(SrcReg), getKillRegState(KillSrc);
884 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
886 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
888 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
890 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
892 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
894 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
895 // There are two different ways this can be done:
896 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
897 // issue in VSU pipeline 0.
898 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
899 // can go to either pipeline.
900 // We'll always use xxlor here, because in practically all cases where
901 // copies are generated, they are close enough to some use that the
902 // lower-latency form is preferable.
904 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
905 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
907 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
909 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
911 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
913 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
916 llvm_unreachable("Impossible reg-to-reg copy");
918 const MCInstrDesc &MCID = get(Opc);
919 if (MCID.getNumOperands() == 3)
920 BuildMI(MBB, I, DL, MCID, DestReg)
921 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
923 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
926 // This function returns true if a CR spill is necessary and false otherwise.
928 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
929 unsigned SrcReg, bool isKill,
931 const TargetRegisterClass *RC,
932 SmallVectorImpl<MachineInstr*> &NewMIs,
933 bool &NonRI, bool &SpillsVRS) const{
934 // Note: If additional store instructions are added here,
935 // update isStoreToStackSlot.
938 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
939 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
940 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
942 getKillRegState(isKill)),
944 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
945 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
946 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
948 getKillRegState(isKill)),
950 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
951 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
953 getKillRegState(isKill)),
955 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
956 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
958 getKillRegState(isKill)),
960 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
961 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
963 getKillRegState(isKill)),
966 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
967 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
969 getKillRegState(isKill)),
972 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
973 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
975 getKillRegState(isKill)),
978 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
981 getKillRegState(isKill)),
984 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
985 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
987 getKillRegState(isKill)),
990 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
991 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
993 getKillRegState(isKill)),
996 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
997 assert(Subtarget.isDarwin() &&
998 "VRSAVE only needs spill/restore on Darwin");
999 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1001 getKillRegState(isKill)),
1004 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1005 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1007 getKillRegState(isKill)),
1010 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1011 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1013 getKillRegState(isKill)),
1016 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1017 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1019 getKillRegState(isKill)),
1023 llvm_unreachable("Unknown regclass!");
1030 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1031 MachineBasicBlock::iterator MI,
1032 unsigned SrcReg, bool isKill, int FrameIdx,
1033 const TargetRegisterClass *RC,
1034 const TargetRegisterInfo *TRI) const {
1035 MachineFunction &MF = *MBB.getParent();
1036 SmallVector<MachineInstr*, 4> NewMIs;
1038 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1039 FuncInfo->setHasSpills();
1041 bool NonRI = false, SpillsVRS = false;
1042 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1044 FuncInfo->setSpillsCR();
1047 FuncInfo->setSpillsVRSAVE();
1050 FuncInfo->setHasNonRISpills();
1052 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1053 MBB.insert(MI, NewMIs[i]);
1055 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1056 MachineMemOperand *MMO = MF.getMachineMemOperand(
1057 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1058 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1059 MFI.getObjectAlignment(FrameIdx));
1060 NewMIs.back()->addMemOperand(MF, MMO);
1064 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1065 unsigned DestReg, int FrameIdx,
1066 const TargetRegisterClass *RC,
1067 SmallVectorImpl<MachineInstr*> &NewMIs,
1068 bool &NonRI, bool &SpillsVRS) const{
1069 // Note: If additional load instructions are added here,
1070 // update isLoadFromStackSlot.
1072 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1073 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1074 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1075 DestReg), FrameIdx));
1076 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1077 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1078 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1080 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1081 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1083 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1084 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1086 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1087 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1088 get(PPC::RESTORE_CR), DestReg),
1091 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1092 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1093 get(PPC::RESTORE_CRBIT), DestReg),
1096 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1097 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1100 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1104 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1105 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1108 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1109 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1112 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1113 assert(Subtarget.isDarwin() &&
1114 "VRSAVE only needs spill/restore on Darwin");
1115 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1116 get(PPC::RESTORE_VRSAVE),
1120 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1121 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1124 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1125 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1128 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1129 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1133 llvm_unreachable("Unknown regclass!");
1140 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1141 MachineBasicBlock::iterator MI,
1142 unsigned DestReg, int FrameIdx,
1143 const TargetRegisterClass *RC,
1144 const TargetRegisterInfo *TRI) const {
1145 MachineFunction &MF = *MBB.getParent();
1146 SmallVector<MachineInstr*, 4> NewMIs;
1148 if (MI != MBB.end()) DL = MI->getDebugLoc();
1150 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1151 FuncInfo->setHasSpills();
1153 bool NonRI = false, SpillsVRS = false;
1154 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1156 FuncInfo->setSpillsCR();
1159 FuncInfo->setSpillsVRSAVE();
1162 FuncInfo->setHasNonRISpills();
1164 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1165 MBB.insert(MI, NewMIs[i]);
1167 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1168 MachineMemOperand *MMO = MF.getMachineMemOperand(
1169 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1170 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1171 MFI.getObjectAlignment(FrameIdx));
1172 NewMIs.back()->addMemOperand(MF, MMO);
1176 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1177 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1178 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1179 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1181 // Leave the CR# the same, but invert the condition.
1182 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1186 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1187 unsigned Reg, MachineRegisterInfo *MRI) const {
1188 // For some instructions, it is legal to fold ZERO into the RA register field.
1189 // A zero immediate should always be loaded with a single li.
1190 unsigned DefOpc = DefMI->getOpcode();
1191 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1193 if (!DefMI->getOperand(1).isImm())
1195 if (DefMI->getOperand(1).getImm() != 0)
1198 // Note that we cannot here invert the arguments of an isel in order to fold
1199 // a ZERO into what is presented as the second argument. All we have here
1200 // is the condition bit, and that might come from a CR-logical bit operation.
1202 const MCInstrDesc &UseMCID = UseMI->getDesc();
1204 // Only fold into real machine instructions.
1205 if (UseMCID.isPseudo())
1209 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1210 if (UseMI->getOperand(UseIdx).isReg() &&
1211 UseMI->getOperand(UseIdx).getReg() == Reg)
1214 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1215 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1217 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1219 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1220 // register (which might also be specified as a pointer class kind).
1221 if (UseInfo->isLookupPtrRegClass()) {
1222 if (UseInfo->RegClass /* Kind */ != 1)
1225 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1226 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1230 // Make sure this is not tied to an output register (or otherwise
1231 // constrained). This is true for ST?UX registers, for example, which
1232 // are tied to their output registers.
1233 if (UseInfo->Constraints != 0)
1237 if (UseInfo->isLookupPtrRegClass()) {
1238 bool isPPC64 = Subtarget.isPPC64();
1239 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1241 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1242 PPC::ZERO8 : PPC::ZERO;
1245 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1246 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1249 DefMI->eraseFromParent();
1254 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1255 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1257 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1262 // We should make sure that, if we're going to predicate both sides of a
1263 // condition (a diamond), that both sides don't define the counter register. We
1264 // can predicate counter-decrement-based branches, but while that predicates
1265 // the branching, it does not predicate the counter decrement. If we tried to
1266 // merge the triangle into one predicated block, we'd decrement the counter
1268 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1269 unsigned NumT, unsigned ExtraT,
1270 MachineBasicBlock &FMBB,
1271 unsigned NumF, unsigned ExtraF,
1272 BranchProbability Probability) const {
1273 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1277 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1278 // The predicated branches are identified by their type, not really by the
1279 // explicit presence of a predicate. Furthermore, some of them can be
1280 // predicated more than once. Because if conversion won't try to predicate
1281 // any instruction which already claims to be predicated (by returning true
1282 // here), always return false. In doing so, we let isPredicable() be the
1283 // final word on whether not the instruction can be (further) predicated.
1288 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1289 if (!MI->isTerminator())
1292 // Conditional branch is a special case.
1293 if (MI->isBranch() && !MI->isBarrier())
1296 return !isPredicated(MI);
1299 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1300 ArrayRef<MachineOperand> Pred) const {
1301 unsigned OpC = MI->getOpcode();
1302 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1303 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1304 bool isPPC64 = Subtarget.isPPC64();
1305 MI->setDesc(get(Pred[0].getImm() ?
1306 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1307 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1308 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1309 MI->setDesc(get(PPC::BCLR));
1310 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1311 .addReg(Pred[1].getReg());
1312 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1313 MI->setDesc(get(PPC::BCLRn));
1314 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1315 .addReg(Pred[1].getReg());
1317 MI->setDesc(get(PPC::BCCLR));
1318 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1319 .addImm(Pred[0].getImm())
1320 .addReg(Pred[1].getReg());
1324 } else if (OpC == PPC::B) {
1325 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1326 bool isPPC64 = Subtarget.isPPC64();
1327 MI->setDesc(get(Pred[0].getImm() ?
1328 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1329 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1330 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1331 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1332 MI->RemoveOperand(0);
1334 MI->setDesc(get(PPC::BC));
1335 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1336 .addReg(Pred[1].getReg())
1338 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1339 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1340 MI->RemoveOperand(0);
1342 MI->setDesc(get(PPC::BCn));
1343 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1344 .addReg(Pred[1].getReg())
1347 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1348 MI->RemoveOperand(0);
1350 MI->setDesc(get(PPC::BCC));
1351 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1352 .addImm(Pred[0].getImm())
1353 .addReg(Pred[1].getReg())
1358 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1359 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1360 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1361 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1363 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1364 bool isPPC64 = Subtarget.isPPC64();
1366 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1367 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1368 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1369 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1370 .addReg(Pred[1].getReg());
1372 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1373 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1374 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1375 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1376 .addReg(Pred[1].getReg());
1380 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1381 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1382 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1383 .addImm(Pred[0].getImm())
1384 .addReg(Pred[1].getReg());
1391 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1392 ArrayRef<MachineOperand> Pred2) const {
1393 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1394 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1396 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1398 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1401 // P1 can only subsume P2 if they test the same condition register.
1402 if (Pred1[1].getReg() != Pred2[1].getReg())
1405 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1406 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1411 // Does P1 subsume P2, e.g. GE subsumes GT.
1412 if (P1 == PPC::PRED_LE &&
1413 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1415 if (P1 == PPC::PRED_GE &&
1416 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1422 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1423 std::vector<MachineOperand> &Pred) const {
1424 // Note: At the present time, the contents of Pred from this function is
1425 // unused by IfConversion. This implementation follows ARM by pushing the
1426 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1427 // predicate, instructions defining CTR or CTR8 are also included as
1428 // predicate-defining instructions.
1430 const TargetRegisterClass *RCs[] =
1431 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1432 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1435 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1436 const MachineOperand &MO = MI->getOperand(i);
1437 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1438 const TargetRegisterClass *RC = RCs[c];
1440 if (MO.isDef() && RC->contains(MO.getReg())) {
1444 } else if (MO.isRegMask()) {
1445 for (TargetRegisterClass::iterator I = RC->begin(),
1446 IE = RC->end(); I != IE; ++I)
1447 if (MO.clobbersPhysReg(*I)) {
1458 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1459 unsigned OpC = MI->getOpcode();
1474 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1475 unsigned &SrcReg, unsigned &SrcReg2,
1476 int &Mask, int &Value) const {
1477 unsigned Opc = MI->getOpcode();
1480 default: return false;
1485 SrcReg = MI->getOperand(1).getReg();
1487 Value = MI->getOperand(2).getImm();
1496 SrcReg = MI->getOperand(1).getReg();
1497 SrcReg2 = MI->getOperand(2).getReg();
1502 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1503 unsigned SrcReg, unsigned SrcReg2,
1504 int Mask, int Value,
1505 const MachineRegisterInfo *MRI) const {
1509 int OpC = CmpInstr->getOpcode();
1510 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1512 // FP record forms set CR1 based on the execption status bits, not a
1513 // comparison with zero.
1514 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1517 // The record forms set the condition register based on a signed comparison
1518 // with zero (so says the ISA manual). This is not as straightforward as it
1519 // seems, however, because this is always a 64-bit comparison on PPC64, even
1520 // for instructions that are 32-bit in nature (like slw for example).
1521 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1522 // for equality checks (as those don't depend on the sign). On PPC64,
1523 // we are restricted to equality for unsigned 64-bit comparisons and for
1524 // signed 32-bit comparisons the applicability is more restricted.
1525 bool isPPC64 = Subtarget.isPPC64();
1526 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1527 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1528 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1530 // Get the unique definition of SrcReg.
1531 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1532 if (!MI) return false;
1533 int MIOpC = MI->getOpcode();
1535 bool equalityOnly = false;
1538 if (is32BitSignedCompare) {
1539 // We can perform this optimization only if MI is sign-extending.
1540 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1541 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1542 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1543 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1544 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1548 } else if (is32BitUnsignedCompare) {
1549 // We can perform this optimization, equality only, if MI is
1551 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1552 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1553 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1555 equalityOnly = true;
1559 equalityOnly = is64BitUnsignedCompare;
1561 equalityOnly = is32BitUnsignedCompare;
1564 // We need to check the uses of the condition register in order to reject
1565 // non-equality comparisons.
1566 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1567 IE = MRI->use_instr_end(); I != IE; ++I) {
1568 MachineInstr *UseMI = &*I;
1569 if (UseMI->getOpcode() == PPC::BCC) {
1570 unsigned Pred = UseMI->getOperand(0).getImm();
1571 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1573 } else if (UseMI->getOpcode() == PPC::ISEL ||
1574 UseMI->getOpcode() == PPC::ISEL8) {
1575 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1576 if (SubIdx != PPC::sub_eq)
1583 MachineBasicBlock::iterator I = CmpInstr;
1585 // Scan forward to find the first use of the compare.
1586 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1588 bool FoundUse = false;
1589 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1590 JE = MRI->use_instr_end(); J != JE; ++J)
1600 // There are two possible candidates which can be changed to set CR[01].
1601 // One is MI, the other is a SUB instruction.
1602 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1603 MachineInstr *Sub = nullptr;
1605 // MI is not a candidate for CMPrr.
1607 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1608 // same BB as the comparison. This is to allow the check below to avoid calls
1609 // (and other explicit clobbers); instead we should really check for these
1610 // more explicitly (in at least a few predecessors).
1611 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1612 // PPC does not have a record-form SUBri.
1617 const TargetRegisterInfo *TRI = &getRegisterInfo();
1620 // Get ready to iterate backward from CmpInstr.
1621 MachineBasicBlock::iterator E = MI,
1622 B = CmpInstr->getParent()->begin();
1624 for (; I != E && !noSub; --I) {
1625 const MachineInstr &Instr = *I;
1626 unsigned IOpC = Instr.getOpcode();
1628 if (&*I != CmpInstr && (
1629 Instr.modifiesRegister(PPC::CR0, TRI) ||
1630 Instr.readsRegister(PPC::CR0, TRI)))
1631 // This instruction modifies or uses the record condition register after
1632 // the one we want to change. While we could do this transformation, it
1633 // would likely not be profitable. This transformation removes one
1634 // instruction, and so even forcing RA to generate one move probably
1635 // makes it unprofitable.
1638 // Check whether CmpInstr can be made redundant by the current instruction.
1639 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1640 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1641 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1642 ((Instr.getOperand(1).getReg() == SrcReg &&
1643 Instr.getOperand(2).getReg() == SrcReg2) ||
1644 (Instr.getOperand(1).getReg() == SrcReg2 &&
1645 Instr.getOperand(2).getReg() == SrcReg))) {
1651 // The 'and' is below the comparison instruction.
1655 // Return false if no candidates exist.
1659 // The single candidate is called MI.
1663 MIOpC = MI->getOpcode();
1664 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1667 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1668 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1672 // FIXME: On the non-embedded POWER architectures, only some of the record
1673 // forms are fast, and we should use only the fast ones.
1675 // The defining instruction has a record form (or is already a record
1676 // form). It is possible, however, that we'll need to reverse the condition
1677 // code of the users.
1681 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1682 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1684 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1685 // needs to be updated to be based on SUB. Push the condition code
1686 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1687 // condition code of these operands will be modified.
1688 bool ShouldSwap = false;
1690 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1691 Sub->getOperand(2).getReg() == SrcReg;
1693 // The operands to subf are the opposite of sub, so only in the fixed-point
1694 // case, invert the order.
1695 ShouldSwap = !ShouldSwap;
1699 for (MachineRegisterInfo::use_instr_iterator
1700 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1702 MachineInstr *UseMI = &*I;
1703 if (UseMI->getOpcode() == PPC::BCC) {
1704 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1705 assert((!equalityOnly ||
1706 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1707 "Invalid predicate for equality-only optimization");
1708 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1709 PPC::getSwappedPredicate(Pred)));
1710 } else if (UseMI->getOpcode() == PPC::ISEL ||
1711 UseMI->getOpcode() == PPC::ISEL8) {
1712 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1713 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1714 "Invalid CR bit for equality-only optimization");
1716 if (NewSubReg == PPC::sub_lt)
1717 NewSubReg = PPC::sub_gt;
1718 else if (NewSubReg == PPC::sub_gt)
1719 NewSubReg = PPC::sub_lt;
1721 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1723 } else // We need to abort on a user we don't understand.
1727 // Create a new virtual register to hold the value of the CR set by the
1728 // record-form instruction. If the instruction was not previously in
1729 // record form, then set the kill flag on the CR.
1730 CmpInstr->eraseFromParent();
1732 MachineBasicBlock::iterator MII = MI;
1733 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1734 get(TargetOpcode::COPY), CRReg)
1735 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1737 if (MIOpC != NewOpC) {
1738 // We need to be careful here: we're replacing one instruction with
1739 // another, and we need to make sure that we get all of the right
1740 // implicit uses and defs. On the other hand, the caller may be holding
1741 // an iterator to this instruction, and so we can't delete it (this is
1742 // specifically the case if this is the instruction directly after the
1745 const MCInstrDesc &NewDesc = get(NewOpC);
1746 MI->setDesc(NewDesc);
1748 if (NewDesc.ImplicitDefs)
1749 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1750 *ImpDefs; ++ImpDefs)
1751 if (!MI->definesRegister(*ImpDefs))
1752 MI->addOperand(*MI->getParent()->getParent(),
1753 MachineOperand::CreateReg(*ImpDefs, true, true));
1754 if (NewDesc.ImplicitUses)
1755 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1756 *ImpUses; ++ImpUses)
1757 if (!MI->readsRegister(*ImpUses))
1758 MI->addOperand(*MI->getParent()->getParent(),
1759 MachineOperand::CreateReg(*ImpUses, false, true));
1762 // Modify the condition code of operands in OperandsToUpdate.
1763 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1764 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1765 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1766 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1768 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1769 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1774 /// GetInstSize - Return the number of bytes of code the specified
1775 /// instruction may be. This returns the maximum number of bytes.
1777 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1778 unsigned Opcode = MI->getOpcode();
1780 if (Opcode == PPC::INLINEASM) {
1781 const MachineFunction *MF = MI->getParent()->getParent();
1782 const char *AsmStr = MI->getOperand(0).getSymbolName();
1783 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1784 } else if (Opcode == TargetOpcode::STACKMAP) {
1785 return MI->getOperand(1).getImm();
1786 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1787 PatchPointOpers Opers(MI);
1788 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1790 const MCInstrDesc &Desc = get(Opcode);
1791 return Desc.getSize();
1795 std::pair<unsigned, unsigned>
1796 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
1797 const unsigned Mask = PPCII::MO_ACCESS_MASK;
1798 return std::make_pair(TF & Mask, TF & ~Mask);
1801 ArrayRef<std::pair<unsigned, const char *>>
1802 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
1803 using namespace PPCII;
1804 static const std::pair<unsigned, const char *> TargetFlags[] = {
1807 {MO_TPREL_LO, "ppc-tprel-lo"},
1808 {MO_TPREL_HA, "ppc-tprel-ha"},
1809 {MO_DTPREL_LO, "ppc-dtprel-lo"},
1810 {MO_TLSLD_LO, "ppc-tlsld-lo"},
1811 {MO_TOC_LO, "ppc-toc-lo"},
1812 {MO_TLS, "ppc-tls"}};
1813 return makeArrayRef(TargetFlags);
1816 ArrayRef<std::pair<unsigned, const char *>>
1817 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
1818 using namespace PPCII;
1819 static const std::pair<unsigned, const char *> TargetFlags[] = {
1820 {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
1821 {MO_PIC_FLAG, "ppc-pic"},
1822 {MO_NLP_FLAG, "ppc-nlp"},
1823 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
1824 return makeArrayRef(TargetFlags);