1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
61 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
62 cl::desc("Use the old (incorrect) instruction latency calculation"));
64 // Pin the vtable to this file.
65 void PPCInstrInfo::anchor() {}
67 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
69 Subtarget(STI), RI(STI.getTargetMachine()) {}
71 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
72 /// this target when scheduling the DAG.
73 ScheduleHazardRecognizer *
74 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
75 const ScheduleDAG *DAG) const {
77 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
80 const InstrItineraryData *II =
81 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
82 return new ScoreboardHazardRecognizer(II, DAG);
85 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
88 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
89 /// to use for this target when scheduling the DAG.
90 ScheduleHazardRecognizer *
91 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
92 const ScheduleDAG *DAG) const {
94 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
96 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
97 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
99 // Most subtargets use a PPC970 recognizer.
100 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
101 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
102 assert(DAG->TII && "No InstrInfo?");
104 return new PPCHazardRecognizer970(*DAG);
107 return new ScoreboardHazardRecognizer(II, DAG);
110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
111 const MachineInstr *MI,
112 unsigned *PredCost) const {
113 if (!ItinData || UseOldLatencyCalc)
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 // The default implementation of getInstrLatency calls getStageLatency, but
117 // getStageLatency does not do the right thing for us. While we have
118 // itinerary, most cores are fully pipelined, and so the itineraries only
119 // express the first part of the pipeline, not every stage. Instead, we need
120 // to use the listed output operand cycle number (using operand 0 here, which
123 unsigned Latency = 1;
124 unsigned DefClass = MI->getDesc().getSchedClass();
125 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
126 const MachineOperand &MO = MI->getOperand(i);
127 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
130 int Cycle = ItinData->getOperandCycle(DefClass, i);
134 Latency = std::max(Latency, (unsigned) Cycle);
140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
141 const MachineInstr *DefMI, unsigned DefIdx,
142 const MachineInstr *UseMI,
143 unsigned UseIdx) const {
144 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
147 if (!DefMI->getParent())
150 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
151 unsigned Reg = DefMO.getReg();
154 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
155 const MachineRegisterInfo *MRI =
156 &DefMI->getParent()->getParent()->getRegInfo();
157 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
158 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
160 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
161 PPC::CRBITRCRegClass.contains(Reg);
164 if (UseMI->isBranch() && IsRegCR) {
166 Latency = getInstrLatency(ItinData, DefMI);
168 // On some cores, there is an additional delay between writing to a condition
169 // register, and using it from a branch.
170 unsigned Directive = Subtarget.getDarwinDirective();
192 static bool hasVirtualRegDefsInBasicBlock(const MachineInstr &Inst,
193 const MachineBasicBlock *MBB) {
194 const MachineOperand &Op1 = Inst.getOperand(1);
195 const MachineOperand &Op2 = Inst.getOperand(2);
196 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
198 // We need virtual register definitions.
199 MachineInstr *MI1 = nullptr;
200 MachineInstr *MI2 = nullptr;
201 if (Op1.isReg() && TargetRegisterInfo::isVirtualRegister(Op1.getReg()))
202 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
203 if (Op2.isReg() && TargetRegisterInfo::isVirtualRegister(Op2.getReg()))
204 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
206 // And they need to be in the trace (otherwise, they won't have a depth).
207 if (MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB)
213 static bool hasReassocSibling(const MachineInstr &Inst, bool &Commuted) {
214 const MachineBasicBlock *MBB = Inst.getParent();
215 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
216 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
217 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
218 unsigned AssocOpcode = Inst.getOpcode();
220 // If only one operand has the same opcode and it's the second source operand,
221 // the operands must be commuted.
222 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
226 // 1. The previous instruction must be the same type as Inst.
227 // 2. The previous instruction must have virtual register definitions for its
228 // operands in the same basic block as Inst.
229 // 3. The previous instruction's result must only be used by Inst.
230 if (MI1->getOpcode() == AssocOpcode &&
231 hasVirtualRegDefsInBasicBlock(*MI1, MBB) &&
232 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg()))
238 // This function does not list all associative and commutative operations, but
239 // only those worth feeding through the machine combiner in an attempt to
240 // reduce the critical path. Mostly, this means floating-point operations,
241 // because they have high latencies (compared to other operations, such and
242 // and/or, which are also associative and commutative, but have low latencies).
244 // The concept is that these operations can benefit from this kind of
255 // breaking the dependency between A and B, allowing them to be executed in
256 // parallel (or back-to-back in a pipeline) instead of depending on each other.
257 static bool isAssociativeAndCommutative(unsigned Opcode) {
291 /// Return true if the input instruction is part of a chain of dependent ops
292 /// that are suitable for reassociation, otherwise return false.
293 /// If the instruction's operands must be commuted to have a previous
294 /// instruction of the same type define the first source operand, Commuted will
296 static bool isReassocCandidate(const MachineInstr &Inst, bool &Commuted) {
297 // 1. The operation must be associative and commutative.
298 // 2. The instruction must have virtual register definitions for its
299 // operands in the same basic block.
300 // 3. The instruction must have a reassociable sibling.
301 if (isAssociativeAndCommutative(Inst.getOpcode()) &&
302 hasVirtualRegDefsInBasicBlock(Inst, Inst.getParent()) &&
303 hasReassocSibling(Inst, Commuted))
309 bool PPCInstrInfo::getMachineCombinerPatterns(MachineInstr &Root,
310 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Patterns) const {
311 // Using the machine combiner in this way is potentially expensive, so
312 // restrict to when aggressive optimizations are desired.
313 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
316 // FP reassociation is only legal when we don't need strict IEEE semantics.
317 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
320 // Look for this reassociation pattern:
324 // FIXME: We should also match FMA operations here, where we consider the
325 // 'part' of the FMA, either the addition or the multiplication, paired with
326 // an actual addition or multiplication.
329 if (isReassocCandidate(Root, Commute)) {
330 // We found a sequence of instructions that may be suitable for a
331 // reassociation of operands to increase ILP. Specify each commutation
332 // possibility for the Prev instruction in the sequence and let the
333 // machine combiner decide if changing the operands is worthwhile.
335 Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_YB);
336 Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_YB);
338 Patterns.push_back(MachineCombinerPattern::MC_REASSOC_AX_BY);
339 Patterns.push_back(MachineCombinerPattern::MC_REASSOC_XA_BY);
347 /// Attempt the following reassociation to reduce critical path length:
348 /// B = A op X (Prev)
349 /// C = B op Y (Root)
353 static void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
354 MachineCombinerPattern::MC_PATTERN Pattern,
355 SmallVectorImpl<MachineInstr *> &InsInstrs,
356 SmallVectorImpl<MachineInstr *> &DelInstrs,
357 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
358 MachineFunction *MF = Root.getParent()->getParent();
359 MachineRegisterInfo &MRI = MF->getRegInfo();
360 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
361 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
362 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
364 // This array encodes the operand index for each parameter because the
365 // operands may be commuted. Each row corresponds to a pattern value,
366 // and each column specifies the index of A, B, X, Y.
367 unsigned OpIdx[4][4] = {
374 MachineOperand &OpA = Prev.getOperand(OpIdx[Pattern][0]);
375 MachineOperand &OpB = Root.getOperand(OpIdx[Pattern][1]);
376 MachineOperand &OpX = Prev.getOperand(OpIdx[Pattern][2]);
377 MachineOperand &OpY = Root.getOperand(OpIdx[Pattern][3]);
378 MachineOperand &OpC = Root.getOperand(0);
380 unsigned RegA = OpA.getReg();
381 unsigned RegB = OpB.getReg();
382 unsigned RegX = OpX.getReg();
383 unsigned RegY = OpY.getReg();
384 unsigned RegC = OpC.getReg();
386 if (TargetRegisterInfo::isVirtualRegister(RegA))
387 MRI.constrainRegClass(RegA, RC);
388 if (TargetRegisterInfo::isVirtualRegister(RegB))
389 MRI.constrainRegClass(RegB, RC);
390 if (TargetRegisterInfo::isVirtualRegister(RegX))
391 MRI.constrainRegClass(RegX, RC);
392 if (TargetRegisterInfo::isVirtualRegister(RegY))
393 MRI.constrainRegClass(RegY, RC);
394 if (TargetRegisterInfo::isVirtualRegister(RegC))
395 MRI.constrainRegClass(RegC, RC);
397 // Create a new virtual register for the result of (X op Y) instead of
398 // recycling RegB because the MachineCombiner's computation of the critical
399 // path requires a new register definition rather than an existing one.
400 unsigned NewVR = MRI.createVirtualRegister(RC);
401 InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
403 unsigned Opcode = Root.getOpcode();
404 bool KillA = OpA.isKill();
405 bool KillX = OpX.isKill();
406 bool KillY = OpY.isKill();
408 // Create new instructions for insertion.
409 MachineInstrBuilder MIB1 =
410 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
411 .addReg(RegX, getKillRegState(KillX))
412 .addReg(RegY, getKillRegState(KillY));
413 InsInstrs.push_back(MIB1);
415 MachineInstrBuilder MIB2 =
416 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
417 .addReg(RegA, getKillRegState(KillA))
418 .addReg(NewVR, getKillRegState(true));
419 InsInstrs.push_back(MIB2);
421 // Record old instructions for deletion.
422 DelInstrs.push_back(&Prev);
423 DelInstrs.push_back(&Root);
426 void PPCInstrInfo::genAlternativeCodeSequence(
428 MachineCombinerPattern::MC_PATTERN Pattern,
429 SmallVectorImpl<MachineInstr *> &InsInstrs,
430 SmallVectorImpl<MachineInstr *> &DelInstrs,
431 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const {
432 MachineRegisterInfo &MRI = Root.getParent()->getParent()->getRegInfo();
434 // Select the previous instruction in the sequence based on the input pattern.
435 MachineInstr *Prev = nullptr;
437 case MachineCombinerPattern::MC_REASSOC_AX_BY:
438 case MachineCombinerPattern::MC_REASSOC_XA_BY:
439 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
441 case MachineCombinerPattern::MC_REASSOC_AX_YB:
442 case MachineCombinerPattern::MC_REASSOC_XA_YB:
443 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
445 assert(Prev && "Unknown pattern for machine combiner");
447 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
451 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
452 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
453 unsigned &SrcReg, unsigned &DstReg,
454 unsigned &SubIdx) const {
455 switch (MI.getOpcode()) {
456 default: return false;
458 case PPC::EXTSW_32_64:
459 SrcReg = MI.getOperand(1).getReg();
460 DstReg = MI.getOperand(0).getReg();
461 SubIdx = PPC::sub_32;
466 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
467 int &FrameIndex) const {
468 // Note: This list must be kept consistent with LoadRegFromStackSlot.
469 switch (MI->getOpcode()) {
475 case PPC::RESTORE_CR:
476 case PPC::RESTORE_CRBIT:
482 case PPC::RESTORE_VRSAVE:
483 // Check for the operands added by addFrameReference (the immediate is the
484 // offset which defaults to 0).
485 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
486 MI->getOperand(2).isFI()) {
487 FrameIndex = MI->getOperand(2).getIndex();
488 return MI->getOperand(0).getReg();
495 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
496 int &FrameIndex) const {
497 // Note: This list must be kept consistent with StoreRegToStackSlot.
498 switch (MI->getOpcode()) {
505 case PPC::SPILL_CRBIT:
511 case PPC::SPILL_VRSAVE:
512 // Check for the operands added by addFrameReference (the immediate is the
513 // offset which defaults to 0).
514 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
515 MI->getOperand(2).isFI()) {
516 FrameIndex = MI->getOperand(2).getIndex();
517 return MI->getOperand(0).getReg();
524 // commuteInstruction - We can commute rlwimi instructions, but only if the
525 // rotate amt is zero. We also have to munge the immediates a bit.
527 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
528 MachineFunction &MF = *MI->getParent()->getParent();
530 // Normal instructions can be commuted the obvious way.
531 if (MI->getOpcode() != PPC::RLWIMI &&
532 MI->getOpcode() != PPC::RLWIMIo)
533 return TargetInstrInfo::commuteInstruction(MI, NewMI);
534 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
535 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
536 // changing the relative order of the mask operands might change what happens
537 // to the high-bits of the mask (and, thus, the result).
539 // Cannot commute if it has a non-zero rotate count.
540 if (MI->getOperand(3).getImm() != 0)
543 // If we have a zero rotate count, we have:
545 // Op0 = (Op1 & ~M) | (Op2 & M)
547 // M = mask((ME+1)&31, (MB-1)&31)
548 // Op0 = (Op2 & ~M) | (Op1 & M)
551 unsigned Reg0 = MI->getOperand(0).getReg();
552 unsigned Reg1 = MI->getOperand(1).getReg();
553 unsigned Reg2 = MI->getOperand(2).getReg();
554 unsigned SubReg1 = MI->getOperand(1).getSubReg();
555 unsigned SubReg2 = MI->getOperand(2).getSubReg();
556 bool Reg1IsKill = MI->getOperand(1).isKill();
557 bool Reg2IsKill = MI->getOperand(2).isKill();
558 bool ChangeReg0 = false;
559 // If machine instrs are no longer in two-address forms, update
560 // destination register as well.
562 // Must be two address instruction!
563 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
564 "Expecting a two-address instruction!");
565 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
571 unsigned MB = MI->getOperand(4).getImm();
572 unsigned ME = MI->getOperand(5).getImm();
574 // We can't commute a trivial mask (there is no way to represent an all-zero
576 if (MB == 0 && ME == 31)
580 // Create a new instruction.
581 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
582 bool Reg0IsDead = MI->getOperand(0).isDead();
583 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
584 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
585 .addReg(Reg2, getKillRegState(Reg2IsKill))
586 .addReg(Reg1, getKillRegState(Reg1IsKill))
588 .addImm((MB-1) & 31);
592 MI->getOperand(0).setReg(Reg2);
593 MI->getOperand(0).setSubReg(SubReg2);
595 MI->getOperand(2).setReg(Reg1);
596 MI->getOperand(1).setReg(Reg2);
597 MI->getOperand(2).setSubReg(SubReg1);
598 MI->getOperand(1).setSubReg(SubReg2);
599 MI->getOperand(2).setIsKill(Reg1IsKill);
600 MI->getOperand(1).setIsKill(Reg2IsKill);
602 // Swap the mask around.
603 MI->getOperand(4).setImm((ME+1) & 31);
604 MI->getOperand(5).setImm((MB-1) & 31);
608 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
609 unsigned &SrcOpIdx2) const {
610 // For VSX A-Type FMA instructions, it is the first two operands that can be
611 // commuted, however, because the non-encoded tied input operand is listed
612 // first, the operands to swap are actually the second and third.
614 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
616 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
623 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
624 MachineBasicBlock::iterator MI) const {
625 // This function is used for scheduling, and the nop wanted here is the type
626 // that terminates dispatch groups on the POWER cores.
627 unsigned Directive = Subtarget.getDarwinDirective();
630 default: Opcode = PPC::NOP; break;
631 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
632 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
633 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
637 BuildMI(MBB, MI, DL, get(Opcode));
640 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
641 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
642 NopInst.setOpcode(PPC::NOP);
646 // Note: If the condition register is set to CTR or CTR8 then this is a
647 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
648 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
649 MachineBasicBlock *&FBB,
650 SmallVectorImpl<MachineOperand> &Cond,
651 bool AllowModify) const {
652 bool isPPC64 = Subtarget.isPPC64();
654 // If the block has no terminators, it just falls into the block after it.
655 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
659 if (!isUnpredicatedTerminator(I))
662 // Get the last instruction in the block.
663 MachineInstr *LastInst = I;
665 // If there is only one terminator instruction, process it.
666 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
667 if (LastInst->getOpcode() == PPC::B) {
668 if (!LastInst->getOperand(0).isMBB())
670 TBB = LastInst->getOperand(0).getMBB();
672 } else if (LastInst->getOpcode() == PPC::BCC) {
673 if (!LastInst->getOperand(2).isMBB())
675 // Block ends with fall-through condbranch.
676 TBB = LastInst->getOperand(2).getMBB();
677 Cond.push_back(LastInst->getOperand(0));
678 Cond.push_back(LastInst->getOperand(1));
680 } else if (LastInst->getOpcode() == PPC::BC) {
681 if (!LastInst->getOperand(1).isMBB())
683 // Block ends with fall-through condbranch.
684 TBB = LastInst->getOperand(1).getMBB();
685 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
686 Cond.push_back(LastInst->getOperand(0));
688 } else if (LastInst->getOpcode() == PPC::BCn) {
689 if (!LastInst->getOperand(1).isMBB())
691 // Block ends with fall-through condbranch.
692 TBB = LastInst->getOperand(1).getMBB();
693 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
694 Cond.push_back(LastInst->getOperand(0));
696 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
697 LastInst->getOpcode() == PPC::BDNZ) {
698 if (!LastInst->getOperand(0).isMBB())
700 if (DisableCTRLoopAnal)
702 TBB = LastInst->getOperand(0).getMBB();
703 Cond.push_back(MachineOperand::CreateImm(1));
704 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
707 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
708 LastInst->getOpcode() == PPC::BDZ) {
709 if (!LastInst->getOperand(0).isMBB())
711 if (DisableCTRLoopAnal)
713 TBB = LastInst->getOperand(0).getMBB();
714 Cond.push_back(MachineOperand::CreateImm(0));
715 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
720 // Otherwise, don't know what this is.
724 // Get the instruction before it if it's a terminator.
725 MachineInstr *SecondLastInst = I;
727 // If there are three terminators, we don't know what sort of block this is.
728 if (SecondLastInst && I != MBB.begin() &&
729 isUnpredicatedTerminator(--I))
732 // If the block ends with PPC::B and PPC:BCC, handle it.
733 if (SecondLastInst->getOpcode() == PPC::BCC &&
734 LastInst->getOpcode() == PPC::B) {
735 if (!SecondLastInst->getOperand(2).isMBB() ||
736 !LastInst->getOperand(0).isMBB())
738 TBB = SecondLastInst->getOperand(2).getMBB();
739 Cond.push_back(SecondLastInst->getOperand(0));
740 Cond.push_back(SecondLastInst->getOperand(1));
741 FBB = LastInst->getOperand(0).getMBB();
743 } else if (SecondLastInst->getOpcode() == PPC::BC &&
744 LastInst->getOpcode() == PPC::B) {
745 if (!SecondLastInst->getOperand(1).isMBB() ||
746 !LastInst->getOperand(0).isMBB())
748 TBB = SecondLastInst->getOperand(1).getMBB();
749 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
750 Cond.push_back(SecondLastInst->getOperand(0));
751 FBB = LastInst->getOperand(0).getMBB();
753 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
754 LastInst->getOpcode() == PPC::B) {
755 if (!SecondLastInst->getOperand(1).isMBB() ||
756 !LastInst->getOperand(0).isMBB())
758 TBB = SecondLastInst->getOperand(1).getMBB();
759 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
760 Cond.push_back(SecondLastInst->getOperand(0));
761 FBB = LastInst->getOperand(0).getMBB();
763 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
764 SecondLastInst->getOpcode() == PPC::BDNZ) &&
765 LastInst->getOpcode() == PPC::B) {
766 if (!SecondLastInst->getOperand(0).isMBB() ||
767 !LastInst->getOperand(0).isMBB())
769 if (DisableCTRLoopAnal)
771 TBB = SecondLastInst->getOperand(0).getMBB();
772 Cond.push_back(MachineOperand::CreateImm(1));
773 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
775 FBB = LastInst->getOperand(0).getMBB();
777 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
778 SecondLastInst->getOpcode() == PPC::BDZ) &&
779 LastInst->getOpcode() == PPC::B) {
780 if (!SecondLastInst->getOperand(0).isMBB() ||
781 !LastInst->getOperand(0).isMBB())
783 if (DisableCTRLoopAnal)
785 TBB = SecondLastInst->getOperand(0).getMBB();
786 Cond.push_back(MachineOperand::CreateImm(0));
787 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
789 FBB = LastInst->getOperand(0).getMBB();
793 // If the block ends with two PPC:Bs, handle it. The second one is not
794 // executed, so remove it.
795 if (SecondLastInst->getOpcode() == PPC::B &&
796 LastInst->getOpcode() == PPC::B) {
797 if (!SecondLastInst->getOperand(0).isMBB())
799 TBB = SecondLastInst->getOperand(0).getMBB();
802 I->eraseFromParent();
806 // Otherwise, can't handle this.
810 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
811 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
815 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
816 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
817 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
818 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
821 // Remove the branch.
822 I->eraseFromParent();
826 if (I == MBB.begin()) return 1;
828 if (I->getOpcode() != PPC::BCC &&
829 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
830 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
831 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
834 // Remove the branch.
835 I->eraseFromParent();
840 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
841 MachineBasicBlock *FBB,
842 ArrayRef<MachineOperand> Cond,
844 // Shouldn't be a fall through.
845 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
846 assert((Cond.size() == 2 || Cond.size() == 0) &&
847 "PPC branch conditions have two components!");
849 bool isPPC64 = Subtarget.isPPC64();
853 if (Cond.empty()) // Unconditional branch
854 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
855 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
856 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
857 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
858 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
859 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
860 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
861 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
862 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
863 else // Conditional branch
864 BuildMI(&MBB, DL, get(PPC::BCC))
865 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
869 // Two-way Conditional Branch.
870 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
871 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
872 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
873 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
874 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
875 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
876 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
877 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
879 BuildMI(&MBB, DL, get(PPC::BCC))
880 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
881 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
886 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
887 ArrayRef<MachineOperand> Cond,
888 unsigned TrueReg, unsigned FalseReg,
889 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
890 if (!Subtarget.hasISEL())
893 if (Cond.size() != 2)
896 // If this is really a bdnz-like condition, then it cannot be turned into a
898 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
901 // Check register classes.
902 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
903 const TargetRegisterClass *RC =
904 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
908 // isel is for regular integer GPRs only.
909 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
910 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
911 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
912 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
915 // FIXME: These numbers are for the A2, how well they work for other cores is
916 // an open question. On the A2, the isel instruction has a 2-cycle latency
917 // but single-cycle throughput. These numbers are used in combination with
918 // the MispredictPenalty setting from the active SchedMachineModel.
926 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
927 MachineBasicBlock::iterator MI, DebugLoc dl,
928 unsigned DestReg, ArrayRef<MachineOperand> Cond,
929 unsigned TrueReg, unsigned FalseReg) const {
930 assert(Cond.size() == 2 &&
931 "PPC branch conditions have two components!");
933 assert(Subtarget.hasISEL() &&
934 "Cannot insert select on target without ISEL support");
936 // Get the register classes.
937 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
938 const TargetRegisterClass *RC =
939 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
940 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
942 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
943 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
945 PPC::GPRCRegClass.hasSubClassEq(RC) ||
946 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
947 "isel is for regular integer GPRs only");
949 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
950 unsigned SelectPred = Cond[0].getImm();
954 switch (SelectPred) {
955 default: llvm_unreachable("invalid predicate for isel");
956 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
957 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
958 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
959 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
960 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
961 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
962 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
963 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
964 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
965 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
968 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
969 SecondReg = SwapOps ? TrueReg : FalseReg;
971 // The first input register of isel cannot be r0. If it is a member
972 // of a register class that can be r0, then copy it first (the
973 // register allocator should eliminate the copy).
974 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
975 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
976 const TargetRegisterClass *FirstRC =
977 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
978 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
979 unsigned OldFirstReg = FirstReg;
980 FirstReg = MRI.createVirtualRegister(FirstRC);
981 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
982 .addReg(OldFirstReg);
985 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
986 .addReg(FirstReg).addReg(SecondReg)
987 .addReg(Cond[1].getReg(), 0, SubIdx);
990 static unsigned getCRBitValue(unsigned CRBit) {
992 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
993 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
994 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
995 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
997 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
998 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
999 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
1000 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
1002 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
1003 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
1004 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
1005 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
1007 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
1008 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
1009 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
1010 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
1013 assert(Ret != 4 && "Invalid CR bit register");
1017 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1018 MachineBasicBlock::iterator I, DebugLoc DL,
1019 unsigned DestReg, unsigned SrcReg,
1020 bool KillSrc) const {
1021 // We can end up with self copies and similar things as a result of VSX copy
1022 // legalization. Promote them here.
1023 const TargetRegisterInfo *TRI = &getRegisterInfo();
1024 if (PPC::F8RCRegClass.contains(DestReg) &&
1025 PPC::VSRCRegClass.contains(SrcReg)) {
1027 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
1029 if (VSXSelfCopyCrash && SrcReg == SuperReg)
1030 llvm_unreachable("nop VSX copy");
1033 } else if (PPC::VRRCRegClass.contains(DestReg) &&
1034 PPC::VSRCRegClass.contains(SrcReg)) {
1036 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
1038 if (VSXSelfCopyCrash && SrcReg == SuperReg)
1039 llvm_unreachable("nop VSX copy");
1042 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
1043 PPC::VSRCRegClass.contains(DestReg)) {
1045 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
1047 if (VSXSelfCopyCrash && DestReg == SuperReg)
1048 llvm_unreachable("nop VSX copy");
1051 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
1052 PPC::VSRCRegClass.contains(DestReg)) {
1054 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
1056 if (VSXSelfCopyCrash && DestReg == SuperReg)
1057 llvm_unreachable("nop VSX copy");
1062 // Different class register copy
1063 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
1064 PPC::GPRCRegClass.contains(DestReg)) {
1065 unsigned CRReg = getCRFromCRBit(SrcReg);
1066 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
1067 .addReg(CRReg), getKillRegState(KillSrc);
1068 // Rotate the CR bit in the CR fields to be the least significant bit and
1069 // then mask with 0x1 (MB = ME = 31).
1070 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
1071 .addReg(DestReg, RegState::Kill)
1072 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
1076 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
1077 PPC::G8RCRegClass.contains(DestReg)) {
1078 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
1079 .addReg(SrcReg), getKillRegState(KillSrc);
1081 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
1082 PPC::GPRCRegClass.contains(DestReg)) {
1083 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
1084 .addReg(SrcReg), getKillRegState(KillSrc);
1089 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
1091 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
1093 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
1095 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
1097 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
1099 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
1100 // There are two different ways this can be done:
1101 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
1102 // issue in VSU pipeline 0.
1103 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
1104 // can go to either pipeline.
1105 // We'll always use xxlor here, because in practically all cases where
1106 // copies are generated, they are close enough to some use that the
1107 // lower-latency form is preferable.
1109 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
1110 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1112 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1114 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1116 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1118 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1121 llvm_unreachable("Impossible reg-to-reg copy");
1123 const MCInstrDesc &MCID = get(Opc);
1124 if (MCID.getNumOperands() == 3)
1125 BuildMI(MBB, I, DL, MCID, DestReg)
1126 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1128 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1131 // This function returns true if a CR spill is necessary and false otherwise.
1133 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
1134 unsigned SrcReg, bool isKill,
1136 const TargetRegisterClass *RC,
1137 SmallVectorImpl<MachineInstr*> &NewMIs,
1138 bool &NonRI, bool &SpillsVRS) const{
1139 // Note: If additional store instructions are added here,
1140 // update isStoreToStackSlot.
1143 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1144 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1145 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
1147 getKillRegState(isKill)),
1149 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1150 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1151 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
1153 getKillRegState(isKill)),
1155 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1156 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
1158 getKillRegState(isKill)),
1160 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1161 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
1163 getKillRegState(isKill)),
1165 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1166 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
1168 getKillRegState(isKill)),
1171 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1172 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
1174 getKillRegState(isKill)),
1177 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1178 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
1180 getKillRegState(isKill)),
1183 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1184 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
1186 getKillRegState(isKill)),
1189 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1190 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
1192 getKillRegState(isKill)),
1195 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1196 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
1198 getKillRegState(isKill)),
1201 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1202 assert(Subtarget.isDarwin() &&
1203 "VRSAVE only needs spill/restore on Darwin");
1204 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
1206 getKillRegState(isKill)),
1209 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1210 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
1212 getKillRegState(isKill)),
1215 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1216 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
1218 getKillRegState(isKill)),
1221 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1222 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
1224 getKillRegState(isKill)),
1228 llvm_unreachable("Unknown regclass!");
1235 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1236 MachineBasicBlock::iterator MI,
1237 unsigned SrcReg, bool isKill, int FrameIdx,
1238 const TargetRegisterClass *RC,
1239 const TargetRegisterInfo *TRI) const {
1240 MachineFunction &MF = *MBB.getParent();
1241 SmallVector<MachineInstr*, 4> NewMIs;
1243 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1244 FuncInfo->setHasSpills();
1246 bool NonRI = false, SpillsVRS = false;
1247 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1249 FuncInfo->setSpillsCR();
1252 FuncInfo->setSpillsVRSAVE();
1255 FuncInfo->setHasNonRISpills();
1257 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1258 MBB.insert(MI, NewMIs[i]);
1260 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1261 MachineMemOperand *MMO = MF.getMachineMemOperand(
1262 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1263 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1264 MFI.getObjectAlignment(FrameIdx));
1265 NewMIs.back()->addMemOperand(MF, MMO);
1269 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
1270 unsigned DestReg, int FrameIdx,
1271 const TargetRegisterClass *RC,
1272 SmallVectorImpl<MachineInstr*> &NewMIs,
1273 bool &NonRI, bool &SpillsVRS) const{
1274 // Note: If additional load instructions are added here,
1275 // update isLoadFromStackSlot.
1277 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1278 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1279 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
1280 DestReg), FrameIdx));
1281 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1282 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1283 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
1285 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1286 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
1288 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1289 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
1291 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1292 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1293 get(PPC::RESTORE_CR), DestReg),
1296 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1297 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1298 get(PPC::RESTORE_CRBIT), DestReg),
1301 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1302 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1305 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1306 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1309 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1310 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1313 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1314 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1317 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1318 assert(Subtarget.isDarwin() &&
1319 "VRSAVE only needs spill/restore on Darwin");
1320 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1321 get(PPC::RESTORE_VRSAVE),
1325 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1326 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1329 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1330 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1333 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1334 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1338 llvm_unreachable("Unknown regclass!");
1345 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1346 MachineBasicBlock::iterator MI,
1347 unsigned DestReg, int FrameIdx,
1348 const TargetRegisterClass *RC,
1349 const TargetRegisterInfo *TRI) const {
1350 MachineFunction &MF = *MBB.getParent();
1351 SmallVector<MachineInstr*, 4> NewMIs;
1353 if (MI != MBB.end()) DL = MI->getDebugLoc();
1355 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1356 FuncInfo->setHasSpills();
1358 bool NonRI = false, SpillsVRS = false;
1359 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1361 FuncInfo->setSpillsCR();
1364 FuncInfo->setSpillsVRSAVE();
1367 FuncInfo->setHasNonRISpills();
1369 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1370 MBB.insert(MI, NewMIs[i]);
1372 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1373 MachineMemOperand *MMO = MF.getMachineMemOperand(
1374 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1375 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1376 MFI.getObjectAlignment(FrameIdx));
1377 NewMIs.back()->addMemOperand(MF, MMO);
1381 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1382 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1383 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1384 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1386 // Leave the CR# the same, but invert the condition.
1387 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1391 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1392 unsigned Reg, MachineRegisterInfo *MRI) const {
1393 // For some instructions, it is legal to fold ZERO into the RA register field.
1394 // A zero immediate should always be loaded with a single li.
1395 unsigned DefOpc = DefMI->getOpcode();
1396 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1398 if (!DefMI->getOperand(1).isImm())
1400 if (DefMI->getOperand(1).getImm() != 0)
1403 // Note that we cannot here invert the arguments of an isel in order to fold
1404 // a ZERO into what is presented as the second argument. All we have here
1405 // is the condition bit, and that might come from a CR-logical bit operation.
1407 const MCInstrDesc &UseMCID = UseMI->getDesc();
1409 // Only fold into real machine instructions.
1410 if (UseMCID.isPseudo())
1414 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1415 if (UseMI->getOperand(UseIdx).isReg() &&
1416 UseMI->getOperand(UseIdx).getReg() == Reg)
1419 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1420 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1422 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1424 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1425 // register (which might also be specified as a pointer class kind).
1426 if (UseInfo->isLookupPtrRegClass()) {
1427 if (UseInfo->RegClass /* Kind */ != 1)
1430 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1431 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1435 // Make sure this is not tied to an output register (or otherwise
1436 // constrained). This is true for ST?UX registers, for example, which
1437 // are tied to their output registers.
1438 if (UseInfo->Constraints != 0)
1442 if (UseInfo->isLookupPtrRegClass()) {
1443 bool isPPC64 = Subtarget.isPPC64();
1444 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1446 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1447 PPC::ZERO8 : PPC::ZERO;
1450 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1451 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1454 DefMI->eraseFromParent();
1459 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1460 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1462 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1467 // We should make sure that, if we're going to predicate both sides of a
1468 // condition (a diamond), that both sides don't define the counter register. We
1469 // can predicate counter-decrement-based branches, but while that predicates
1470 // the branching, it does not predicate the counter decrement. If we tried to
1471 // merge the triangle into one predicated block, we'd decrement the counter
1473 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1474 unsigned NumT, unsigned ExtraT,
1475 MachineBasicBlock &FMBB,
1476 unsigned NumF, unsigned ExtraF,
1477 const BranchProbability &Probability) const {
1478 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1482 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1483 // The predicated branches are identified by their type, not really by the
1484 // explicit presence of a predicate. Furthermore, some of them can be
1485 // predicated more than once. Because if conversion won't try to predicate
1486 // any instruction which already claims to be predicated (by returning true
1487 // here), always return false. In doing so, we let isPredicable() be the
1488 // final word on whether not the instruction can be (further) predicated.
1493 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1494 if (!MI->isTerminator())
1497 // Conditional branch is a special case.
1498 if (MI->isBranch() && !MI->isBarrier())
1501 return !isPredicated(MI);
1504 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1505 ArrayRef<MachineOperand> Pred) const {
1506 unsigned OpC = MI->getOpcode();
1507 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1508 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1509 bool isPPC64 = Subtarget.isPPC64();
1510 MI->setDesc(get(Pred[0].getImm() ?
1511 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1512 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1513 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1514 MI->setDesc(get(PPC::BCLR));
1515 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1516 .addReg(Pred[1].getReg());
1517 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1518 MI->setDesc(get(PPC::BCLRn));
1519 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1520 .addReg(Pred[1].getReg());
1522 MI->setDesc(get(PPC::BCCLR));
1523 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1524 .addImm(Pred[0].getImm())
1525 .addReg(Pred[1].getReg());
1529 } else if (OpC == PPC::B) {
1530 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1531 bool isPPC64 = Subtarget.isPPC64();
1532 MI->setDesc(get(Pred[0].getImm() ?
1533 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1534 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1535 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1536 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1537 MI->RemoveOperand(0);
1539 MI->setDesc(get(PPC::BC));
1540 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1541 .addReg(Pred[1].getReg())
1543 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1544 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1545 MI->RemoveOperand(0);
1547 MI->setDesc(get(PPC::BCn));
1548 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1549 .addReg(Pred[1].getReg())
1552 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1553 MI->RemoveOperand(0);
1555 MI->setDesc(get(PPC::BCC));
1556 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1557 .addImm(Pred[0].getImm())
1558 .addReg(Pred[1].getReg())
1563 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1564 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1565 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1566 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1568 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1569 bool isPPC64 = Subtarget.isPPC64();
1571 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1572 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1573 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1574 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1575 .addReg(Pred[1].getReg());
1577 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1578 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1579 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1580 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1581 .addReg(Pred[1].getReg());
1585 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1586 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1587 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1588 .addImm(Pred[0].getImm())
1589 .addReg(Pred[1].getReg());
1596 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1597 ArrayRef<MachineOperand> Pred2) const {
1598 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1599 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1601 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1603 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1606 // P1 can only subsume P2 if they test the same condition register.
1607 if (Pred1[1].getReg() != Pred2[1].getReg())
1610 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1611 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1616 // Does P1 subsume P2, e.g. GE subsumes GT.
1617 if (P1 == PPC::PRED_LE &&
1618 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1620 if (P1 == PPC::PRED_GE &&
1621 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1627 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1628 std::vector<MachineOperand> &Pred) const {
1629 // Note: At the present time, the contents of Pred from this function is
1630 // unused by IfConversion. This implementation follows ARM by pushing the
1631 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1632 // predicate, instructions defining CTR or CTR8 are also included as
1633 // predicate-defining instructions.
1635 const TargetRegisterClass *RCs[] =
1636 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1637 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1640 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1641 const MachineOperand &MO = MI->getOperand(i);
1642 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1643 const TargetRegisterClass *RC = RCs[c];
1645 if (MO.isDef() && RC->contains(MO.getReg())) {
1649 } else if (MO.isRegMask()) {
1650 for (TargetRegisterClass::iterator I = RC->begin(),
1651 IE = RC->end(); I != IE; ++I)
1652 if (MO.clobbersPhysReg(*I)) {
1663 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1664 unsigned OpC = MI->getOpcode();
1679 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1680 unsigned &SrcReg, unsigned &SrcReg2,
1681 int &Mask, int &Value) const {
1682 unsigned Opc = MI->getOpcode();
1685 default: return false;
1690 SrcReg = MI->getOperand(1).getReg();
1692 Value = MI->getOperand(2).getImm();
1701 SrcReg = MI->getOperand(1).getReg();
1702 SrcReg2 = MI->getOperand(2).getReg();
1707 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1708 unsigned SrcReg, unsigned SrcReg2,
1709 int Mask, int Value,
1710 const MachineRegisterInfo *MRI) const {
1714 int OpC = CmpInstr->getOpcode();
1715 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1717 // FP record forms set CR1 based on the execption status bits, not a
1718 // comparison with zero.
1719 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1722 // The record forms set the condition register based on a signed comparison
1723 // with zero (so says the ISA manual). This is not as straightforward as it
1724 // seems, however, because this is always a 64-bit comparison on PPC64, even
1725 // for instructions that are 32-bit in nature (like slw for example).
1726 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1727 // for equality checks (as those don't depend on the sign). On PPC64,
1728 // we are restricted to equality for unsigned 64-bit comparisons and for
1729 // signed 32-bit comparisons the applicability is more restricted.
1730 bool isPPC64 = Subtarget.isPPC64();
1731 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1732 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1733 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1735 // Get the unique definition of SrcReg.
1736 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1737 if (!MI) return false;
1738 int MIOpC = MI->getOpcode();
1740 bool equalityOnly = false;
1743 if (is32BitSignedCompare) {
1744 // We can perform this optimization only if MI is sign-extending.
1745 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1746 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1747 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1748 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1749 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1753 } else if (is32BitUnsignedCompare) {
1754 // We can perform this optimization, equality only, if MI is
1756 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1757 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1758 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1760 equalityOnly = true;
1764 equalityOnly = is64BitUnsignedCompare;
1766 equalityOnly = is32BitUnsignedCompare;
1769 // We need to check the uses of the condition register in order to reject
1770 // non-equality comparisons.
1771 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1772 IE = MRI->use_instr_end(); I != IE; ++I) {
1773 MachineInstr *UseMI = &*I;
1774 if (UseMI->getOpcode() == PPC::BCC) {
1775 unsigned Pred = UseMI->getOperand(0).getImm();
1776 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1778 } else if (UseMI->getOpcode() == PPC::ISEL ||
1779 UseMI->getOpcode() == PPC::ISEL8) {
1780 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1781 if (SubIdx != PPC::sub_eq)
1788 MachineBasicBlock::iterator I = CmpInstr;
1790 // Scan forward to find the first use of the compare.
1791 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1793 bool FoundUse = false;
1794 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1795 JE = MRI->use_instr_end(); J != JE; ++J)
1805 // There are two possible candidates which can be changed to set CR[01].
1806 // One is MI, the other is a SUB instruction.
1807 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1808 MachineInstr *Sub = nullptr;
1810 // MI is not a candidate for CMPrr.
1812 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1813 // same BB as the comparison. This is to allow the check below to avoid calls
1814 // (and other explicit clobbers); instead we should really check for these
1815 // more explicitly (in at least a few predecessors).
1816 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1817 // PPC does not have a record-form SUBri.
1822 const TargetRegisterInfo *TRI = &getRegisterInfo();
1825 // Get ready to iterate backward from CmpInstr.
1826 MachineBasicBlock::iterator E = MI,
1827 B = CmpInstr->getParent()->begin();
1829 for (; I != E && !noSub; --I) {
1830 const MachineInstr &Instr = *I;
1831 unsigned IOpC = Instr.getOpcode();
1833 if (&*I != CmpInstr && (
1834 Instr.modifiesRegister(PPC::CR0, TRI) ||
1835 Instr.readsRegister(PPC::CR0, TRI)))
1836 // This instruction modifies or uses the record condition register after
1837 // the one we want to change. While we could do this transformation, it
1838 // would likely not be profitable. This transformation removes one
1839 // instruction, and so even forcing RA to generate one move probably
1840 // makes it unprofitable.
1843 // Check whether CmpInstr can be made redundant by the current instruction.
1844 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1845 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1846 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1847 ((Instr.getOperand(1).getReg() == SrcReg &&
1848 Instr.getOperand(2).getReg() == SrcReg2) ||
1849 (Instr.getOperand(1).getReg() == SrcReg2 &&
1850 Instr.getOperand(2).getReg() == SrcReg))) {
1856 // The 'and' is below the comparison instruction.
1860 // Return false if no candidates exist.
1864 // The single candidate is called MI.
1868 MIOpC = MI->getOpcode();
1869 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1872 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1873 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1877 // FIXME: On the non-embedded POWER architectures, only some of the record
1878 // forms are fast, and we should use only the fast ones.
1880 // The defining instruction has a record form (or is already a record
1881 // form). It is possible, however, that we'll need to reverse the condition
1882 // code of the users.
1886 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1887 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1889 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1890 // needs to be updated to be based on SUB. Push the condition code
1891 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1892 // condition code of these operands will be modified.
1893 bool ShouldSwap = false;
1895 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1896 Sub->getOperand(2).getReg() == SrcReg;
1898 // The operands to subf are the opposite of sub, so only in the fixed-point
1899 // case, invert the order.
1900 ShouldSwap = !ShouldSwap;
1904 for (MachineRegisterInfo::use_instr_iterator
1905 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1907 MachineInstr *UseMI = &*I;
1908 if (UseMI->getOpcode() == PPC::BCC) {
1909 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1910 assert((!equalityOnly ||
1911 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1912 "Invalid predicate for equality-only optimization");
1913 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1914 PPC::getSwappedPredicate(Pred)));
1915 } else if (UseMI->getOpcode() == PPC::ISEL ||
1916 UseMI->getOpcode() == PPC::ISEL8) {
1917 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1918 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1919 "Invalid CR bit for equality-only optimization");
1921 if (NewSubReg == PPC::sub_lt)
1922 NewSubReg = PPC::sub_gt;
1923 else if (NewSubReg == PPC::sub_gt)
1924 NewSubReg = PPC::sub_lt;
1926 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1928 } else // We need to abort on a user we don't understand.
1932 // Create a new virtual register to hold the value of the CR set by the
1933 // record-form instruction. If the instruction was not previously in
1934 // record form, then set the kill flag on the CR.
1935 CmpInstr->eraseFromParent();
1937 MachineBasicBlock::iterator MII = MI;
1938 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1939 get(TargetOpcode::COPY), CRReg)
1940 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1942 if (MIOpC != NewOpC) {
1943 // We need to be careful here: we're replacing one instruction with
1944 // another, and we need to make sure that we get all of the right
1945 // implicit uses and defs. On the other hand, the caller may be holding
1946 // an iterator to this instruction, and so we can't delete it (this is
1947 // specifically the case if this is the instruction directly after the
1950 const MCInstrDesc &NewDesc = get(NewOpC);
1951 MI->setDesc(NewDesc);
1953 if (NewDesc.ImplicitDefs)
1954 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1955 *ImpDefs; ++ImpDefs)
1956 if (!MI->definesRegister(*ImpDefs))
1957 MI->addOperand(*MI->getParent()->getParent(),
1958 MachineOperand::CreateReg(*ImpDefs, true, true));
1959 if (NewDesc.ImplicitUses)
1960 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1961 *ImpUses; ++ImpUses)
1962 if (!MI->readsRegister(*ImpUses))
1963 MI->addOperand(*MI->getParent()->getParent(),
1964 MachineOperand::CreateReg(*ImpUses, false, true));
1967 // Modify the condition code of operands in OperandsToUpdate.
1968 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1969 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1970 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1971 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1973 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1974 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1979 /// GetInstSize - Return the number of bytes of code the specified
1980 /// instruction may be. This returns the maximum number of bytes.
1982 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1983 unsigned Opcode = MI->getOpcode();
1985 if (Opcode == PPC::INLINEASM) {
1986 const MachineFunction *MF = MI->getParent()->getParent();
1987 const char *AsmStr = MI->getOperand(0).getSymbolName();
1988 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1989 } else if (Opcode == TargetOpcode::STACKMAP) {
1990 return MI->getOperand(1).getImm();
1991 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1992 PatchPointOpers Opers(MI);
1993 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1995 const MCInstrDesc &Desc = get(Opcode);
1996 return Desc.getSize();
2000 std::pair<unsigned, unsigned>
2001 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2002 const unsigned Mask = PPCII::MO_ACCESS_MASK;
2003 return std::make_pair(TF & Mask, TF & ~Mask);
2006 ArrayRef<std::pair<unsigned, const char *>>
2007 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2008 using namespace PPCII;
2009 static const std::pair<unsigned, const char *> TargetFlags[] = {
2012 {MO_TPREL_LO, "ppc-tprel-lo"},
2013 {MO_TPREL_HA, "ppc-tprel-ha"},
2014 {MO_DTPREL_LO, "ppc-dtprel-lo"},
2015 {MO_TLSLD_LO, "ppc-tlsld-lo"},
2016 {MO_TOC_LO, "ppc-toc-lo"},
2017 {MO_TLS, "ppc-tls"}};
2018 return makeArrayRef(TargetFlags);
2021 ArrayRef<std::pair<unsigned, const char *>>
2022 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2023 using namespace PPCII;
2024 static const std::pair<unsigned, const char *> TargetFlags[] = {
2025 {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
2026 {MO_PIC_FLAG, "ppc-pic"},
2027 {MO_NLP_FLAG, "ppc-nlp"},
2028 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2029 return makeArrayRef(TargetFlags);