1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/CodeGen/ScheduleDAG.h"
31 #include "llvm/CodeGen/SlotIndexes.h"
32 #include "llvm/CodeGen/StackMaps.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
43 #define DEBUG_TYPE "ppc-instr-info"
45 #define GET_INSTRMAP_INFO
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "PPCGenInstrInfo.inc"
50 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
51 cl::desc("Disable analysis for CTR loops"));
53 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
54 cl::desc("Disable compare instruction optimization"), cl::Hidden);
56 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
57 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
60 // Pin the vtable to this file.
61 void PPCInstrInfo::anchor() {}
63 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
64 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
65 Subtarget(STI), RI(STI.getTargetMachine()) {}
67 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
68 /// this target when scheduling the DAG.
69 ScheduleHazardRecognizer *
70 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
71 const ScheduleDAG *DAG) const {
73 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
74 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
75 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
76 const InstrItineraryData *II =
77 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
78 return new ScoreboardHazardRecognizer(II, DAG);
81 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
84 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
85 /// to use for this target when scheduling the DAG.
86 ScheduleHazardRecognizer *
87 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
88 const ScheduleDAG *DAG) const {
90 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
92 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
93 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
95 // Most subtargets use a PPC970 recognizer.
96 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
97 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
98 assert(DAG->TII && "No InstrInfo?");
100 return new PPCHazardRecognizer970(*DAG);
103 return new ScoreboardHazardRecognizer(II, DAG);
107 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
108 const MachineInstr *DefMI, unsigned DefIdx,
109 const MachineInstr *UseMI,
110 unsigned UseIdx) const {
111 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
114 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
115 unsigned Reg = DefMO.getReg();
118 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
119 const MachineRegisterInfo *MRI =
120 &DefMI->getParent()->getParent()->getRegInfo();
121 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
122 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
124 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
125 PPC::CRBITRCRegClass.contains(Reg);
128 if (UseMI->isBranch() && IsRegCR) {
130 Latency = getInstrLatency(ItinData, DefMI);
132 // On some cores, there is an additional delay between writing to a condition
133 // register, and using it from a branch.
134 unsigned Directive = Subtarget.getDarwinDirective();
156 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
157 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
158 unsigned &SrcReg, unsigned &DstReg,
159 unsigned &SubIdx) const {
160 switch (MI.getOpcode()) {
161 default: return false;
163 case PPC::EXTSW_32_64:
164 SrcReg = MI.getOperand(1).getReg();
165 DstReg = MI.getOperand(0).getReg();
166 SubIdx = PPC::sub_32;
171 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
172 int &FrameIndex) const {
173 // Note: This list must be kept consistent with LoadRegFromStackSlot.
174 switch (MI->getOpcode()) {
180 case PPC::RESTORE_CR:
181 case PPC::RESTORE_CRBIT:
187 case PPC::RESTORE_VRSAVE:
188 // Check for the operands added by addFrameReference (the immediate is the
189 // offset which defaults to 0).
190 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
191 MI->getOperand(2).isFI()) {
192 FrameIndex = MI->getOperand(2).getIndex();
193 return MI->getOperand(0).getReg();
200 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
201 int &FrameIndex) const {
202 // Note: This list must be kept consistent with StoreRegToStackSlot.
203 switch (MI->getOpcode()) {
210 case PPC::SPILL_CRBIT:
216 case PPC::SPILL_VRSAVE:
217 // Check for the operands added by addFrameReference (the immediate is the
218 // offset which defaults to 0).
219 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
220 MI->getOperand(2).isFI()) {
221 FrameIndex = MI->getOperand(2).getIndex();
222 return MI->getOperand(0).getReg();
229 // commuteInstruction - We can commute rlwimi instructions, but only if the
230 // rotate amt is zero. We also have to munge the immediates a bit.
232 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
233 MachineFunction &MF = *MI->getParent()->getParent();
235 // Normal instructions can be commuted the obvious way.
236 if (MI->getOpcode() != PPC::RLWIMI &&
237 MI->getOpcode() != PPC::RLWIMIo)
238 return TargetInstrInfo::commuteInstruction(MI, NewMI);
239 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
240 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
241 // changing the relative order of the mask operands might change what happens
242 // to the high-bits of the mask (and, thus, the result).
244 // Cannot commute if it has a non-zero rotate count.
245 if (MI->getOperand(3).getImm() != 0)
248 // If we have a zero rotate count, we have:
250 // Op0 = (Op1 & ~M) | (Op2 & M)
252 // M = mask((ME+1)&31, (MB-1)&31)
253 // Op0 = (Op2 & ~M) | (Op1 & M)
256 unsigned Reg0 = MI->getOperand(0).getReg();
257 unsigned Reg1 = MI->getOperand(1).getReg();
258 unsigned Reg2 = MI->getOperand(2).getReg();
259 unsigned SubReg1 = MI->getOperand(1).getSubReg();
260 unsigned SubReg2 = MI->getOperand(2).getSubReg();
261 bool Reg1IsKill = MI->getOperand(1).isKill();
262 bool Reg2IsKill = MI->getOperand(2).isKill();
263 bool ChangeReg0 = false;
264 // If machine instrs are no longer in two-address forms, update
265 // destination register as well.
267 // Must be two address instruction!
268 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
269 "Expecting a two-address instruction!");
270 assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
276 unsigned MB = MI->getOperand(4).getImm();
277 unsigned ME = MI->getOperand(5).getImm();
280 // Create a new instruction.
281 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
282 bool Reg0IsDead = MI->getOperand(0).isDead();
283 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
284 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
285 .addReg(Reg2, getKillRegState(Reg2IsKill))
286 .addReg(Reg1, getKillRegState(Reg1IsKill))
288 .addImm((MB-1) & 31);
292 MI->getOperand(0).setReg(Reg2);
293 MI->getOperand(0).setSubReg(SubReg2);
295 MI->getOperand(2).setReg(Reg1);
296 MI->getOperand(1).setReg(Reg2);
297 MI->getOperand(2).setSubReg(SubReg1);
298 MI->getOperand(1).setSubReg(SubReg2);
299 MI->getOperand(2).setIsKill(Reg1IsKill);
300 MI->getOperand(1).setIsKill(Reg2IsKill);
302 // Swap the mask around.
303 MI->getOperand(4).setImm((ME+1) & 31);
304 MI->getOperand(5).setImm((MB-1) & 31);
308 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
309 unsigned &SrcOpIdx2) const {
310 // For VSX A-Type FMA instructions, it is the first two operands that can be
311 // commuted, however, because the non-encoded tied input operand is listed
312 // first, the operands to swap are actually the second and third.
314 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
316 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
323 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator MI) const {
325 // This function is used for scheduling, and the nop wanted here is the type
326 // that terminates dispatch groups on the POWER cores.
327 unsigned Directive = Subtarget.getDarwinDirective();
330 default: Opcode = PPC::NOP; break;
331 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
332 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
333 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
337 BuildMI(MBB, MI, DL, get(Opcode));
340 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
341 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
342 NopInst.setOpcode(PPC::NOP);
346 // Note: If the condition register is set to CTR or CTR8 then this is a
347 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
348 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
349 MachineBasicBlock *&FBB,
350 SmallVectorImpl<MachineOperand> &Cond,
351 bool AllowModify) const {
352 bool isPPC64 = Subtarget.isPPC64();
354 // If the block has no terminators, it just falls into the block after it.
355 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
359 if (!isUnpredicatedTerminator(I))
362 // Get the last instruction in the block.
363 MachineInstr *LastInst = I;
365 // If there is only one terminator instruction, process it.
366 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
367 if (LastInst->getOpcode() == PPC::B) {
368 if (!LastInst->getOperand(0).isMBB())
370 TBB = LastInst->getOperand(0).getMBB();
372 } else if (LastInst->getOpcode() == PPC::BCC) {
373 if (!LastInst->getOperand(2).isMBB())
375 // Block ends with fall-through condbranch.
376 TBB = LastInst->getOperand(2).getMBB();
377 Cond.push_back(LastInst->getOperand(0));
378 Cond.push_back(LastInst->getOperand(1));
380 } else if (LastInst->getOpcode() == PPC::BC) {
381 if (!LastInst->getOperand(1).isMBB())
383 // Block ends with fall-through condbranch.
384 TBB = LastInst->getOperand(1).getMBB();
385 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
386 Cond.push_back(LastInst->getOperand(0));
388 } else if (LastInst->getOpcode() == PPC::BCn) {
389 if (!LastInst->getOperand(1).isMBB())
391 // Block ends with fall-through condbranch.
392 TBB = LastInst->getOperand(1).getMBB();
393 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
394 Cond.push_back(LastInst->getOperand(0));
396 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
397 LastInst->getOpcode() == PPC::BDNZ) {
398 if (!LastInst->getOperand(0).isMBB())
400 if (DisableCTRLoopAnal)
402 TBB = LastInst->getOperand(0).getMBB();
403 Cond.push_back(MachineOperand::CreateImm(1));
404 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
407 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
408 LastInst->getOpcode() == PPC::BDZ) {
409 if (!LastInst->getOperand(0).isMBB())
411 if (DisableCTRLoopAnal)
413 TBB = LastInst->getOperand(0).getMBB();
414 Cond.push_back(MachineOperand::CreateImm(0));
415 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
420 // Otherwise, don't know what this is.
424 // Get the instruction before it if it's a terminator.
425 MachineInstr *SecondLastInst = I;
427 // If there are three terminators, we don't know what sort of block this is.
428 if (SecondLastInst && I != MBB.begin() &&
429 isUnpredicatedTerminator(--I))
432 // If the block ends with PPC::B and PPC:BCC, handle it.
433 if (SecondLastInst->getOpcode() == PPC::BCC &&
434 LastInst->getOpcode() == PPC::B) {
435 if (!SecondLastInst->getOperand(2).isMBB() ||
436 !LastInst->getOperand(0).isMBB())
438 TBB = SecondLastInst->getOperand(2).getMBB();
439 Cond.push_back(SecondLastInst->getOperand(0));
440 Cond.push_back(SecondLastInst->getOperand(1));
441 FBB = LastInst->getOperand(0).getMBB();
443 } else if (SecondLastInst->getOpcode() == PPC::BC &&
444 LastInst->getOpcode() == PPC::B) {
445 if (!SecondLastInst->getOperand(1).isMBB() ||
446 !LastInst->getOperand(0).isMBB())
448 TBB = SecondLastInst->getOperand(1).getMBB();
449 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
450 Cond.push_back(SecondLastInst->getOperand(0));
451 FBB = LastInst->getOperand(0).getMBB();
453 } else if (SecondLastInst->getOpcode() == PPC::BCn &&
454 LastInst->getOpcode() == PPC::B) {
455 if (!SecondLastInst->getOperand(1).isMBB() ||
456 !LastInst->getOperand(0).isMBB())
458 TBB = SecondLastInst->getOperand(1).getMBB();
459 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
460 Cond.push_back(SecondLastInst->getOperand(0));
461 FBB = LastInst->getOperand(0).getMBB();
463 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
464 SecondLastInst->getOpcode() == PPC::BDNZ) &&
465 LastInst->getOpcode() == PPC::B) {
466 if (!SecondLastInst->getOperand(0).isMBB() ||
467 !LastInst->getOperand(0).isMBB())
469 if (DisableCTRLoopAnal)
471 TBB = SecondLastInst->getOperand(0).getMBB();
472 Cond.push_back(MachineOperand::CreateImm(1));
473 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
475 FBB = LastInst->getOperand(0).getMBB();
477 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
478 SecondLastInst->getOpcode() == PPC::BDZ) &&
479 LastInst->getOpcode() == PPC::B) {
480 if (!SecondLastInst->getOperand(0).isMBB() ||
481 !LastInst->getOperand(0).isMBB())
483 if (DisableCTRLoopAnal)
485 TBB = SecondLastInst->getOperand(0).getMBB();
486 Cond.push_back(MachineOperand::CreateImm(0));
487 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
489 FBB = LastInst->getOperand(0).getMBB();
493 // If the block ends with two PPC:Bs, handle it. The second one is not
494 // executed, so remove it.
495 if (SecondLastInst->getOpcode() == PPC::B &&
496 LastInst->getOpcode() == PPC::B) {
497 if (!SecondLastInst->getOperand(0).isMBB())
499 TBB = SecondLastInst->getOperand(0).getMBB();
502 I->eraseFromParent();
506 // Otherwise, can't handle this.
510 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
511 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
515 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
516 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
517 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
518 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
521 // Remove the branch.
522 I->eraseFromParent();
526 if (I == MBB.begin()) return 1;
528 if (I->getOpcode() != PPC::BCC &&
529 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
530 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
531 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
534 // Remove the branch.
535 I->eraseFromParent();
540 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
541 MachineBasicBlock *FBB,
542 ArrayRef<MachineOperand> Cond,
544 // Shouldn't be a fall through.
545 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
546 assert((Cond.size() == 2 || Cond.size() == 0) &&
547 "PPC branch conditions have two components!");
549 bool isPPC64 = Subtarget.isPPC64();
553 if (Cond.empty()) // Unconditional branch
554 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
555 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
556 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
557 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
558 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
559 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
560 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
561 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
562 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
563 else // Conditional branch
564 BuildMI(&MBB, DL, get(PPC::BCC))
565 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
569 // Two-way Conditional Branch.
570 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
571 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
572 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
573 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
574 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
575 BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
576 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
577 BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
579 BuildMI(&MBB, DL, get(PPC::BCC))
580 .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
581 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
586 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
587 ArrayRef<MachineOperand> Cond,
588 unsigned TrueReg, unsigned FalseReg,
589 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
590 if (!Subtarget.hasISEL())
593 if (Cond.size() != 2)
596 // If this is really a bdnz-like condition, then it cannot be turned into a
598 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
601 // Check register classes.
602 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
603 const TargetRegisterClass *RC =
604 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
608 // isel is for regular integer GPRs only.
609 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
610 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
611 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
612 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
615 // FIXME: These numbers are for the A2, how well they work for other cores is
616 // an open question. On the A2, the isel instruction has a 2-cycle latency
617 // but single-cycle throughput. These numbers are used in combination with
618 // the MispredictPenalty setting from the active SchedMachineModel.
626 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
627 MachineBasicBlock::iterator MI, DebugLoc dl,
628 unsigned DestReg, ArrayRef<MachineOperand> Cond,
629 unsigned TrueReg, unsigned FalseReg) const {
630 assert(Cond.size() == 2 &&
631 "PPC branch conditions have two components!");
633 assert(Subtarget.hasISEL() &&
634 "Cannot insert select on target without ISEL support");
636 // Get the register classes.
637 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
638 const TargetRegisterClass *RC =
639 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
640 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
642 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
643 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
645 PPC::GPRCRegClass.hasSubClassEq(RC) ||
646 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
647 "isel is for regular integer GPRs only");
649 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
650 unsigned SelectPred = Cond[0].getImm();
654 switch (SelectPred) {
655 default: llvm_unreachable("invalid predicate for isel");
656 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
657 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
658 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
659 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
660 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
661 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
662 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
663 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
664 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
665 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
668 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
669 SecondReg = SwapOps ? TrueReg : FalseReg;
671 // The first input register of isel cannot be r0. If it is a member
672 // of a register class that can be r0, then copy it first (the
673 // register allocator should eliminate the copy).
674 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
675 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
676 const TargetRegisterClass *FirstRC =
677 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
678 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
679 unsigned OldFirstReg = FirstReg;
680 FirstReg = MRI.createVirtualRegister(FirstRC);
681 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
682 .addReg(OldFirstReg);
685 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
686 .addReg(FirstReg).addReg(SecondReg)
687 .addReg(Cond[1].getReg(), 0, SubIdx);
690 static unsigned getCRBitValue(unsigned CRBit) {
692 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
693 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
694 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
695 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
697 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
698 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
699 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
700 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
702 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
703 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
704 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
705 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
707 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
708 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
709 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
710 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
713 assert(Ret != 4 && "Invalid CR bit register");
717 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
718 MachineBasicBlock::iterator I, DebugLoc DL,
719 unsigned DestReg, unsigned SrcReg,
720 bool KillSrc) const {
721 // We can end up with self copies and similar things as a result of VSX copy
722 // legalization. Promote them here.
723 const TargetRegisterInfo *TRI = &getRegisterInfo();
724 if (PPC::F8RCRegClass.contains(DestReg) &&
725 PPC::VSRCRegClass.contains(SrcReg)) {
727 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
729 if (VSXSelfCopyCrash && SrcReg == SuperReg)
730 llvm_unreachable("nop VSX copy");
733 } else if (PPC::VRRCRegClass.contains(DestReg) &&
734 PPC::VSRCRegClass.contains(SrcReg)) {
736 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
738 if (VSXSelfCopyCrash && SrcReg == SuperReg)
739 llvm_unreachable("nop VSX copy");
742 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
743 PPC::VSRCRegClass.contains(DestReg)) {
745 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
747 if (VSXSelfCopyCrash && DestReg == SuperReg)
748 llvm_unreachable("nop VSX copy");
751 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
752 PPC::VSRCRegClass.contains(DestReg)) {
754 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
756 if (VSXSelfCopyCrash && DestReg == SuperReg)
757 llvm_unreachable("nop VSX copy");
762 // Different class register copy
763 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
764 PPC::GPRCRegClass.contains(DestReg)) {
765 unsigned CRReg = getCRFromCRBit(SrcReg);
766 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
767 .addReg(CRReg), getKillRegState(KillSrc);
768 // Rotate the CR bit in the CR fields to be the least significant bit and
769 // then mask with 0x1 (MB = ME = 31).
770 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
771 .addReg(DestReg, RegState::Kill)
772 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
776 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
777 PPC::G8RCRegClass.contains(DestReg)) {
778 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
779 .addReg(SrcReg), getKillRegState(KillSrc);
781 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
782 PPC::GPRCRegClass.contains(DestReg)) {
783 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
784 .addReg(SrcReg), getKillRegState(KillSrc);
789 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
791 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
793 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
795 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
797 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
799 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
800 // There are two different ways this can be done:
801 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
802 // issue in VSU pipeline 0.
803 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
804 // can go to either pipeline.
805 // We'll always use xxlor here, because in practically all cases where
806 // copies are generated, they are close enough to some use that the
807 // lower-latency form is preferable.
809 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
810 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
812 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
814 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
816 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
818 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
821 llvm_unreachable("Impossible reg-to-reg copy");
823 const MCInstrDesc &MCID = get(Opc);
824 if (MCID.getNumOperands() == 3)
825 BuildMI(MBB, I, DL, MCID, DestReg)
826 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
828 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
831 // This function returns true if a CR spill is necessary and false otherwise.
833 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
834 unsigned SrcReg, bool isKill,
836 const TargetRegisterClass *RC,
837 SmallVectorImpl<MachineInstr*> &NewMIs,
838 bool &NonRI, bool &SpillsVRS) const{
839 // Note: If additional store instructions are added here,
840 // update isStoreToStackSlot.
843 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
844 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
845 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
847 getKillRegState(isKill)),
849 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
850 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
851 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
853 getKillRegState(isKill)),
855 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
856 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
858 getKillRegState(isKill)),
860 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
861 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
863 getKillRegState(isKill)),
865 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
866 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
868 getKillRegState(isKill)),
871 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
872 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
874 getKillRegState(isKill)),
877 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
878 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
880 getKillRegState(isKill)),
883 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
884 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
886 getKillRegState(isKill)),
889 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
890 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
892 getKillRegState(isKill)),
895 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
896 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
898 getKillRegState(isKill)),
901 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
902 assert(Subtarget.isDarwin() &&
903 "VRSAVE only needs spill/restore on Darwin");
904 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
906 getKillRegState(isKill)),
909 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
910 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
912 getKillRegState(isKill)),
915 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
916 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
918 getKillRegState(isKill)),
921 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
922 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
924 getKillRegState(isKill)),
928 llvm_unreachable("Unknown regclass!");
935 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
936 MachineBasicBlock::iterator MI,
937 unsigned SrcReg, bool isKill, int FrameIdx,
938 const TargetRegisterClass *RC,
939 const TargetRegisterInfo *TRI) const {
940 MachineFunction &MF = *MBB.getParent();
941 SmallVector<MachineInstr*, 4> NewMIs;
943 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
944 FuncInfo->setHasSpills();
946 bool NonRI = false, SpillsVRS = false;
947 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
949 FuncInfo->setSpillsCR();
952 FuncInfo->setSpillsVRSAVE();
955 FuncInfo->setHasNonRISpills();
957 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
958 MBB.insert(MI, NewMIs[i]);
960 const MachineFrameInfo &MFI = *MF.getFrameInfo();
961 MachineMemOperand *MMO =
962 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
963 MachineMemOperand::MOStore,
964 MFI.getObjectSize(FrameIdx),
965 MFI.getObjectAlignment(FrameIdx));
966 NewMIs.back()->addMemOperand(MF, MMO);
970 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
971 unsigned DestReg, int FrameIdx,
972 const TargetRegisterClass *RC,
973 SmallVectorImpl<MachineInstr*> &NewMIs,
974 bool &NonRI, bool &SpillsVRS) const{
975 // Note: If additional load instructions are added here,
976 // update isLoadFromStackSlot.
978 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
979 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
980 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
981 DestReg), FrameIdx));
982 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
983 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
984 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
986 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
987 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
989 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
990 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
992 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
993 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
994 get(PPC::RESTORE_CR), DestReg),
997 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
998 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
999 get(PPC::RESTORE_CRBIT), DestReg),
1002 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1003 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
1006 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1007 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
1010 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1011 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
1014 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1015 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
1018 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1019 assert(Subtarget.isDarwin() &&
1020 "VRSAVE only needs spill/restore on Darwin");
1021 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
1022 get(PPC::RESTORE_VRSAVE),
1026 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1027 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
1030 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1031 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
1034 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1035 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
1039 llvm_unreachable("Unknown regclass!");
1046 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1047 MachineBasicBlock::iterator MI,
1048 unsigned DestReg, int FrameIdx,
1049 const TargetRegisterClass *RC,
1050 const TargetRegisterInfo *TRI) const {
1051 MachineFunction &MF = *MBB.getParent();
1052 SmallVector<MachineInstr*, 4> NewMIs;
1054 if (MI != MBB.end()) DL = MI->getDebugLoc();
1056 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1057 FuncInfo->setHasSpills();
1059 bool NonRI = false, SpillsVRS = false;
1060 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
1062 FuncInfo->setSpillsCR();
1065 FuncInfo->setSpillsVRSAVE();
1068 FuncInfo->setHasNonRISpills();
1070 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1071 MBB.insert(MI, NewMIs[i]);
1073 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1074 MachineMemOperand *MMO =
1075 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
1076 MachineMemOperand::MOLoad,
1077 MFI.getObjectSize(FrameIdx),
1078 MFI.getObjectAlignment(FrameIdx));
1079 NewMIs.back()->addMemOperand(MF, MMO);
1083 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1084 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
1085 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1086 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1088 // Leave the CR# the same, but invert the condition.
1089 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1093 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1094 unsigned Reg, MachineRegisterInfo *MRI) const {
1095 // For some instructions, it is legal to fold ZERO into the RA register field.
1096 // A zero immediate should always be loaded with a single li.
1097 unsigned DefOpc = DefMI->getOpcode();
1098 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1100 if (!DefMI->getOperand(1).isImm())
1102 if (DefMI->getOperand(1).getImm() != 0)
1105 // Note that we cannot here invert the arguments of an isel in order to fold
1106 // a ZERO into what is presented as the second argument. All we have here
1107 // is the condition bit, and that might come from a CR-logical bit operation.
1109 const MCInstrDesc &UseMCID = UseMI->getDesc();
1111 // Only fold into real machine instructions.
1112 if (UseMCID.isPseudo())
1116 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
1117 if (UseMI->getOperand(UseIdx).isReg() &&
1118 UseMI->getOperand(UseIdx).getReg() == Reg)
1121 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
1122 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
1124 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1126 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1127 // register (which might also be specified as a pointer class kind).
1128 if (UseInfo->isLookupPtrRegClass()) {
1129 if (UseInfo->RegClass /* Kind */ != 1)
1132 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1133 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1137 // Make sure this is not tied to an output register (or otherwise
1138 // constrained). This is true for ST?UX registers, for example, which
1139 // are tied to their output registers.
1140 if (UseInfo->Constraints != 0)
1144 if (UseInfo->isLookupPtrRegClass()) {
1145 bool isPPC64 = Subtarget.isPPC64();
1146 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1148 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1149 PPC::ZERO8 : PPC::ZERO;
1152 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1153 UseMI->getOperand(UseIdx).setReg(ZeroReg);
1156 DefMI->eraseFromParent();
1161 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1162 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1164 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1169 // We should make sure that, if we're going to predicate both sides of a
1170 // condition (a diamond), that both sides don't define the counter register. We
1171 // can predicate counter-decrement-based branches, but while that predicates
1172 // the branching, it does not predicate the counter decrement. If we tried to
1173 // merge the triangle into one predicated block, we'd decrement the counter
1175 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1176 unsigned NumT, unsigned ExtraT,
1177 MachineBasicBlock &FMBB,
1178 unsigned NumF, unsigned ExtraF,
1179 const BranchProbability &Probability) const {
1180 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1184 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
1185 // The predicated branches are identified by their type, not really by the
1186 // explicit presence of a predicate. Furthermore, some of them can be
1187 // predicated more than once. Because if conversion won't try to predicate
1188 // any instruction which already claims to be predicated (by returning true
1189 // here), always return false. In doing so, we let isPredicable() be the
1190 // final word on whether not the instruction can be (further) predicated.
1195 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1196 if (!MI->isTerminator())
1199 // Conditional branch is a special case.
1200 if (MI->isBranch() && !MI->isBarrier())
1203 return !isPredicated(MI);
1206 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
1207 ArrayRef<MachineOperand> Pred) const {
1208 unsigned OpC = MI->getOpcode();
1209 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1210 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1211 bool isPPC64 = Subtarget.isPPC64();
1212 MI->setDesc(get(Pred[0].getImm() ?
1213 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
1214 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1215 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1216 MI->setDesc(get(PPC::BCLR));
1217 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1218 .addReg(Pred[1].getReg());
1219 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1220 MI->setDesc(get(PPC::BCLRn));
1221 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1222 .addReg(Pred[1].getReg());
1224 MI->setDesc(get(PPC::BCCLR));
1225 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1226 .addImm(Pred[0].getImm())
1227 .addReg(Pred[1].getReg());
1231 } else if (OpC == PPC::B) {
1232 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1233 bool isPPC64 = Subtarget.isPPC64();
1234 MI->setDesc(get(Pred[0].getImm() ?
1235 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1236 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1237 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1238 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1239 MI->RemoveOperand(0);
1241 MI->setDesc(get(PPC::BC));
1242 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1243 .addReg(Pred[1].getReg())
1245 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1246 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1247 MI->RemoveOperand(0);
1249 MI->setDesc(get(PPC::BCn));
1250 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1251 .addReg(Pred[1].getReg())
1254 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
1255 MI->RemoveOperand(0);
1257 MI->setDesc(get(PPC::BCC));
1258 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1259 .addImm(Pred[0].getImm())
1260 .addReg(Pred[1].getReg())
1265 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1266 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1267 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1268 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
1270 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1271 bool isPPC64 = Subtarget.isPPC64();
1273 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1274 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
1275 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1276 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1277 .addReg(Pred[1].getReg());
1279 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1280 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
1281 (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1282 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1283 .addReg(Pred[1].getReg());
1287 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
1288 (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1289 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
1290 .addImm(Pred[0].getImm())
1291 .addReg(Pred[1].getReg());
1298 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1299 ArrayRef<MachineOperand> Pred2) const {
1300 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
1301 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
1303 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1305 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1308 // P1 can only subsume P2 if they test the same condition register.
1309 if (Pred1[1].getReg() != Pred2[1].getReg())
1312 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1313 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1318 // Does P1 subsume P2, e.g. GE subsumes GT.
1319 if (P1 == PPC::PRED_LE &&
1320 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1322 if (P1 == PPC::PRED_GE &&
1323 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1329 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1330 std::vector<MachineOperand> &Pred) const {
1331 // Note: At the present time, the contents of Pred from this function is
1332 // unused by IfConversion. This implementation follows ARM by pushing the
1333 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1334 // predicate, instructions defining CTR or CTR8 are also included as
1335 // predicate-defining instructions.
1337 const TargetRegisterClass *RCs[] =
1338 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1339 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1342 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1343 const MachineOperand &MO = MI->getOperand(i);
1344 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1345 const TargetRegisterClass *RC = RCs[c];
1347 if (MO.isDef() && RC->contains(MO.getReg())) {
1351 } else if (MO.isRegMask()) {
1352 for (TargetRegisterClass::iterator I = RC->begin(),
1353 IE = RC->end(); I != IE; ++I)
1354 if (MO.clobbersPhysReg(*I)) {
1365 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1366 unsigned OpC = MI->getOpcode();
1381 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
1382 unsigned &SrcReg, unsigned &SrcReg2,
1383 int &Mask, int &Value) const {
1384 unsigned Opc = MI->getOpcode();
1387 default: return false;
1392 SrcReg = MI->getOperand(1).getReg();
1394 Value = MI->getOperand(2).getImm();
1403 SrcReg = MI->getOperand(1).getReg();
1404 SrcReg2 = MI->getOperand(2).getReg();
1409 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
1410 unsigned SrcReg, unsigned SrcReg2,
1411 int Mask, int Value,
1412 const MachineRegisterInfo *MRI) const {
1416 int OpC = CmpInstr->getOpcode();
1417 unsigned CRReg = CmpInstr->getOperand(0).getReg();
1419 // FP record forms set CR1 based on the execption status bits, not a
1420 // comparison with zero.
1421 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1424 // The record forms set the condition register based on a signed comparison
1425 // with zero (so says the ISA manual). This is not as straightforward as it
1426 // seems, however, because this is always a 64-bit comparison on PPC64, even
1427 // for instructions that are 32-bit in nature (like slw for example).
1428 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1429 // for equality checks (as those don't depend on the sign). On PPC64,
1430 // we are restricted to equality for unsigned 64-bit comparisons and for
1431 // signed 32-bit comparisons the applicability is more restricted.
1432 bool isPPC64 = Subtarget.isPPC64();
1433 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1434 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1435 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1437 // Get the unique definition of SrcReg.
1438 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1439 if (!MI) return false;
1440 int MIOpC = MI->getOpcode();
1442 bool equalityOnly = false;
1445 if (is32BitSignedCompare) {
1446 // We can perform this optimization only if MI is sign-extending.
1447 if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
1448 MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
1449 MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
1450 MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
1451 MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
1455 } else if (is32BitUnsignedCompare) {
1456 // We can perform this optimization, equality only, if MI is
1458 if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
1459 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
1460 MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
1462 equalityOnly = true;
1466 equalityOnly = is64BitUnsignedCompare;
1468 equalityOnly = is32BitUnsignedCompare;
1471 // We need to check the uses of the condition register in order to reject
1472 // non-equality comparisons.
1473 for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
1474 IE = MRI->use_instr_end(); I != IE; ++I) {
1475 MachineInstr *UseMI = &*I;
1476 if (UseMI->getOpcode() == PPC::BCC) {
1477 unsigned Pred = UseMI->getOperand(0).getImm();
1478 if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
1480 } else if (UseMI->getOpcode() == PPC::ISEL ||
1481 UseMI->getOpcode() == PPC::ISEL8) {
1482 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1483 if (SubIdx != PPC::sub_eq)
1490 MachineBasicBlock::iterator I = CmpInstr;
1492 // Scan forward to find the first use of the compare.
1493 for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
1495 bool FoundUse = false;
1496 for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
1497 JE = MRI->use_instr_end(); J != JE; ++J)
1507 // There are two possible candidates which can be changed to set CR[01].
1508 // One is MI, the other is a SUB instruction.
1509 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1510 MachineInstr *Sub = nullptr;
1512 // MI is not a candidate for CMPrr.
1514 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1515 // same BB as the comparison. This is to allow the check below to avoid calls
1516 // (and other explicit clobbers); instead we should really check for these
1517 // more explicitly (in at least a few predecessors).
1518 else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
1519 // PPC does not have a record-form SUBri.
1524 const TargetRegisterInfo *TRI = &getRegisterInfo();
1527 // Get ready to iterate backward from CmpInstr.
1528 MachineBasicBlock::iterator E = MI,
1529 B = CmpInstr->getParent()->begin();
1531 for (; I != E && !noSub; --I) {
1532 const MachineInstr &Instr = *I;
1533 unsigned IOpC = Instr.getOpcode();
1535 if (&*I != CmpInstr && (
1536 Instr.modifiesRegister(PPC::CR0, TRI) ||
1537 Instr.readsRegister(PPC::CR0, TRI)))
1538 // This instruction modifies or uses the record condition register after
1539 // the one we want to change. While we could do this transformation, it
1540 // would likely not be profitable. This transformation removes one
1541 // instruction, and so even forcing RA to generate one move probably
1542 // makes it unprofitable.
1545 // Check whether CmpInstr can be made redundant by the current instruction.
1546 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1547 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1548 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1549 ((Instr.getOperand(1).getReg() == SrcReg &&
1550 Instr.getOperand(2).getReg() == SrcReg2) ||
1551 (Instr.getOperand(1).getReg() == SrcReg2 &&
1552 Instr.getOperand(2).getReg() == SrcReg))) {
1558 // The 'and' is below the comparison instruction.
1562 // Return false if no candidates exist.
1566 // The single candidate is called MI.
1570 MIOpC = MI->getOpcode();
1571 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
1574 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1575 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1579 // FIXME: On the non-embedded POWER architectures, only some of the record
1580 // forms are fast, and we should use only the fast ones.
1582 // The defining instruction has a record form (or is already a record
1583 // form). It is possible, however, that we'll need to reverse the condition
1584 // code of the users.
1588 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1589 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1591 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1592 // needs to be updated to be based on SUB. Push the condition code
1593 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1594 // condition code of these operands will be modified.
1595 bool ShouldSwap = false;
1597 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1598 Sub->getOperand(2).getReg() == SrcReg;
1600 // The operands to subf are the opposite of sub, so only in the fixed-point
1601 // case, invert the order.
1602 ShouldSwap = !ShouldSwap;
1606 for (MachineRegisterInfo::use_instr_iterator
1607 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1609 MachineInstr *UseMI = &*I;
1610 if (UseMI->getOpcode() == PPC::BCC) {
1611 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1612 assert((!equalityOnly ||
1613 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
1614 "Invalid predicate for equality-only optimization");
1615 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1616 PPC::getSwappedPredicate(Pred)));
1617 } else if (UseMI->getOpcode() == PPC::ISEL ||
1618 UseMI->getOpcode() == PPC::ISEL8) {
1619 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1620 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
1621 "Invalid CR bit for equality-only optimization");
1623 if (NewSubReg == PPC::sub_lt)
1624 NewSubReg = PPC::sub_gt;
1625 else if (NewSubReg == PPC::sub_gt)
1626 NewSubReg = PPC::sub_lt;
1628 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1630 } else // We need to abort on a user we don't understand.
1634 // Create a new virtual register to hold the value of the CR set by the
1635 // record-form instruction. If the instruction was not previously in
1636 // record form, then set the kill flag on the CR.
1637 CmpInstr->eraseFromParent();
1639 MachineBasicBlock::iterator MII = MI;
1640 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1641 get(TargetOpcode::COPY), CRReg)
1642 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1644 if (MIOpC != NewOpC) {
1645 // We need to be careful here: we're replacing one instruction with
1646 // another, and we need to make sure that we get all of the right
1647 // implicit uses and defs. On the other hand, the caller may be holding
1648 // an iterator to this instruction, and so we can't delete it (this is
1649 // specifically the case if this is the instruction directly after the
1652 const MCInstrDesc &NewDesc = get(NewOpC);
1653 MI->setDesc(NewDesc);
1655 if (NewDesc.ImplicitDefs)
1656 for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
1657 *ImpDefs; ++ImpDefs)
1658 if (!MI->definesRegister(*ImpDefs))
1659 MI->addOperand(*MI->getParent()->getParent(),
1660 MachineOperand::CreateReg(*ImpDefs, true, true));
1661 if (NewDesc.ImplicitUses)
1662 for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
1663 *ImpUses; ++ImpUses)
1664 if (!MI->readsRegister(*ImpUses))
1665 MI->addOperand(*MI->getParent()->getParent(),
1666 MachineOperand::CreateReg(*ImpUses, false, true));
1669 // Modify the condition code of operands in OperandsToUpdate.
1670 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1671 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1672 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1673 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1675 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1676 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1681 /// GetInstSize - Return the number of bytes of code the specified
1682 /// instruction may be. This returns the maximum number of bytes.
1684 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1685 unsigned Opcode = MI->getOpcode();
1687 if (Opcode == PPC::INLINEASM) {
1688 const MachineFunction *MF = MI->getParent()->getParent();
1689 const char *AsmStr = MI->getOperand(0).getSymbolName();
1690 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1691 } else if (Opcode == TargetOpcode::STACKMAP) {
1692 return MI->getOperand(1).getImm();
1693 } else if (Opcode == TargetOpcode::PATCHPOINT) {
1694 PatchPointOpers Opers(MI);
1695 return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
1697 const MCInstrDesc &Desc = get(Opcode);
1698 return Desc.getSize();