1 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCHazardRecognizers.h"
18 #include "PPCInstrBuilder.h"
19 #include "PPCMachineFunctionInfo.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineMemOperand.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/PseudoSourceValue.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
35 #define GET_INSTRINFO_CTOR
36 #include "PPCGenInstrInfo.inc"
41 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
42 cl::desc("Disable analysis for CTR loops"));
44 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
45 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
46 TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
48 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
49 /// this target when scheduling the DAG.
50 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
51 const TargetMachine *TM,
52 const ScheduleDAG *DAG) const {
53 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
54 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
55 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
56 const InstrItineraryData *II = TM->getInstrItineraryData();
57 return new PPCScoreboardHazardRecognizer(II, DAG);
60 return TargetInstrInfo::CreateTargetHazardRecognizer(TM, DAG);
63 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
64 /// to use for this target when scheduling the DAG.
65 ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
66 const InstrItineraryData *II,
67 const ScheduleDAG *DAG) const {
68 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
70 // Most subtargets use a PPC970 recognizer.
71 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
72 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
73 const TargetInstrInfo *TII = TM.getInstrInfo();
74 assert(TII && "No InstrInfo?");
76 return new PPCHazardRecognizer970(*TII);
79 return new PPCScoreboardHazardRecognizer(II, DAG);
82 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
83 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
84 unsigned &SrcReg, unsigned &DstReg,
85 unsigned &SubIdx) const {
86 switch (MI.getOpcode()) {
87 default: return false;
89 case PPC::EXTSW_32_64:
90 SrcReg = MI.getOperand(1).getReg();
91 DstReg = MI.getOperand(0).getReg();
97 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const {
99 // Note: This list must be kept consistent with LoadRegFromStackSlot.
100 switch (MI->getOpcode()) {
106 case PPC::RESTORE_CR:
108 case PPC::RESTORE_VRSAVE:
109 // Check for the operands added by addFrameReference (the immediate is the
110 // offset which defaults to 0).
111 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
112 MI->getOperand(2).isFI()) {
113 FrameIndex = MI->getOperand(2).getIndex();
114 return MI->getOperand(0).getReg();
121 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
122 int &FrameIndex) const {
123 // Note: This list must be kept consistent with StoreRegToStackSlot.
124 switch (MI->getOpcode()) {
132 case PPC::SPILL_VRSAVE:
133 // Check for the operands added by addFrameReference (the immediate is the
134 // offset which defaults to 0).
135 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
136 MI->getOperand(2).isFI()) {
137 FrameIndex = MI->getOperand(2).getIndex();
138 return MI->getOperand(0).getReg();
145 // commuteInstruction - We can commute rlwimi instructions, but only if the
146 // rotate amt is zero. We also have to munge the immediates a bit.
148 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
149 MachineFunction &MF = *MI->getParent()->getParent();
151 // Normal instructions can be commuted the obvious way.
152 if (MI->getOpcode() != PPC::RLWIMI &&
153 MI->getOpcode() != PPC::RLWIMIo)
154 return TargetInstrInfo::commuteInstruction(MI, NewMI);
156 // Cannot commute if it has a non-zero rotate count.
157 if (MI->getOperand(3).getImm() != 0)
160 // If we have a zero rotate count, we have:
162 // Op0 = (Op1 & ~M) | (Op2 & M)
164 // M = mask((ME+1)&31, (MB-1)&31)
165 // Op0 = (Op2 & ~M) | (Op1 & M)
168 unsigned Reg0 = MI->getOperand(0).getReg();
169 unsigned Reg1 = MI->getOperand(1).getReg();
170 unsigned Reg2 = MI->getOperand(2).getReg();
171 bool Reg1IsKill = MI->getOperand(1).isKill();
172 bool Reg2IsKill = MI->getOperand(2).isKill();
173 bool ChangeReg0 = false;
174 // If machine instrs are no longer in two-address forms, update
175 // destination register as well.
177 // Must be two address instruction!
178 assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
179 "Expecting a two-address instruction!");
185 unsigned MB = MI->getOperand(4).getImm();
186 unsigned ME = MI->getOperand(5).getImm();
189 // Create a new instruction.
190 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
191 bool Reg0IsDead = MI->getOperand(0).isDead();
192 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
193 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
194 .addReg(Reg2, getKillRegState(Reg2IsKill))
195 .addReg(Reg1, getKillRegState(Reg1IsKill))
197 .addImm((MB-1) & 31);
201 MI->getOperand(0).setReg(Reg2);
202 MI->getOperand(2).setReg(Reg1);
203 MI->getOperand(1).setReg(Reg2);
204 MI->getOperand(2).setIsKill(Reg1IsKill);
205 MI->getOperand(1).setIsKill(Reg2IsKill);
207 // Swap the mask around.
208 MI->getOperand(4).setImm((ME+1) & 31);
209 MI->getOperand(5).setImm((MB-1) & 31);
213 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
214 MachineBasicBlock::iterator MI) const {
216 BuildMI(MBB, MI, DL, get(PPC::NOP));
221 // Note: If the condition register is set to CTR or CTR8 then this is a
222 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
223 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
224 MachineBasicBlock *&FBB,
225 SmallVectorImpl<MachineOperand> &Cond,
226 bool AllowModify) const {
227 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
229 // If the block has no terminators, it just falls into the block after it.
230 MachineBasicBlock::iterator I = MBB.end();
231 if (I == MBB.begin())
234 while (I->isDebugValue()) {
235 if (I == MBB.begin())
239 if (!isUnpredicatedTerminator(I))
242 // Get the last instruction in the block.
243 MachineInstr *LastInst = I;
245 // If there is only one terminator instruction, process it.
246 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
247 if (LastInst->getOpcode() == PPC::B) {
248 if (!LastInst->getOperand(0).isMBB())
250 TBB = LastInst->getOperand(0).getMBB();
252 } else if (LastInst->getOpcode() == PPC::BCC) {
253 if (!LastInst->getOperand(2).isMBB())
255 // Block ends with fall-through condbranch.
256 TBB = LastInst->getOperand(2).getMBB();
257 Cond.push_back(LastInst->getOperand(0));
258 Cond.push_back(LastInst->getOperand(1));
260 } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
261 LastInst->getOpcode() == PPC::BDNZ) {
262 if (!LastInst->getOperand(0).isMBB())
264 if (DisableCTRLoopAnal)
266 TBB = LastInst->getOperand(0).getMBB();
267 Cond.push_back(MachineOperand::CreateImm(1));
268 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
271 } else if (LastInst->getOpcode() == PPC::BDZ8 ||
272 LastInst->getOpcode() == PPC::BDZ) {
273 if (!LastInst->getOperand(0).isMBB())
275 if (DisableCTRLoopAnal)
277 TBB = LastInst->getOperand(0).getMBB();
278 Cond.push_back(MachineOperand::CreateImm(0));
279 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
284 // Otherwise, don't know what this is.
288 // Get the instruction before it if it's a terminator.
289 MachineInstr *SecondLastInst = I;
291 // If there are three terminators, we don't know what sort of block this is.
292 if (SecondLastInst && I != MBB.begin() &&
293 isUnpredicatedTerminator(--I))
296 // If the block ends with PPC::B and PPC:BCC, handle it.
297 if (SecondLastInst->getOpcode() == PPC::BCC &&
298 LastInst->getOpcode() == PPC::B) {
299 if (!SecondLastInst->getOperand(2).isMBB() ||
300 !LastInst->getOperand(0).isMBB())
302 TBB = SecondLastInst->getOperand(2).getMBB();
303 Cond.push_back(SecondLastInst->getOperand(0));
304 Cond.push_back(SecondLastInst->getOperand(1));
305 FBB = LastInst->getOperand(0).getMBB();
307 } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
308 SecondLastInst->getOpcode() == PPC::BDNZ) &&
309 LastInst->getOpcode() == PPC::B) {
310 if (!SecondLastInst->getOperand(0).isMBB() ||
311 !LastInst->getOperand(0).isMBB())
313 if (DisableCTRLoopAnal)
315 TBB = SecondLastInst->getOperand(0).getMBB();
316 Cond.push_back(MachineOperand::CreateImm(1));
317 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
319 FBB = LastInst->getOperand(0).getMBB();
321 } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
322 SecondLastInst->getOpcode() == PPC::BDZ) &&
323 LastInst->getOpcode() == PPC::B) {
324 if (!SecondLastInst->getOperand(0).isMBB() ||
325 !LastInst->getOperand(0).isMBB())
327 if (DisableCTRLoopAnal)
329 TBB = SecondLastInst->getOperand(0).getMBB();
330 Cond.push_back(MachineOperand::CreateImm(0));
331 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
333 FBB = LastInst->getOperand(0).getMBB();
337 // If the block ends with two PPC:Bs, handle it. The second one is not
338 // executed, so remove it.
339 if (SecondLastInst->getOpcode() == PPC::B &&
340 LastInst->getOpcode() == PPC::B) {
341 if (!SecondLastInst->getOperand(0).isMBB())
343 TBB = SecondLastInst->getOperand(0).getMBB();
346 I->eraseFromParent();
350 // Otherwise, can't handle this.
354 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
355 MachineBasicBlock::iterator I = MBB.end();
356 if (I == MBB.begin()) return 0;
358 while (I->isDebugValue()) {
359 if (I == MBB.begin())
363 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
364 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
365 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
368 // Remove the branch.
369 I->eraseFromParent();
373 if (I == MBB.begin()) return 1;
375 if (I->getOpcode() != PPC::BCC &&
376 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
377 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
380 // Remove the branch.
381 I->eraseFromParent();
386 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
387 MachineBasicBlock *FBB,
388 const SmallVectorImpl<MachineOperand> &Cond,
390 // Shouldn't be a fall through.
391 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
392 assert((Cond.size() == 2 || Cond.size() == 0) &&
393 "PPC branch conditions have two components!");
395 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
399 if (Cond.empty()) // Unconditional branch
400 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
401 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
402 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
403 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
404 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
405 else // Conditional branch
406 BuildMI(&MBB, DL, get(PPC::BCC))
407 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
411 // Two-way Conditional Branch.
412 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
413 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
414 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
415 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
417 BuildMI(&MBB, DL, get(PPC::BCC))
418 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
419 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
424 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
425 const SmallVectorImpl<MachineOperand> &Cond,
426 unsigned TrueReg, unsigned FalseReg,
427 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
428 if (!TM.getSubtargetImpl()->hasISEL())
431 if (Cond.size() != 2)
434 // If this is really a bdnz-like condition, then it cannot be turned into a
436 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
439 // Check register classes.
440 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
441 const TargetRegisterClass *RC =
442 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
446 // isel is for regular integer GPRs only.
447 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
448 !PPC::G8RCRegClass.hasSubClassEq(RC))
451 // FIXME: These numbers are for the A2, how well they work for other cores is
452 // an open question. On the A2, the isel instruction has a 2-cycle latency
453 // but single-cycle throughput. These numbers are used in combination with
454 // the MispredictPenalty setting from the active SchedMachineModel.
462 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
463 MachineBasicBlock::iterator MI, DebugLoc dl,
465 const SmallVectorImpl<MachineOperand> &Cond,
466 unsigned TrueReg, unsigned FalseReg) const {
467 assert(Cond.size() == 2 &&
468 "PPC branch conditions have two components!");
470 assert(TM.getSubtargetImpl()->hasISEL() &&
471 "Cannot insert select on target without ISEL support");
473 // Get the register classes.
474 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
475 const TargetRegisterClass *RC =
476 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
477 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
478 assert((PPC::GPRCRegClass.hasSubClassEq(RC) ||
479 PPC::G8RCRegClass.hasSubClassEq(RC)) &&
480 "isel is for regular integer GPRs only");
483 PPC::GPRCRegClass.hasSubClassEq(RC) ? PPC::ISEL : PPC::ISEL8;
484 unsigned SelectPred = Cond[0].getImm();
488 switch (SelectPred) {
489 default: llvm_unreachable("invalid predicate for isel");
490 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
491 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
492 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
493 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
494 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
495 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
496 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break;
497 case PPC::PRED_NU: SubIdx = PPC::sub_un; SwapOps = true; break;
500 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
501 SecondReg = SwapOps ? TrueReg : FalseReg;
503 // The first input register of isel cannot be r0. If it is a member
504 // of a register class that can be r0, then copy it first (the
505 // register allocator should eliminate the copy).
506 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
507 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
508 const TargetRegisterClass *FirstRC =
509 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
510 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
511 unsigned OldFirstReg = FirstReg;
512 FirstReg = MRI.createVirtualRegister(FirstRC);
513 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
514 .addReg(OldFirstReg);
517 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
518 .addReg(FirstReg).addReg(SecondReg)
519 .addReg(Cond[1].getReg(), 0, SubIdx);
522 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
523 MachineBasicBlock::iterator I, DebugLoc DL,
524 unsigned DestReg, unsigned SrcReg,
525 bool KillSrc) const {
527 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
529 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
531 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
533 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
535 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
537 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
540 llvm_unreachable("Impossible reg-to-reg copy");
542 const MCInstrDesc &MCID = get(Opc);
543 if (MCID.getNumOperands() == 3)
544 BuildMI(MBB, I, DL, MCID, DestReg)
545 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
547 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
550 // This function returns true if a CR spill is necessary and false otherwise.
552 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
553 unsigned SrcReg, bool isKill,
555 const TargetRegisterClass *RC,
556 SmallVectorImpl<MachineInstr*> &NewMIs,
557 bool &NonRI, bool &SpillsVRS) const{
558 // Note: If additional store instructions are added here,
559 // update isStoreToStackSlot.
562 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
563 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
565 getKillRegState(isKill)),
567 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
568 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
570 getKillRegState(isKill)),
572 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
573 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
575 getKillRegState(isKill)),
577 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
578 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
580 getKillRegState(isKill)),
582 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
583 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
585 getKillRegState(isKill)),
588 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
589 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
590 // backend currently only uses CR1EQ as an individual bit, this should
591 // not cause any bug. If we need other uses of CR bits, the following
592 // code may be invalid.
594 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
595 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
597 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
598 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
600 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
601 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
603 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
604 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
606 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
607 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
609 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
610 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
612 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
613 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
615 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
616 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
619 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
620 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
622 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
623 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
625 getKillRegState(isKill)),
628 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
629 assert(TM.getSubtargetImpl()->isDarwin() &&
630 "VRSAVE only needs spill/restore on Darwin");
631 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
633 getKillRegState(isKill)),
637 llvm_unreachable("Unknown regclass!");
644 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
645 MachineBasicBlock::iterator MI,
646 unsigned SrcReg, bool isKill, int FrameIdx,
647 const TargetRegisterClass *RC,
648 const TargetRegisterInfo *TRI) const {
649 MachineFunction &MF = *MBB.getParent();
650 SmallVector<MachineInstr*, 4> NewMIs;
652 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
653 FuncInfo->setHasSpills();
655 bool NonRI = false, SpillsVRS = false;
656 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
658 FuncInfo->setSpillsCR();
661 FuncInfo->setSpillsVRSAVE();
664 FuncInfo->setHasNonRISpills();
666 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
667 MBB.insert(MI, NewMIs[i]);
669 const MachineFrameInfo &MFI = *MF.getFrameInfo();
670 MachineMemOperand *MMO =
671 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
672 MachineMemOperand::MOStore,
673 MFI.getObjectSize(FrameIdx),
674 MFI.getObjectAlignment(FrameIdx));
675 NewMIs.back()->addMemOperand(MF, MMO);
679 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
680 unsigned DestReg, int FrameIdx,
681 const TargetRegisterClass *RC,
682 SmallVectorImpl<MachineInstr*> &NewMIs,
683 bool &NonRI, bool &SpillsVRS) const{
684 // Note: If additional load instructions are added here,
685 // update isLoadFromStackSlot.
687 if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
688 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
689 DestReg), FrameIdx));
690 } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
691 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
693 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
694 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
696 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
697 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
699 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
700 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
701 get(PPC::RESTORE_CR), DestReg),
704 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
707 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
708 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
710 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
711 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
713 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
714 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
716 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
717 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
719 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
720 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
722 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
723 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
725 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
726 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
728 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
729 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
732 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
733 &PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
735 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
736 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
739 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
740 assert(TM.getSubtargetImpl()->isDarwin() &&
741 "VRSAVE only needs spill/restore on Darwin");
742 NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
743 get(PPC::RESTORE_VRSAVE),
748 llvm_unreachable("Unknown regclass!");
755 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
756 MachineBasicBlock::iterator MI,
757 unsigned DestReg, int FrameIdx,
758 const TargetRegisterClass *RC,
759 const TargetRegisterInfo *TRI) const {
760 MachineFunction &MF = *MBB.getParent();
761 SmallVector<MachineInstr*, 4> NewMIs;
763 if (MI != MBB.end()) DL = MI->getDebugLoc();
765 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
766 FuncInfo->setHasSpills();
768 bool NonRI = false, SpillsVRS = false;
769 if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
771 FuncInfo->setSpillsCR();
774 FuncInfo->setSpillsVRSAVE();
777 FuncInfo->setHasNonRISpills();
779 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
780 MBB.insert(MI, NewMIs[i]);
782 const MachineFrameInfo &MFI = *MF.getFrameInfo();
783 MachineMemOperand *MMO =
784 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
785 MachineMemOperand::MOLoad,
786 MFI.getObjectSize(FrameIdx),
787 MFI.getObjectAlignment(FrameIdx));
788 NewMIs.back()->addMemOperand(MF, MMO);
792 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
793 int FrameIx, uint64_t Offset,
796 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
797 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
802 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
803 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
804 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
805 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
807 // Leave the CR# the same, but invert the condition.
808 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
812 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
813 unsigned Reg, MachineRegisterInfo *MRI) const {
814 // For some instructions, it is legal to fold ZERO into the RA register field.
815 // A zero immediate should always be loaded with a single li.
816 unsigned DefOpc = DefMI->getOpcode();
817 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
819 if (!DefMI->getOperand(1).isImm())
821 if (DefMI->getOperand(1).getImm() != 0)
824 // Note that we cannot here invert the arguments of an isel in order to fold
825 // a ZERO into what is presented as the second argument. All we have here
826 // is the condition bit, and that might come from a CR-logical bit operation.
828 const MCInstrDesc &UseMCID = UseMI->getDesc();
830 // Only fold into real machine instructions.
831 if (UseMCID.isPseudo())
835 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
836 if (UseMI->getOperand(UseIdx).isReg() &&
837 UseMI->getOperand(UseIdx).getReg() == Reg)
840 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
841 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
843 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
845 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
846 // register (which might also be specified as a pointer class kind).
847 if (UseInfo->isLookupPtrRegClass()) {
848 if (UseInfo->RegClass /* Kind */ != 1)
851 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
852 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
856 // Make sure this is not tied to an output register (or otherwise
857 // constrained). This is true for ST?UX registers, for example, which
858 // are tied to their output registers.
859 if (UseInfo->Constraints != 0)
863 if (UseInfo->isLookupPtrRegClass()) {
864 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
865 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
867 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
868 PPC::ZERO8 : PPC::ZERO;
871 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
872 UseMI->getOperand(UseIdx).setReg(ZeroReg);
875 DefMI->eraseFromParent();
880 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
881 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
883 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
888 // We should make sure that, if we're going to predicate both sides of a
889 // condition (a diamond), that both sides don't define the counter register. We
890 // can predicate counter-decrement-based branches, but while that predicates
891 // the branching, it does not predicate the counter decrement. If we tried to
892 // merge the triangle into one predicated block, we'd decrement the counter
894 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
895 unsigned NumT, unsigned ExtraT,
896 MachineBasicBlock &FMBB,
897 unsigned NumF, unsigned ExtraF,
898 const BranchProbability &Probability) const {
899 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
903 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
904 // The predicated branches are identified by their type, not really by the
905 // explicit presence of a predicate. Furthermore, some of them can be
906 // predicated more than once. Because if conversion won't try to predicate
907 // any instruction which already claims to be predicated (by returning true
908 // here), always return false. In doing so, we let isPredicable() be the
909 // final word on whether not the instruction can be (further) predicated.
914 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
915 if (!MI->isTerminator())
918 // Conditional branch is a special case.
919 if (MI->isBranch() && !MI->isBarrier())
922 return !isPredicated(MI);
925 bool PPCInstrInfo::PredicateInstruction(
927 const SmallVectorImpl<MachineOperand> &Pred) const {
928 unsigned OpC = MI->getOpcode();
929 if (OpC == PPC::BLR) {
930 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
931 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
932 MI->setDesc(get(Pred[0].getImm() ?
933 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
934 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
936 MI->setDesc(get(PPC::BCLR));
937 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
938 .addImm(Pred[0].getImm())
939 .addReg(Pred[1].getReg());
943 } else if (OpC == PPC::B) {
944 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
945 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
946 MI->setDesc(get(Pred[0].getImm() ?
947 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
948 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
950 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
951 MI->RemoveOperand(0);
953 MI->setDesc(get(PPC::BCC));
954 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
955 .addImm(Pred[0].getImm())
956 .addReg(Pred[1].getReg())
961 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
962 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
963 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
964 llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
966 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
967 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
968 MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
969 (setLR ? PPC::BCCTRL : PPC::BCCTR)));
970 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
971 .addImm(Pred[0].getImm())
972 .addReg(Pred[1].getReg());
979 bool PPCInstrInfo::SubsumesPredicate(
980 const SmallVectorImpl<MachineOperand> &Pred1,
981 const SmallVectorImpl<MachineOperand> &Pred2) const {
982 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
983 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
985 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
987 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
990 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
991 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
996 // Does P1 subsume P2, e.g. GE subsumes GT.
997 if (P1 == PPC::PRED_LE &&
998 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1000 if (P1 == PPC::PRED_GE &&
1001 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1007 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
1008 std::vector<MachineOperand> &Pred) const {
1009 // Note: At the present time, the contents of Pred from this function is
1010 // unused by IfConversion. This implementation follows ARM by pushing the
1011 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1012 // predicate, instructions defining CTR or CTR8 are also included as
1013 // predicate-defining instructions.
1015 const TargetRegisterClass *RCs[] =
1016 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1017 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1020 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1021 const MachineOperand &MO = MI->getOperand(i);
1022 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1023 const TargetRegisterClass *RC = RCs[c];
1025 if (MO.isDef() && RC->contains(MO.getReg())) {
1029 } else if (MO.isRegMask()) {
1030 for (TargetRegisterClass::iterator I = RC->begin(),
1031 IE = RC->end(); I != IE; ++I)
1032 if (MO.clobbersPhysReg(*I)) {
1043 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1044 unsigned OpC = MI->getOpcode();
1058 /// GetInstSize - Return the number of bytes of code the specified
1059 /// instruction may be. This returns the maximum number of bytes.
1061 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
1062 switch (MI->getOpcode()) {
1063 case PPC::INLINEASM: { // Inline Asm: Variable size.
1064 const MachineFunction *MF = MI->getParent()->getParent();
1065 const char *AsmStr = MI->getOperand(0).getSymbolName();
1066 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1068 case PPC::PROLOG_LABEL:
1071 case PPC::DBG_VALUE:
1077 return 4; // PowerPC instructions are all 4 bytes
1082 #define DEBUG_TYPE "ppc-early-ret"
1083 STATISTIC(NumBCLR, "Number of early conditional returns");
1084 STATISTIC(NumBLR, "Number of early returns");
1087 void initializePPCEarlyReturnPass(PassRegistry&);
1091 // PPCEarlyReturn pass - For simple functions without epilogue code, move
1092 // returns up, and create conditional returns, to avoid unnecessary
1093 // branch-to-blr sequences.
1094 struct PPCEarlyReturn : public MachineFunctionPass {
1096 PPCEarlyReturn() : MachineFunctionPass(ID) {
1097 initializePPCEarlyReturnPass(*PassRegistry::getPassRegistry());
1100 const PPCTargetMachine *TM;
1101 const PPCInstrInfo *TII;
1104 bool processBlock(MachineBasicBlock &ReturnMBB) {
1105 bool Changed = false;
1107 MachineBasicBlock::iterator I = ReturnMBB.begin();
1108 I = ReturnMBB.SkipPHIsAndLabels(I);
1110 // The block must be essentially empty except for the blr.
1111 if (I == ReturnMBB.end() || I->getOpcode() != PPC::BLR ||
1112 I != ReturnMBB.getLastNonDebugInstr())
1115 SmallVector<MachineBasicBlock*, 8> PredToRemove;
1116 for (MachineBasicBlock::pred_iterator PI = ReturnMBB.pred_begin(),
1117 PIE = ReturnMBB.pred_end(); PI != PIE; ++PI) {
1118 bool OtherReference = false, BlockChanged = false;
1119 for (MachineBasicBlock::iterator J = (*PI)->getLastNonDebugInstr();;) {
1120 if (J->getOpcode() == PPC::B) {
1121 if (J->getOperand(0).getMBB() == &ReturnMBB) {
1122 // This is an unconditional branch to the return. Replace the
1123 // branch with a blr.
1124 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BLR));
1125 MachineBasicBlock::iterator K = J--;
1126 K->eraseFromParent();
1127 BlockChanged = true;
1131 } else if (J->getOpcode() == PPC::BCC) {
1132 if (J->getOperand(2).getMBB() == &ReturnMBB) {
1133 // This is a conditional branch to the return. Replace the branch
1135 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCLR))
1136 .addImm(J->getOperand(0).getImm())
1137 .addReg(J->getOperand(1).getReg());
1138 MachineBasicBlock::iterator K = J--;
1139 K->eraseFromParent();
1140 BlockChanged = true;
1144 } else if (J->isBranch()) {
1145 if (J->isIndirectBranch()) {
1146 if (ReturnMBB.hasAddressTaken())
1147 OtherReference = true;
1149 for (unsigned i = 0; i < J->getNumOperands(); ++i)
1150 if (J->getOperand(i).isMBB() &&
1151 J->getOperand(i).getMBB() == &ReturnMBB)
1152 OtherReference = true;
1153 } else if (!J->isTerminator() && !J->isDebugValue())
1156 if (J == (*PI)->begin())
1162 if ((*PI)->canFallThrough() && (*PI)->isLayoutSuccessor(&ReturnMBB))
1163 OtherReference = true;
1165 // Predecessors are stored in a vector and can't be removed here.
1166 if (!OtherReference && BlockChanged) {
1167 PredToRemove.push_back(*PI);
1174 for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
1175 PredToRemove[i]->removeSuccessor(&ReturnMBB);
1177 if (Changed && !ReturnMBB.hasAddressTaken()) {
1178 // We now might be able to merge this blr-only block into its
1179 // by-layout predecessor.
1180 if (ReturnMBB.pred_size() == 1 &&
1181 (*ReturnMBB.pred_begin())->isLayoutSuccessor(&ReturnMBB)) {
1182 // Move the blr into the preceding block.
1183 MachineBasicBlock &PrevMBB = **ReturnMBB.pred_begin();
1184 PrevMBB.splice(PrevMBB.end(), &ReturnMBB, I);
1185 PrevMBB.removeSuccessor(&ReturnMBB);
1188 if (ReturnMBB.pred_empty())
1189 ReturnMBB.eraseFromParent();
1196 virtual bool runOnMachineFunction(MachineFunction &MF) {
1197 TM = static_cast<const PPCTargetMachine *>(&MF.getTarget());
1198 TII = TM->getInstrInfo();
1200 bool Changed = false;
1202 // If the function does not have at least two blocks, then there is
1207 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
1208 MachineBasicBlock &B = *I++;
1209 if (processBlock(B))
1216 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1217 MachineFunctionPass::getAnalysisUsage(AU);
1222 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
1223 "PowerPC Early-Return Creation", false, false)
1225 char PPCEarlyReturn::ID = 0;
1227 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }