1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
29 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31 RI(*TM.getSubtargetImpl(), *this) {}
33 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
36 unsigned& sourceSubIdx,
37 unsigned& destSubIdx) const {
38 sourceSubIdx = destSubIdx = 0; // No sub-registers.
40 unsigned oc = MI.getOpcode();
41 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
43 assert(MI.getNumOperands() >= 3 &&
44 MI.getOperand(0).isReg() &&
45 MI.getOperand(1).isReg() &&
46 MI.getOperand(2).isReg() &&
47 "invalid PPC OR instruction!");
48 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49 sourceReg = MI.getOperand(1).getReg();
50 destReg = MI.getOperand(0).getReg();
53 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
54 assert(MI.getNumOperands() >= 3 &&
55 MI.getOperand(0).isReg() &&
56 MI.getOperand(2).isImm() &&
57 "invalid PPC ADDI instruction!");
58 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59 sourceReg = MI.getOperand(1).getReg();
60 destReg = MI.getOperand(0).getReg();
63 } else if (oc == PPC::ORI) { // ori r1, r2, 0
64 assert(MI.getNumOperands() >= 3 &&
65 MI.getOperand(0).isReg() &&
66 MI.getOperand(1).isReg() &&
67 MI.getOperand(2).isImm() &&
68 "invalid PPC ORI instruction!");
69 if (MI.getOperand(2).getImm() == 0) {
70 sourceReg = MI.getOperand(1).getReg();
71 destReg = MI.getOperand(0).getReg();
74 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75 oc == PPC::FMRSD) { // fmr r1, r2
76 assert(MI.getNumOperands() >= 2 &&
77 MI.getOperand(0).isReg() &&
78 MI.getOperand(1).isReg() &&
79 "invalid PPC FMR instruction");
80 sourceReg = MI.getOperand(1).getReg();
81 destReg = MI.getOperand(0).getReg();
83 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
84 assert(MI.getNumOperands() >= 2 &&
85 MI.getOperand(0).isReg() &&
86 MI.getOperand(1).isReg() &&
87 "invalid PPC MCRF instruction");
88 sourceReg = MI.getOperand(1).getReg();
89 destReg = MI.getOperand(0).getReg();
95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
113 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114 int &FrameIndex) const {
115 switch (MI->getOpcode()) {
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI()) {
123 FrameIndex = MI->getOperand(2).getIndex();
124 return MI->getOperand(0).getReg();
131 // commuteInstruction - We can commute rlwimi instructions, but only if the
132 // rotate amt is zero. We also have to munge the immediates a bit.
134 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135 MachineFunction &MF = *MI->getParent()->getParent();
137 // Normal instructions can be commuted the obvious way.
138 if (MI->getOpcode() != PPC::RLWIMI)
139 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
141 // Cannot commute if it has a non-zero rotate count.
142 if (MI->getOperand(3).getImm() != 0)
145 // If we have a zero rotate count, we have:
147 // Op0 = (Op1 & ~M) | (Op2 & M)
149 // M = mask((ME+1)&31, (MB-1)&31)
150 // Op0 = (Op2 & ~M) | (Op1 & M)
153 unsigned Reg0 = MI->getOperand(0).getReg();
154 unsigned Reg1 = MI->getOperand(1).getReg();
155 unsigned Reg2 = MI->getOperand(2).getReg();
156 bool Reg1IsKill = MI->getOperand(1).isKill();
157 bool Reg2IsKill = MI->getOperand(2).isKill();
158 bool ChangeReg0 = false;
159 // If machine instrs are no longer in two-address forms, update
160 // destination register as well.
162 // Must be two address instruction!
163 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164 "Expecting a two-address instruction!");
170 unsigned MB = MI->getOperand(4).getImm();
171 unsigned ME = MI->getOperand(5).getImm();
174 // Create a new instruction.
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176 bool Reg0IsDead = MI->getOperand(0).isDead();
177 return BuildMI(MF, MI->getDesc())
178 .addReg(Reg0, true, false, false, Reg0IsDead)
179 .addReg(Reg2, false, false, Reg2IsKill)
180 .addReg(Reg1, false, false, Reg1IsKill)
182 .addImm((MB-1) & 31);
186 MI->getOperand(0).setReg(Reg2);
187 MI->getOperand(2).setReg(Reg1);
188 MI->getOperand(1).setReg(Reg2);
189 MI->getOperand(2).setIsKill(Reg1IsKill);
190 MI->getOperand(1).setIsKill(Reg2IsKill);
192 // Swap the mask around.
193 MI->getOperand(4).setImm((ME+1) & 31);
194 MI->getOperand(5).setImm((MB-1) & 31);
198 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator MI) const {
200 BuildMI(MBB, MI, get(PPC::NOP));
205 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
206 MachineBasicBlock *&FBB,
207 SmallVectorImpl<MachineOperand> &Cond,
208 bool AllowModify) const {
209 // If the block has no terminators, it just falls into the block after it.
210 MachineBasicBlock::iterator I = MBB.end();
211 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
214 // Get the last instruction in the block.
215 MachineInstr *LastInst = I;
217 // If there is only one terminator instruction, process it.
218 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
219 if (LastInst->getOpcode() == PPC::B) {
220 TBB = LastInst->getOperand(0).getMBB();
222 } else if (LastInst->getOpcode() == PPC::BCC) {
223 // Block ends with fall-through condbranch.
224 TBB = LastInst->getOperand(2).getMBB();
225 Cond.push_back(LastInst->getOperand(0));
226 Cond.push_back(LastInst->getOperand(1));
229 // Otherwise, don't know what this is.
233 // Get the instruction before it if it's a terminator.
234 MachineInstr *SecondLastInst = I;
236 // If there are three terminators, we don't know what sort of block this is.
237 if (SecondLastInst && I != MBB.begin() &&
238 isUnpredicatedTerminator(--I))
241 // If the block ends with PPC::B and PPC:BCC, handle it.
242 if (SecondLastInst->getOpcode() == PPC::BCC &&
243 LastInst->getOpcode() == PPC::B) {
244 TBB = SecondLastInst->getOperand(2).getMBB();
245 Cond.push_back(SecondLastInst->getOperand(0));
246 Cond.push_back(SecondLastInst->getOperand(1));
247 FBB = LastInst->getOperand(0).getMBB();
251 // If the block ends with two PPC:Bs, handle it. The second one is not
252 // executed, so remove it.
253 if (SecondLastInst->getOpcode() == PPC::B &&
254 LastInst->getOpcode() == PPC::B) {
255 TBB = SecondLastInst->getOperand(0).getMBB();
258 I->eraseFromParent();
262 // Otherwise, can't handle this.
266 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
267 MachineBasicBlock::iterator I = MBB.end();
268 if (I == MBB.begin()) return 0;
270 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
273 // Remove the branch.
274 I->eraseFromParent();
278 if (I == MBB.begin()) return 1;
280 if (I->getOpcode() != PPC::BCC)
283 // Remove the branch.
284 I->eraseFromParent();
289 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
290 MachineBasicBlock *FBB,
291 const SmallVectorImpl<MachineOperand> &Cond) const {
292 // Shouldn't be a fall through.
293 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
294 assert((Cond.size() == 2 || Cond.size() == 0) &&
295 "PPC branch conditions have two components!");
299 if (Cond.empty()) // Unconditional branch
300 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
301 else // Conditional branch
302 BuildMI(&MBB, get(PPC::BCC))
303 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
307 // Two-way Conditional Branch.
308 BuildMI(&MBB, get(PPC::BCC))
309 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
310 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
314 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator MI,
316 unsigned DestReg, unsigned SrcReg,
317 const TargetRegisterClass *DestRC,
318 const TargetRegisterClass *SrcRC) const {
319 if (DestRC != SrcRC) {
320 // Not yet supported!
324 if (DestRC == PPC::GPRCRegisterClass) {
325 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
326 } else if (DestRC == PPC::G8RCRegisterClass) {
327 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
328 } else if (DestRC == PPC::F4RCRegisterClass) {
329 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
330 } else if (DestRC == PPC::F8RCRegisterClass) {
331 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
332 } else if (DestRC == PPC::CRRCRegisterClass) {
333 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
334 } else if (DestRC == PPC::VRRCRegisterClass) {
335 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
336 } else if (DestRC == PPC::CRBITRCRegisterClass) {
337 BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
339 // Attempt to copy register that is not GPR or FPR
347 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
348 unsigned SrcReg, bool isKill,
350 const TargetRegisterClass *RC,
351 SmallVectorImpl<MachineInstr*> &NewMIs) const{
352 if (RC == PPC::GPRCRegisterClass) {
353 if (SrcReg != PPC::LR) {
354 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
355 .addReg(SrcReg, false, false, isKill),
358 // FIXME: this spills LR immediately to memory in one step. To do this,
359 // we use R11, which we know cannot be used in the prolog/epilog. This is
361 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
362 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
363 .addReg(PPC::R11, false, false, isKill),
366 } else if (RC == PPC::G8RCRegisterClass) {
367 if (SrcReg != PPC::LR8) {
368 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
369 .addReg(SrcReg, false, false, isKill), FrameIdx));
371 // FIXME: this spills LR immediately to memory in one step. To do this,
372 // we use R11, which we know cannot be used in the prolog/epilog. This is
374 NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
375 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
376 .addReg(PPC::X11, false, false, isKill), FrameIdx));
378 } else if (RC == PPC::F8RCRegisterClass) {
379 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
380 .addReg(SrcReg, false, false, isKill), FrameIdx));
381 } else if (RC == PPC::F4RCRegisterClass) {
382 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
383 .addReg(SrcReg, false, false, isKill), FrameIdx));
384 } else if (RC == PPC::CRRCRegisterClass) {
385 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
386 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
387 // FIXME (64-bit): Enable
388 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
389 .addReg(SrcReg, false, false, isKill),
393 // FIXME: We use R0 here, because it isn't available for RA. We need to
394 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
395 // to save all of the CRBits.
396 NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
398 // If the saved register wasn't CR0, shift the bits left so that they are
400 if (SrcReg != PPC::CR0) {
401 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
402 // rlwinm r0, r0, ShiftBits, 0, 31.
403 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
404 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
407 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
408 .addReg(PPC::R0, false, false, isKill),
411 } else if (RC == PPC::CRBITRCRegisterClass) {
412 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
413 // backend currently only uses CR1EQ as an individual bit, this should
414 // not cause any bug. If we need other uses of CR bits, the following
415 // code may be invalid.
417 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
419 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
421 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
423 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
425 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
427 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
429 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
431 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
434 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
435 PPC::CRRCRegisterClass, NewMIs);
437 } else if (RC == PPC::VRRCRegisterClass) {
438 // We don't have indexed addressing for vector loads. Emit:
442 // FIXME: We use R0 here, because it isn't available for RA.
443 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
445 NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
446 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
448 assert(0 && "Unknown regclass!");
456 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator MI,
458 unsigned SrcReg, bool isKill, int FrameIdx,
459 const TargetRegisterClass *RC) const {
460 MachineFunction &MF = *MBB.getParent();
461 SmallVector<MachineInstr*, 4> NewMIs;
463 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
464 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
465 FuncInfo->setSpillsCR();
468 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
469 MBB.insert(MI, NewMIs[i]);
472 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
474 SmallVectorImpl<MachineOperand> &Addr,
475 const TargetRegisterClass *RC,
476 SmallVectorImpl<MachineInstr*> &NewMIs) const{
477 if (Addr[0].isFI()) {
478 if (StoreRegToStackSlot(MF, SrcReg, isKill,
479 Addr[0].getIndex(), RC, NewMIs)) {
480 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
481 FuncInfo->setSpillsCR();
488 if (RC == PPC::GPRCRegisterClass) {
490 } else if (RC == PPC::G8RCRegisterClass) {
492 } else if (RC == PPC::F8RCRegisterClass) {
494 } else if (RC == PPC::F4RCRegisterClass) {
496 } else if (RC == PPC::VRRCRegisterClass) {
499 assert(0 && "Unknown regclass!");
502 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
503 .addReg(SrcReg, false, false, isKill);
504 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
505 MachineOperand &MO = Addr[i];
507 MIB.addReg(MO.getReg());
509 MIB.addImm(MO.getImm());
511 MIB.addFrameIndex(MO.getIndex());
513 NewMIs.push_back(MIB);
518 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
519 unsigned DestReg, int FrameIdx,
520 const TargetRegisterClass *RC,
521 SmallVectorImpl<MachineInstr*> &NewMIs)const{
522 if (RC == PPC::GPRCRegisterClass) {
523 if (DestReg != PPC::LR) {
524 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
527 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
529 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
531 } else if (RC == PPC::G8RCRegisterClass) {
532 if (DestReg != PPC::LR8) {
533 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
536 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
538 NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
540 } else if (RC == PPC::F8RCRegisterClass) {
541 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
543 } else if (RC == PPC::F4RCRegisterClass) {
544 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
546 } else if (RC == PPC::CRRCRegisterClass) {
547 // FIXME: We use R0 here, because it isn't available for RA.
548 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
551 // If the reloaded register isn't CR0, shift the bits right so that they are
552 // in the right CR's slot.
553 if (DestReg != PPC::CR0) {
554 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
555 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
556 NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
557 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
560 NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
561 } else if (RC == PPC::CRBITRCRegisterClass) {
564 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
566 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
568 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
570 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
572 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
574 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
576 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
578 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
581 return LoadRegFromStackSlot(MF, Reg, FrameIdx,
582 PPC::CRRCRegisterClass, NewMIs);
584 } else if (RC == PPC::VRRCRegisterClass) {
585 // We don't have indexed addressing for vector loads. Emit:
589 // FIXME: We use R0 here, because it isn't available for RA.
590 NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
592 NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
595 assert(0 && "Unknown regclass!");
601 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
602 MachineBasicBlock::iterator MI,
603 unsigned DestReg, int FrameIdx,
604 const TargetRegisterClass *RC) const {
605 MachineFunction &MF = *MBB.getParent();
606 SmallVector<MachineInstr*, 4> NewMIs;
607 LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
608 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
609 MBB.insert(MI, NewMIs[i]);
612 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
613 SmallVectorImpl<MachineOperand> &Addr,
614 const TargetRegisterClass *RC,
615 SmallVectorImpl<MachineInstr*> &NewMIs)const{
616 if (Addr[0].isFI()) {
617 LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
622 if (RC == PPC::GPRCRegisterClass) {
623 assert(DestReg != PPC::LR && "Can't handle this yet!");
625 } else if (RC == PPC::G8RCRegisterClass) {
626 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
628 } else if (RC == PPC::F8RCRegisterClass) {
630 } else if (RC == PPC::F4RCRegisterClass) {
632 } else if (RC == PPC::VRRCRegisterClass) {
635 assert(0 && "Unknown regclass!");
638 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
639 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
640 MachineOperand &MO = Addr[i];
642 MIB.addReg(MO.getReg());
644 MIB.addImm(MO.getImm());
646 MIB.addFrameIndex(MO.getIndex());
648 NewMIs.push_back(MIB);
652 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
653 /// copy instructions, turning them into load/store instructions.
654 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
656 const SmallVectorImpl<unsigned> &Ops,
657 int FrameIndex) const {
658 if (Ops.size() != 1) return NULL;
660 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
661 // it takes more than one instruction to store it.
662 unsigned Opc = MI->getOpcode();
663 unsigned OpNum = Ops[0];
665 MachineInstr *NewMI = NULL;
666 if ((Opc == PPC::OR &&
667 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
668 if (OpNum == 0) { // move -> store
669 unsigned InReg = MI->getOperand(1).getReg();
670 bool isKill = MI->getOperand(1).isKill();
671 NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
672 .addReg(InReg, false, false, isKill),
674 } else { // move -> load
675 unsigned OutReg = MI->getOperand(0).getReg();
676 bool isDead = MI->getOperand(0).isDead();
677 NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
678 .addReg(OutReg, true, false, false, isDead),
681 } else if ((Opc == PPC::OR8 &&
682 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
683 if (OpNum == 0) { // move -> store
684 unsigned InReg = MI->getOperand(1).getReg();
685 bool isKill = MI->getOperand(1).isKill();
686 NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
687 .addReg(InReg, false, false, isKill),
689 } else { // move -> load
690 unsigned OutReg = MI->getOperand(0).getReg();
691 bool isDead = MI->getOperand(0).isDead();
692 NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
693 .addReg(OutReg, true, false, false, isDead),
696 } else if (Opc == PPC::FMRD) {
697 if (OpNum == 0) { // move -> store
698 unsigned InReg = MI->getOperand(1).getReg();
699 bool isKill = MI->getOperand(1).isKill();
700 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
701 .addReg(InReg, false, false, isKill),
703 } else { // move -> load
704 unsigned OutReg = MI->getOperand(0).getReg();
705 bool isDead = MI->getOperand(0).isDead();
706 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
707 .addReg(OutReg, true, false, false, isDead),
710 } else if (Opc == PPC::FMRS) {
711 if (OpNum == 0) { // move -> store
712 unsigned InReg = MI->getOperand(1).getReg();
713 bool isKill = MI->getOperand(1).isKill();
714 NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
715 .addReg(InReg, false, false, isKill),
717 } else { // move -> load
718 unsigned OutReg = MI->getOperand(0).getReg();
719 bool isDead = MI->getOperand(0).isDead();
720 NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
721 .addReg(OutReg, true, false, false, isDead),
729 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
730 const SmallVectorImpl<unsigned> &Ops) const {
731 if (Ops.size() != 1) return false;
733 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
734 // it takes more than one instruction to store it.
735 unsigned Opc = MI->getOpcode();
737 if ((Opc == PPC::OR &&
738 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
740 else if ((Opc == PPC::OR8 &&
741 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
743 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
750 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
751 if (MBB.empty()) return false;
753 switch (MBB.back().getOpcode()) {
754 case PPC::BLR: // Return.
755 case PPC::B: // Uncond branch.
756 case PPC::BCTR: // Indirect branch.
758 default: return false;
763 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
764 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
765 // Leave the CR# the same, but invert the condition.
766 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
770 /// GetInstSize - Return the number of bytes of code the specified
771 /// instruction may be. This returns the maximum number of bytes.
773 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
774 switch (MI->getOpcode()) {
775 case PPC::INLINEASM: { // Inline Asm: Variable size.
776 const MachineFunction *MF = MI->getParent()->getParent();
777 const char *AsmStr = MI->getOperand(0).getSymbolName();
778 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
785 return 4; // PowerPC instructions are all 4 bytes