1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
29 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31 RI(*TM.getSubtargetImpl(), *this) {}
33 /// getPointerRegClass - Return the register class to use to hold pointers.
34 /// This is used for addressing modes.
35 const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
36 if (TM.getSubtargetImpl()->isPPC64())
37 return &PPC::G8RCRegClass;
39 return &PPC::GPRCRegClass;
43 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
45 unsigned& destReg) const {
46 unsigned oc = MI.getOpcode();
47 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
49 assert(MI.getNumOperands() >= 3 &&
50 MI.getOperand(0).isRegister() &&
51 MI.getOperand(1).isRegister() &&
52 MI.getOperand(2).isRegister() &&
53 "invalid PPC OR instruction!");
54 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55 sourceReg = MI.getOperand(1).getReg();
56 destReg = MI.getOperand(0).getReg();
59 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
60 assert(MI.getNumOperands() >= 3 &&
61 MI.getOperand(0).isRegister() &&
62 MI.getOperand(2).isImmediate() &&
63 "invalid PPC ADDI instruction!");
64 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
65 sourceReg = MI.getOperand(1).getReg();
66 destReg = MI.getOperand(0).getReg();
69 } else if (oc == PPC::ORI) { // ori r1, r2, 0
70 assert(MI.getNumOperands() >= 3 &&
71 MI.getOperand(0).isRegister() &&
72 MI.getOperand(1).isRegister() &&
73 MI.getOperand(2).isImmediate() &&
74 "invalid PPC ORI instruction!");
75 if (MI.getOperand(2).getImm() == 0) {
76 sourceReg = MI.getOperand(1).getReg();
77 destReg = MI.getOperand(0).getReg();
80 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
81 oc == PPC::FMRSD) { // fmr r1, r2
82 assert(MI.getNumOperands() >= 2 &&
83 MI.getOperand(0).isRegister() &&
84 MI.getOperand(1).isRegister() &&
85 "invalid PPC FMR instruction");
86 sourceReg = MI.getOperand(1).getReg();
87 destReg = MI.getOperand(0).getReg();
89 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
90 assert(MI.getNumOperands() >= 2 &&
91 MI.getOperand(0).isRegister() &&
92 MI.getOperand(1).isRegister() &&
93 "invalid PPC MCRF instruction");
94 sourceReg = MI.getOperand(1).getReg();
95 destReg = MI.getOperand(0).getReg();
101 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
102 int &FrameIndex) const {
103 switch (MI->getOpcode()) {
109 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
110 MI->getOperand(2).isFI()) {
111 FrameIndex = MI->getOperand(2).getIndex();
112 return MI->getOperand(0).getReg();
119 unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
120 int &FrameIndex) const {
121 switch (MI->getOpcode()) {
127 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
128 MI->getOperand(2).isFI()) {
129 FrameIndex = MI->getOperand(2).getIndex();
130 return MI->getOperand(0).getReg();
137 // commuteInstruction - We can commute rlwimi instructions, but only if the
138 // rotate amt is zero. We also have to munge the immediates a bit.
139 MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
140 // Normal instructions can be commuted the obvious way.
141 if (MI->getOpcode() != PPC::RLWIMI)
142 return TargetInstrInfoImpl::commuteInstruction(MI);
144 // Cannot commute if it has a non-zero rotate count.
145 if (MI->getOperand(3).getImm() != 0)
148 // If we have a zero rotate count, we have:
150 // Op0 = (Op1 & ~M) | (Op2 & M)
152 // M = mask((ME+1)&31, (MB-1)&31)
153 // Op0 = (Op2 & ~M) | (Op1 & M)
156 unsigned Reg0 = MI->getOperand(0).getReg();
157 unsigned Reg1 = MI->getOperand(1).getReg();
158 unsigned Reg2 = MI->getOperand(2).getReg();
159 bool Reg1IsKill = MI->getOperand(1).isKill();
160 bool Reg2IsKill = MI->getOperand(2).isKill();
161 // If machine instrs are no longer in two-address forms, update
162 // destination register as well.
164 // Must be two address instruction!
165 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
166 "Expecting a two-address instruction!");
167 MI->getOperand(0).setReg(Reg2);
170 MI->getOperand(2).setReg(Reg1);
171 MI->getOperand(1).setReg(Reg2);
172 MI->getOperand(2).setIsKill(Reg1IsKill);
173 MI->getOperand(1).setIsKill(Reg2IsKill);
175 // Swap the mask around.
176 unsigned MB = MI->getOperand(4).getImm();
177 unsigned ME = MI->getOperand(5).getImm();
178 MI->getOperand(4).setImm((ME+1) & 31);
179 MI->getOperand(5).setImm((MB-1) & 31);
183 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI) const {
185 BuildMI(MBB, MI, get(PPC::NOP));
190 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
191 MachineBasicBlock *&FBB,
192 std::vector<MachineOperand> &Cond) const {
193 // If the block has no terminators, it just falls into the block after it.
194 MachineBasicBlock::iterator I = MBB.end();
195 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
198 // Get the last instruction in the block.
199 MachineInstr *LastInst = I;
201 // If there is only one terminator instruction, process it.
202 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
203 if (LastInst->getOpcode() == PPC::B) {
204 TBB = LastInst->getOperand(0).getMBB();
206 } else if (LastInst->getOpcode() == PPC::BCC) {
207 // Block ends with fall-through condbranch.
208 TBB = LastInst->getOperand(2).getMBB();
209 Cond.push_back(LastInst->getOperand(0));
210 Cond.push_back(LastInst->getOperand(1));
213 // Otherwise, don't know what this is.
217 // Get the instruction before it if it's a terminator.
218 MachineInstr *SecondLastInst = I;
220 // If there are three terminators, we don't know what sort of block this is.
221 if (SecondLastInst && I != MBB.begin() &&
222 isUnpredicatedTerminator(--I))
225 // If the block ends with PPC::B and PPC:BCC, handle it.
226 if (SecondLastInst->getOpcode() == PPC::BCC &&
227 LastInst->getOpcode() == PPC::B) {
228 TBB = SecondLastInst->getOperand(2).getMBB();
229 Cond.push_back(SecondLastInst->getOperand(0));
230 Cond.push_back(SecondLastInst->getOperand(1));
231 FBB = LastInst->getOperand(0).getMBB();
235 // If the block ends with two PPC:Bs, handle it. The second one is not
236 // executed, so remove it.
237 if (SecondLastInst->getOpcode() == PPC::B &&
238 LastInst->getOpcode() == PPC::B) {
239 TBB = SecondLastInst->getOperand(0).getMBB();
241 I->eraseFromParent();
245 // Otherwise, can't handle this.
249 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
250 MachineBasicBlock::iterator I = MBB.end();
251 if (I == MBB.begin()) return 0;
253 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
256 // Remove the branch.
257 I->eraseFromParent();
261 if (I == MBB.begin()) return 1;
263 if (I->getOpcode() != PPC::BCC)
266 // Remove the branch.
267 I->eraseFromParent();
272 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
273 MachineBasicBlock *FBB,
274 const std::vector<MachineOperand> &Cond) const {
275 // Shouldn't be a fall through.
276 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
277 assert((Cond.size() == 2 || Cond.size() == 0) &&
278 "PPC branch conditions have two components!");
282 if (Cond.empty()) // Unconditional branch
283 BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
284 else // Conditional branch
285 BuildMI(&MBB, get(PPC::BCC))
286 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
290 // Two-way Conditional Branch.
291 BuildMI(&MBB, get(PPC::BCC))
292 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
293 BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
297 void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator MI,
299 unsigned DestReg, unsigned SrcReg,
300 const TargetRegisterClass *DestRC,
301 const TargetRegisterClass *SrcRC) const {
302 if (DestRC != SrcRC) {
303 cerr << "Not yet supported!";
307 if (DestRC == PPC::GPRCRegisterClass) {
308 BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
309 } else if (DestRC == PPC::G8RCRegisterClass) {
310 BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
311 } else if (DestRC == PPC::F4RCRegisterClass) {
312 BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
313 } else if (DestRC == PPC::F8RCRegisterClass) {
314 BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
315 } else if (DestRC == PPC::CRRCRegisterClass) {
316 BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
317 } else if (DestRC == PPC::VRRCRegisterClass) {
318 BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
319 } else if (DestRC == PPC::CRBITRCRegisterClass) {
320 BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
322 cerr << "Attempt to copy register that is not GPR or FPR";
328 PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill,
330 const TargetRegisterClass *RC,
331 SmallVectorImpl<MachineInstr*> &NewMIs) const{
332 if (RC == PPC::GPRCRegisterClass) {
333 if (SrcReg != PPC::LR) {
334 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
335 .addReg(SrcReg, false, false, isKill),
338 // FIXME: this spills LR immediately to memory in one step. To do this,
339 // we use R11, which we know cannot be used in the prolog/epilog. This is
341 NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11));
342 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
343 .addReg(PPC::R11, false, false, isKill),
346 } else if (RC == PPC::G8RCRegisterClass) {
347 if (SrcReg != PPC::LR8) {
348 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
349 .addReg(SrcReg, false, false, isKill), FrameIdx));
351 // FIXME: this spills LR immediately to memory in one step. To do this,
352 // we use R11, which we know cannot be used in the prolog/epilog. This is
354 NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11));
355 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
356 .addReg(PPC::X11, false, false, isKill), FrameIdx));
358 } else if (RC == PPC::F8RCRegisterClass) {
359 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD))
360 .addReg(SrcReg, false, false, isKill), FrameIdx));
361 } else if (RC == PPC::F4RCRegisterClass) {
362 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS))
363 .addReg(SrcReg, false, false, isKill), FrameIdx));
364 } else if (RC == PPC::CRRCRegisterClass) {
365 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
366 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
367 // FIXME (64-bit): Enable
368 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
369 .addReg(SrcReg, false, false, isKill),
373 // FIXME: We use R0 here, because it isn't available for RA. We need to
374 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
375 // to save all of the CRBits.
376 NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0));
378 // If the saved register wasn't CR0, shift the bits left so that they are
380 if (SrcReg != PPC::CR0) {
381 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
382 // rlwinm r0, r0, ShiftBits, 0, 31.
383 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
384 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
387 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
388 .addReg(PPC::R0, false, false, isKill),
391 } else if (RC == PPC::CRBITRCRegisterClass) {
392 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
393 // backend currently only uses CR1EQ as an individual bit, this should
394 // not cause any bug. If we need other uses of CR bits, the following
395 // code may be invalid.
397 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
399 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
401 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
403 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
405 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
407 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
409 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
411 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
414 return StoreRegToStackSlot(Reg, isKill, FrameIdx,
415 PPC::CRRCRegisterClass, NewMIs);
417 } else if (RC == PPC::VRRCRegisterClass) {
418 // We don't have indexed addressing for vector loads. Emit:
422 // FIXME: We use R0 here, because it isn't available for RA.
423 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
425 NewMIs.push_back(BuildMI(get(PPC::STVX))
426 .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
428 assert(0 && "Unknown regclass!");
436 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator MI,
438 unsigned SrcReg, bool isKill, int FrameIdx,
439 const TargetRegisterClass *RC) const {
440 SmallVector<MachineInstr*, 4> NewMIs;
442 if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) {
443 PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
444 FuncInfo->setSpillsCR();
447 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
448 MBB.insert(MI, NewMIs[i]);
451 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
453 SmallVectorImpl<MachineOperand> &Addr,
454 const TargetRegisterClass *RC,
455 SmallVectorImpl<MachineInstr*> &NewMIs) const{
456 if (Addr[0].isFrameIndex()) {
457 if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) {
458 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
459 FuncInfo->setSpillsCR();
466 if (RC == PPC::GPRCRegisterClass) {
468 } else if (RC == PPC::G8RCRegisterClass) {
470 } else if (RC == PPC::F8RCRegisterClass) {
472 } else if (RC == PPC::F4RCRegisterClass) {
474 } else if (RC == PPC::VRRCRegisterClass) {
477 assert(0 && "Unknown regclass!");
480 MachineInstrBuilder MIB = BuildMI(get(Opc))
481 .addReg(SrcReg, false, false, isKill);
482 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
483 MachineOperand &MO = Addr[i];
485 MIB.addReg(MO.getReg());
486 else if (MO.isImmediate())
487 MIB.addImm(MO.getImm());
489 MIB.addFrameIndex(MO.getIndex());
491 NewMIs.push_back(MIB);
496 PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
497 const TargetRegisterClass *RC,
498 SmallVectorImpl<MachineInstr*> &NewMIs)const{
499 if (RC == PPC::GPRCRegisterClass) {
500 if (DestReg != PPC::LR) {
501 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg),
504 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11),
506 NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11));
508 } else if (RC == PPC::G8RCRegisterClass) {
509 if (DestReg != PPC::LR8) {
510 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg),
513 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11),
515 NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11));
517 } else if (RC == PPC::F8RCRegisterClass) {
518 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg),
520 } else if (RC == PPC::F4RCRegisterClass) {
521 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg),
523 } else if (RC == PPC::CRRCRegisterClass) {
524 // FIXME: We use R0 here, because it isn't available for RA.
525 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0),
528 // If the reloaded register isn't CR0, shift the bits right so that they are
529 // in the right CR's slot.
530 if (DestReg != PPC::CR0) {
531 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
532 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
533 NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
534 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
537 NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0));
538 } else if (RC == PPC::CRBITRCRegisterClass) {
541 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
543 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
545 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
547 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
549 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
551 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
553 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
555 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
558 return LoadRegFromStackSlot(Reg, FrameIdx,
559 PPC::CRRCRegisterClass, NewMIs);
561 } else if (RC == PPC::VRRCRegisterClass) {
562 // We don't have indexed addressing for vector loads. Emit:
566 // FIXME: We use R0 here, because it isn't available for RA.
567 NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
569 NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0)
572 assert(0 && "Unknown regclass!");
578 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
579 MachineBasicBlock::iterator MI,
580 unsigned DestReg, int FrameIdx,
581 const TargetRegisterClass *RC) const {
582 SmallVector<MachineInstr*, 4> NewMIs;
583 LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs);
584 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
585 MBB.insert(MI, NewMIs[i]);
588 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
589 SmallVectorImpl<MachineOperand> &Addr,
590 const TargetRegisterClass *RC,
591 SmallVectorImpl<MachineInstr*> &NewMIs)const{
592 if (Addr[0].isFrameIndex()) {
593 LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs);
598 if (RC == PPC::GPRCRegisterClass) {
599 assert(DestReg != PPC::LR && "Can't handle this yet!");
601 } else if (RC == PPC::G8RCRegisterClass) {
602 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
604 } else if (RC == PPC::F8RCRegisterClass) {
606 } else if (RC == PPC::F4RCRegisterClass) {
608 } else if (RC == PPC::VRRCRegisterClass) {
611 assert(0 && "Unknown regclass!");
614 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
615 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
616 MachineOperand &MO = Addr[i];
618 MIB.addReg(MO.getReg());
619 else if (MO.isImmediate())
620 MIB.addImm(MO.getImm());
622 MIB.addFrameIndex(MO.getIndex());
624 NewMIs.push_back(MIB);
628 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
629 /// copy instructions, turning them into load/store instructions.
630 MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
632 SmallVectorImpl<unsigned> &Ops,
633 int FrameIndex) const {
634 if (Ops.size() != 1) return NULL;
636 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
637 // it takes more than one instruction to store it.
638 unsigned Opc = MI->getOpcode();
639 unsigned OpNum = Ops[0];
641 MachineInstr *NewMI = NULL;
642 if ((Opc == PPC::OR &&
643 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
644 if (OpNum == 0) { // move -> store
645 unsigned InReg = MI->getOperand(1).getReg();
646 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
648 } else { // move -> load
649 unsigned OutReg = MI->getOperand(0).getReg();
650 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
653 } else if ((Opc == PPC::OR8 &&
654 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
655 if (OpNum == 0) { // move -> store
656 unsigned InReg = MI->getOperand(1).getReg();
657 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
659 } else { // move -> load
660 unsigned OutReg = MI->getOperand(0).getReg();
661 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
663 } else if (Opc == PPC::FMRD) {
664 if (OpNum == 0) { // move -> store
665 unsigned InReg = MI->getOperand(1).getReg();
666 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
668 } else { // move -> load
669 unsigned OutReg = MI->getOperand(0).getReg();
670 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
672 } else if (Opc == PPC::FMRS) {
673 if (OpNum == 0) { // move -> store
674 unsigned InReg = MI->getOperand(1).getReg();
675 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
677 } else { // move -> load
678 unsigned OutReg = MI->getOperand(0).getReg();
679 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
684 NewMI->copyKillDeadInfo(MI);
688 bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
689 SmallVectorImpl<unsigned> &Ops) const {
690 if (Ops.size() != 1) return false;
692 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
693 // it takes more than one instruction to store it.
694 unsigned Opc = MI->getOpcode();
696 if ((Opc == PPC::OR &&
697 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
699 else if ((Opc == PPC::OR8 &&
700 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
702 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
709 bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
710 if (MBB.empty()) return false;
712 switch (MBB.back().getOpcode()) {
713 case PPC::BLR: // Return.
714 case PPC::B: // Uncond branch.
715 case PPC::BCTR: // Indirect branch.
717 default: return false;
722 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
723 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
724 // Leave the CR# the same, but invert the condition.
725 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
729 /// GetInstSize - Return the number of bytes of code the specified
730 /// instruction may be. This returns the maximum number of bytes.
732 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
733 switch (MI->getOpcode()) {
734 case PPC::INLINEASM: { // Inline Asm: Variable size.
735 const MachineFunction *MF = MI->getParent()->getParent();
736 const char *AsmStr = MI->getOperand(0).getSymbolName();
737 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
743 return 4; // PowerPC instructions are all 4 bytes