1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/MC/MCAsmInfo.h"
29 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
30 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
35 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
36 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
37 RI(*TM.getSubtargetImpl(), *this) {}
39 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
42 unsigned& sourceSubIdx,
43 unsigned& destSubIdx) const {
44 sourceSubIdx = destSubIdx = 0; // No sub-registers.
46 unsigned oc = MI.getOpcode();
47 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
49 assert(MI.getNumOperands() >= 3 &&
50 MI.getOperand(0).isReg() &&
51 MI.getOperand(1).isReg() &&
52 MI.getOperand(2).isReg() &&
53 "invalid PPC OR instruction!");
54 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55 sourceReg = MI.getOperand(1).getReg();
56 destReg = MI.getOperand(0).getReg();
59 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
60 assert(MI.getNumOperands() >= 3 &&
61 MI.getOperand(0).isReg() &&
62 MI.getOperand(2).isImm() &&
63 "invalid PPC ADDI instruction!");
64 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
65 sourceReg = MI.getOperand(1).getReg();
66 destReg = MI.getOperand(0).getReg();
69 } else if (oc == PPC::ORI) { // ori r1, r2, 0
70 assert(MI.getNumOperands() >= 3 &&
71 MI.getOperand(0).isReg() &&
72 MI.getOperand(1).isReg() &&
73 MI.getOperand(2).isImm() &&
74 "invalid PPC ORI instruction!");
75 if (MI.getOperand(2).getImm() == 0) {
76 sourceReg = MI.getOperand(1).getReg();
77 destReg = MI.getOperand(0).getReg();
80 } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
81 assert(MI.getNumOperands() >= 2 &&
82 MI.getOperand(0).isReg() &&
83 MI.getOperand(1).isReg() &&
84 "invalid PPC FMR instruction");
85 sourceReg = MI.getOperand(1).getReg();
86 destReg = MI.getOperand(0).getReg();
88 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
89 assert(MI.getNumOperands() >= 2 &&
90 MI.getOperand(0).isReg() &&
91 MI.getOperand(1).isReg() &&
92 "invalid PPC MCRF instruction");
93 sourceReg = MI.getOperand(1).getReg();
94 destReg = MI.getOperand(0).getReg();
100 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
108 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109 MI->getOperand(2).isFI()) {
110 FrameIndex = MI->getOperand(2).getIndex();
111 return MI->getOperand(0).getReg();
118 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
119 int &FrameIndex) const {
120 switch (MI->getOpcode()) {
126 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127 MI->getOperand(2).isFI()) {
128 FrameIndex = MI->getOperand(2).getIndex();
129 return MI->getOperand(0).getReg();
136 // commuteInstruction - We can commute rlwimi instructions, but only if the
137 // rotate amt is zero. We also have to munge the immediates a bit.
139 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
140 MachineFunction &MF = *MI->getParent()->getParent();
142 // Normal instructions can be commuted the obvious way.
143 if (MI->getOpcode() != PPC::RLWIMI)
144 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
146 // Cannot commute if it has a non-zero rotate count.
147 if (MI->getOperand(3).getImm() != 0)
150 // If we have a zero rotate count, we have:
152 // Op0 = (Op1 & ~M) | (Op2 & M)
154 // M = mask((ME+1)&31, (MB-1)&31)
155 // Op0 = (Op2 & ~M) | (Op1 & M)
158 unsigned Reg0 = MI->getOperand(0).getReg();
159 unsigned Reg1 = MI->getOperand(1).getReg();
160 unsigned Reg2 = MI->getOperand(2).getReg();
161 bool Reg1IsKill = MI->getOperand(1).isKill();
162 bool Reg2IsKill = MI->getOperand(2).isKill();
163 bool ChangeReg0 = false;
164 // If machine instrs are no longer in two-address forms, update
165 // destination register as well.
167 // Must be two address instruction!
168 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
169 "Expecting a two-address instruction!");
175 unsigned MB = MI->getOperand(4).getImm();
176 unsigned ME = MI->getOperand(5).getImm();
179 // Create a new instruction.
180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
181 bool Reg0IsDead = MI->getOperand(0).isDead();
182 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
183 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
184 .addReg(Reg2, getKillRegState(Reg2IsKill))
185 .addReg(Reg1, getKillRegState(Reg1IsKill))
187 .addImm((MB-1) & 31);
191 MI->getOperand(0).setReg(Reg2);
192 MI->getOperand(2).setReg(Reg1);
193 MI->getOperand(1).setReg(Reg2);
194 MI->getOperand(2).setIsKill(Reg1IsKill);
195 MI->getOperand(1).setIsKill(Reg2IsKill);
197 // Swap the mask around.
198 MI->getOperand(4).setImm((ME+1) & 31);
199 MI->getOperand(5).setImm((MB-1) & 31);
203 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
204 MachineBasicBlock::iterator MI) const {
206 BuildMI(MBB, MI, DL, get(PPC::NOP));
211 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
212 MachineBasicBlock *&FBB,
213 SmallVectorImpl<MachineOperand> &Cond,
214 bool AllowModify) const {
215 // If the block has no terminators, it just falls into the block after it.
216 MachineBasicBlock::iterator I = MBB.end();
217 if (I == MBB.begin())
220 while (I->isDebugValue()) {
221 if (I == MBB.begin())
225 if (!isUnpredicatedTerminator(I))
228 // Get the last instruction in the block.
229 MachineInstr *LastInst = I;
231 // If there is only one terminator instruction, process it.
232 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
233 if (LastInst->getOpcode() == PPC::B) {
234 if (!LastInst->getOperand(0).isMBB())
236 TBB = LastInst->getOperand(0).getMBB();
238 } else if (LastInst->getOpcode() == PPC::BCC) {
239 if (!LastInst->getOperand(2).isMBB())
241 // Block ends with fall-through condbranch.
242 TBB = LastInst->getOperand(2).getMBB();
243 Cond.push_back(LastInst->getOperand(0));
244 Cond.push_back(LastInst->getOperand(1));
247 // Otherwise, don't know what this is.
251 // Get the instruction before it if it's a terminator.
252 MachineInstr *SecondLastInst = I;
254 // If there are three terminators, we don't know what sort of block this is.
255 if (SecondLastInst && I != MBB.begin() &&
256 isUnpredicatedTerminator(--I))
259 // If the block ends with PPC::B and PPC:BCC, handle it.
260 if (SecondLastInst->getOpcode() == PPC::BCC &&
261 LastInst->getOpcode() == PPC::B) {
262 if (!SecondLastInst->getOperand(2).isMBB() ||
263 !LastInst->getOperand(0).isMBB())
265 TBB = SecondLastInst->getOperand(2).getMBB();
266 Cond.push_back(SecondLastInst->getOperand(0));
267 Cond.push_back(SecondLastInst->getOperand(1));
268 FBB = LastInst->getOperand(0).getMBB();
272 // If the block ends with two PPC:Bs, handle it. The second one is not
273 // executed, so remove it.
274 if (SecondLastInst->getOpcode() == PPC::B &&
275 LastInst->getOpcode() == PPC::B) {
276 if (!SecondLastInst->getOperand(0).isMBB())
278 TBB = SecondLastInst->getOperand(0).getMBB();
281 I->eraseFromParent();
285 // Otherwise, can't handle this.
289 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
290 MachineBasicBlock::iterator I = MBB.end();
291 if (I == MBB.begin()) return 0;
293 while (I->isDebugValue()) {
294 if (I == MBB.begin())
298 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
301 // Remove the branch.
302 I->eraseFromParent();
306 if (I == MBB.begin()) return 1;
308 if (I->getOpcode() != PPC::BCC)
311 // Remove the branch.
312 I->eraseFromParent();
317 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
318 MachineBasicBlock *FBB,
319 const SmallVectorImpl<MachineOperand> &Cond,
321 // Shouldn't be a fall through.
322 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
323 assert((Cond.size() == 2 || Cond.size() == 0) &&
324 "PPC branch conditions have two components!");
328 if (Cond.empty()) // Unconditional branch
329 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
330 else // Conditional branch
331 BuildMI(&MBB, DL, get(PPC::BCC))
332 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
336 // Two-way Conditional Branch.
337 BuildMI(&MBB, DL, get(PPC::BCC))
338 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
339 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
343 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
344 MachineBasicBlock::iterator I, DebugLoc DL,
345 unsigned DestReg, unsigned SrcReg,
346 bool KillSrc) const {
348 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
350 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
352 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
354 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
356 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
358 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
361 llvm_unreachable("Impossible reg-to-reg copy");
363 const TargetInstrDesc &TID = get(Opc);
364 if (TID.getNumOperands() == 3)
365 BuildMI(MBB, I, DL, TID, DestReg)
366 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
368 BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
372 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
373 unsigned SrcReg, bool isKill,
375 const TargetRegisterClass *RC,
376 SmallVectorImpl<MachineInstr*> &NewMIs) const{
378 if (RC == PPC::GPRCRegisterClass) {
379 if (SrcReg != PPC::LR) {
380 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
382 getKillRegState(isKill)),
385 // FIXME: this spills LR immediately to memory in one step. To do this,
386 // we use R11, which we know cannot be used in the prolog/epilog. This is
388 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
389 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
391 getKillRegState(isKill)),
394 } else if (RC == PPC::G8RCRegisterClass) {
395 if (SrcReg != PPC::LR8) {
396 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
398 getKillRegState(isKill)),
401 // FIXME: this spills LR immediately to memory in one step. To do this,
402 // we use R11, which we know cannot be used in the prolog/epilog. This is
404 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
405 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
407 getKillRegState(isKill)),
410 } else if (RC == PPC::F8RCRegisterClass) {
411 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
413 getKillRegState(isKill)),
415 } else if (RC == PPC::F4RCRegisterClass) {
416 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
418 getKillRegState(isKill)),
420 } else if (RC == PPC::CRRCRegisterClass) {
421 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
422 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
423 // FIXME (64-bit): Enable
424 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
426 getKillRegState(isKill)),
430 // FIXME: We need a scatch reg here. The trouble with using R0 is that
431 // it's possible for the stack frame to be so big the save location is
432 // out of range of immediate offsets, necessitating another register.
433 // We hack this on Darwin by reserving R2. It's probably broken on Linux
436 // We need to store the CR in the low 4-bits of the saved value. First,
437 // issue a MFCR to save all of the CRBits.
438 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
440 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCRpseud), ScratchReg)
441 .addReg(SrcReg, getKillRegState(isKill)));
443 // If the saved register wasn't CR0, shift the bits left so that they are
445 if (SrcReg != PPC::CR0) {
446 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
447 // rlwinm scratch, scratch, ShiftBits, 0, 31.
448 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
449 .addReg(ScratchReg).addImm(ShiftBits)
450 .addImm(0).addImm(31));
453 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
455 getKillRegState(isKill)),
458 } else if (RC == PPC::CRBITRCRegisterClass) {
459 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
460 // backend currently only uses CR1EQ as an individual bit, this should
461 // not cause any bug. If we need other uses of CR bits, the following
462 // code may be invalid.
464 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
465 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
467 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
468 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
470 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
471 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
473 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
474 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
476 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
477 SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
479 else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
480 SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
482 else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
483 SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
485 else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
486 SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
489 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
490 PPC::CRRCRegisterClass, NewMIs);
492 } else if (RC == PPC::VRRCRegisterClass) {
493 // We don't have indexed addressing for vector loads. Emit:
497 // FIXME: We use R0 here, because it isn't available for RA.
498 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
500 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
501 .addReg(SrcReg, getKillRegState(isKill))
505 llvm_unreachable("Unknown regclass!");
512 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator MI,
514 unsigned SrcReg, bool isKill, int FrameIdx,
515 const TargetRegisterClass *RC,
516 const TargetRegisterInfo *TRI) const {
517 MachineFunction &MF = *MBB.getParent();
518 SmallVector<MachineInstr*, 4> NewMIs;
520 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
521 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
522 FuncInfo->setSpillsCR();
525 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
526 MBB.insert(MI, NewMIs[i]);
530 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
531 unsigned DestReg, int FrameIdx,
532 const TargetRegisterClass *RC,
533 SmallVectorImpl<MachineInstr*> &NewMIs)const{
534 if (RC == PPC::GPRCRegisterClass) {
535 if (DestReg != PPC::LR) {
536 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
537 DestReg), FrameIdx));
539 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
540 PPC::R11), FrameIdx));
541 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
543 } else if (RC == PPC::G8RCRegisterClass) {
544 if (DestReg != PPC::LR8) {
545 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
548 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
549 PPC::R11), FrameIdx));
550 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
552 } else if (RC == PPC::F8RCRegisterClass) {
553 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
555 } else if (RC == PPC::F4RCRegisterClass) {
556 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
558 } else if (RC == PPC::CRRCRegisterClass) {
559 // FIXME: We need a scatch reg here. The trouble with using R0 is that
560 // it's possible for the stack frame to be so big the save location is
561 // out of range of immediate offsets, necessitating another register.
562 // We hack this on Darwin by reserving R2. It's probably broken on Linux
564 unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
566 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
567 ScratchReg), FrameIdx));
569 // If the reloaded register isn't CR0, shift the bits right so that they are
570 // in the right CR's slot.
571 if (DestReg != PPC::CR0) {
572 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
573 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
574 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
575 .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
579 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
580 .addReg(ScratchReg));
581 } else if (RC == PPC::CRBITRCRegisterClass) {
584 if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
585 DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
587 else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
588 DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
590 else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
591 DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
593 else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
594 DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
596 else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
597 DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
599 else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
600 DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
602 else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
603 DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
605 else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
606 DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
609 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
610 PPC::CRRCRegisterClass, NewMIs);
612 } else if (RC == PPC::VRRCRegisterClass) {
613 // We don't have indexed addressing for vector loads. Emit:
617 // FIXME: We use R0 here, because it isn't available for RA.
618 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
620 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
623 llvm_unreachable("Unknown regclass!");
628 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
629 MachineBasicBlock::iterator MI,
630 unsigned DestReg, int FrameIdx,
631 const TargetRegisterClass *RC,
632 const TargetRegisterInfo *TRI) const {
633 MachineFunction &MF = *MBB.getParent();
634 SmallVector<MachineInstr*, 4> NewMIs;
636 if (MI != MBB.end()) DL = MI->getDebugLoc();
637 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
638 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
639 MBB.insert(MI, NewMIs[i]);
643 PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
644 int FrameIx, uint64_t Offset,
647 MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
648 addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
653 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
654 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
655 // Leave the CR# the same, but invert the condition.
656 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
660 /// GetInstSize - Return the number of bytes of code the specified
661 /// instruction may be. This returns the maximum number of bytes.
663 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
664 switch (MI->getOpcode()) {
665 case PPC::INLINEASM: { // Inline Asm: Variable size.
666 const MachineFunction *MF = MI->getParent()->getParent();
667 const char *AsmStr = MI->getOperand(0).getSymbolName();
668 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
676 return 4; // PowerPC instructions are all 4 bytes