1 //===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCInstrInfo.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPredicates.h"
18 #include "PPCGenInstrInfo.inc"
19 #include "PPCTargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
27 extern cl::opt<bool> EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
29 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30 : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31 RI(*TM.getSubtargetImpl(), *this) {}
33 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
36 unsigned& sourceSubIdx,
37 unsigned& destSubIdx) const {
38 sourceSubIdx = destSubIdx = 0; // No sub-registers.
40 unsigned oc = MI.getOpcode();
41 if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42 oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
43 assert(MI.getNumOperands() >= 3 &&
44 MI.getOperand(0).isReg() &&
45 MI.getOperand(1).isReg() &&
46 MI.getOperand(2).isReg() &&
47 "invalid PPC OR instruction!");
48 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49 sourceReg = MI.getOperand(1).getReg();
50 destReg = MI.getOperand(0).getReg();
53 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
54 assert(MI.getNumOperands() >= 3 &&
55 MI.getOperand(0).isReg() &&
56 MI.getOperand(2).isImm() &&
57 "invalid PPC ADDI instruction!");
58 if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59 sourceReg = MI.getOperand(1).getReg();
60 destReg = MI.getOperand(0).getReg();
63 } else if (oc == PPC::ORI) { // ori r1, r2, 0
64 assert(MI.getNumOperands() >= 3 &&
65 MI.getOperand(0).isReg() &&
66 MI.getOperand(1).isReg() &&
67 MI.getOperand(2).isImm() &&
68 "invalid PPC ORI instruction!");
69 if (MI.getOperand(2).getImm() == 0) {
70 sourceReg = MI.getOperand(1).getReg();
71 destReg = MI.getOperand(0).getReg();
74 } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75 oc == PPC::FMRSD) { // fmr r1, r2
76 assert(MI.getNumOperands() >= 2 &&
77 MI.getOperand(0).isReg() &&
78 MI.getOperand(1).isReg() &&
79 "invalid PPC FMR instruction");
80 sourceReg = MI.getOperand(1).getReg();
81 destReg = MI.getOperand(0).getReg();
83 } else if (oc == PPC::MCRF) { // mcrf cr1, cr2
84 assert(MI.getNumOperands() >= 2 &&
85 MI.getOperand(0).isReg() &&
86 MI.getOperand(1).isReg() &&
87 "invalid PPC MCRF instruction");
88 sourceReg = MI.getOperand(1).getReg();
89 destReg = MI.getOperand(0).getReg();
95 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 switch (MI->getOpcode()) {
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
113 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114 int &FrameIndex) const {
115 switch (MI->getOpcode()) {
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI()) {
123 FrameIndex = MI->getOperand(2).getIndex();
124 return MI->getOperand(0).getReg();
131 // commuteInstruction - We can commute rlwimi instructions, but only if the
132 // rotate amt is zero. We also have to munge the immediates a bit.
134 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135 MachineFunction &MF = *MI->getParent()->getParent();
137 // Normal instructions can be commuted the obvious way.
138 if (MI->getOpcode() != PPC::RLWIMI)
139 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
141 // Cannot commute if it has a non-zero rotate count.
142 if (MI->getOperand(3).getImm() != 0)
145 // If we have a zero rotate count, we have:
147 // Op0 = (Op1 & ~M) | (Op2 & M)
149 // M = mask((ME+1)&31, (MB-1)&31)
150 // Op0 = (Op2 & ~M) | (Op1 & M)
153 unsigned Reg0 = MI->getOperand(0).getReg();
154 unsigned Reg1 = MI->getOperand(1).getReg();
155 unsigned Reg2 = MI->getOperand(2).getReg();
156 bool Reg1IsKill = MI->getOperand(1).isKill();
157 bool Reg2IsKill = MI->getOperand(2).isKill();
158 bool ChangeReg0 = false;
159 // If machine instrs are no longer in two-address forms, update
160 // destination register as well.
162 // Must be two address instruction!
163 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164 "Expecting a two-address instruction!");
170 unsigned MB = MI->getOperand(4).getImm();
171 unsigned ME = MI->getOperand(5).getImm();
174 // Create a new instruction.
175 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176 bool Reg0IsDead = MI->getOperand(0).isDead();
177 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
179 .addReg(Reg2, getKillRegState(Reg2IsKill))
180 .addReg(Reg1, getKillRegState(Reg1IsKill))
182 .addImm((MB-1) & 31);
186 MI->getOperand(0).setReg(Reg2);
187 MI->getOperand(2).setReg(Reg1);
188 MI->getOperand(1).setReg(Reg2);
189 MI->getOperand(2).setIsKill(Reg1IsKill);
190 MI->getOperand(1).setIsKill(Reg2IsKill);
192 // Swap the mask around.
193 MI->getOperand(4).setImm((ME+1) & 31);
194 MI->getOperand(5).setImm((MB-1) & 31);
198 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator MI) const {
200 DebugLoc DL = DebugLoc::getUnknownLoc();
201 if (MI != MBB.end()) DL = MI->getDebugLoc();
203 BuildMI(MBB, MI, DL, get(PPC::NOP));
208 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209 MachineBasicBlock *&FBB,
210 SmallVectorImpl<MachineOperand> &Cond,
211 bool AllowModify) const {
212 // If the block has no terminators, it just falls into the block after it.
213 MachineBasicBlock::iterator I = MBB.end();
214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
217 // Get the last instruction in the block.
218 MachineInstr *LastInst = I;
220 // If there is only one terminator instruction, process it.
221 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
222 if (LastInst->getOpcode() == PPC::B) {
223 if (!LastInst->getOperand(0).isMBB())
225 TBB = LastInst->getOperand(0).getMBB();
227 } else if (LastInst->getOpcode() == PPC::BCC) {
228 if (!LastInst->getOperand(2).isMBB())
230 // Block ends with fall-through condbranch.
231 TBB = LastInst->getOperand(2).getMBB();
232 Cond.push_back(LastInst->getOperand(0));
233 Cond.push_back(LastInst->getOperand(1));
236 // Otherwise, don't know what this is.
240 // Get the instruction before it if it's a terminator.
241 MachineInstr *SecondLastInst = I;
243 // If there are three terminators, we don't know what sort of block this is.
244 if (SecondLastInst && I != MBB.begin() &&
245 isUnpredicatedTerminator(--I))
248 // If the block ends with PPC::B and PPC:BCC, handle it.
249 if (SecondLastInst->getOpcode() == PPC::BCC &&
250 LastInst->getOpcode() == PPC::B) {
251 if (!SecondLastInst->getOperand(2).isMBB() ||
252 !LastInst->getOperand(0).isMBB())
254 TBB = SecondLastInst->getOperand(2).getMBB();
255 Cond.push_back(SecondLastInst->getOperand(0));
256 Cond.push_back(SecondLastInst->getOperand(1));
257 FBB = LastInst->getOperand(0).getMBB();
261 // If the block ends with two PPC:Bs, handle it. The second one is not
262 // executed, so remove it.
263 if (SecondLastInst->getOpcode() == PPC::B &&
264 LastInst->getOpcode() == PPC::B) {
265 if (!SecondLastInst->getOperand(0).isMBB())
267 TBB = SecondLastInst->getOperand(0).getMBB();
270 I->eraseFromParent();
274 // Otherwise, can't handle this.
278 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
279 MachineBasicBlock::iterator I = MBB.end();
280 if (I == MBB.begin()) return 0;
282 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
285 // Remove the branch.
286 I->eraseFromParent();
290 if (I == MBB.begin()) return 1;
292 if (I->getOpcode() != PPC::BCC)
295 // Remove the branch.
296 I->eraseFromParent();
301 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
302 MachineBasicBlock *FBB,
303 const SmallVectorImpl<MachineOperand> &Cond) const {
304 // FIXME this should probably have a DebugLoc argument
305 DebugLoc dl = DebugLoc::getUnknownLoc();
306 // Shouldn't be a fall through.
307 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
308 assert((Cond.size() == 2 || Cond.size() == 0) &&
309 "PPC branch conditions have two components!");
313 if (Cond.empty()) // Unconditional branch
314 BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
315 else // Conditional branch
316 BuildMI(&MBB, dl, get(PPC::BCC))
317 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
321 // Two-way Conditional Branch.
322 BuildMI(&MBB, dl, get(PPC::BCC))
323 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
324 BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
328 bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
329 MachineBasicBlock::iterator MI,
330 unsigned DestReg, unsigned SrcReg,
331 const TargetRegisterClass *DestRC,
332 const TargetRegisterClass *SrcRC) const {
333 if (DestRC != SrcRC) {
334 // Not yet supported!
338 DebugLoc DL = DebugLoc::getUnknownLoc();
339 if (MI != MBB.end()) DL = MI->getDebugLoc();
341 if (DestRC == PPC::GPRCRegisterClass) {
342 BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
343 } else if (DestRC == PPC::G8RCRegisterClass) {
344 BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
345 } else if (DestRC == PPC::F4RCRegisterClass) {
346 BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
347 } else if (DestRC == PPC::F8RCRegisterClass) {
348 BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
349 } else if (DestRC == PPC::CRRCRegisterClass) {
350 BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
351 } else if (DestRC == PPC::VRRCRegisterClass) {
352 BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
353 } else if (DestRC == PPC::CRBITRCRegisterClass) {
354 BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
356 // Attempt to copy register that is not GPR or FPR
364 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
365 unsigned SrcReg, bool isKill,
367 const TargetRegisterClass *RC,
368 SmallVectorImpl<MachineInstr*> &NewMIs) const{
369 DebugLoc DL = DebugLoc::getUnknownLoc();
370 if (RC == PPC::GPRCRegisterClass) {
371 if (SrcReg != PPC::LR) {
372 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
374 getKillRegState(isKill)),
377 // FIXME: this spills LR immediately to memory in one step. To do this,
378 // we use R11, which we know cannot be used in the prolog/epilog. This is
380 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
381 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
383 getKillRegState(isKill)),
386 } else if (RC == PPC::G8RCRegisterClass) {
387 if (SrcReg != PPC::LR8) {
388 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
390 getKillRegState(isKill)),
393 // FIXME: this spills LR immediately to memory in one step. To do this,
394 // we use R11, which we know cannot be used in the prolog/epilog. This is
396 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
397 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
399 getKillRegState(isKill)),
402 } else if (RC == PPC::F8RCRegisterClass) {
403 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
405 getKillRegState(isKill)),
407 } else if (RC == PPC::F4RCRegisterClass) {
408 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
410 getKillRegState(isKill)),
412 } else if (RC == PPC::CRRCRegisterClass) {
413 if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
414 (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
415 // FIXME (64-bit): Enable
416 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
418 getKillRegState(isKill)),
422 // FIXME: We use R0 here, because it isn't available for RA. We need to
423 // store the CR in the low 4-bits of the saved value. First, issue a MFCR
424 // to save all of the CRBits.
425 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
427 // If the saved register wasn't CR0, shift the bits left so that they are
429 if (SrcReg != PPC::CR0) {
430 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
431 // rlwinm r0, r0, ShiftBits, 0, 31.
432 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
433 .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
436 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
438 getKillRegState(isKill)),
441 } else if (RC == PPC::CRBITRCRegisterClass) {
442 // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
443 // backend currently only uses CR1EQ as an individual bit, this should
444 // not cause any bug. If we need other uses of CR bits, the following
445 // code may be invalid.
447 if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
449 else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
451 else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
453 else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
455 else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
457 else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
459 else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
461 else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
464 return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
465 PPC::CRRCRegisterClass, NewMIs);
467 } else if (RC == PPC::VRRCRegisterClass) {
468 // We don't have indexed addressing for vector loads. Emit:
472 // FIXME: We use R0 here, because it isn't available for RA.
473 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
475 NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
476 .addReg(SrcReg, getKillRegState(isKill))
480 assert(0 && "Unknown regclass!");
488 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
489 MachineBasicBlock::iterator MI,
490 unsigned SrcReg, bool isKill, int FrameIdx,
491 const TargetRegisterClass *RC) const {
492 MachineFunction &MF = *MBB.getParent();
493 SmallVector<MachineInstr*, 4> NewMIs;
495 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
496 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
497 FuncInfo->setSpillsCR();
500 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
501 MBB.insert(MI, NewMIs[i]);
504 void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
506 SmallVectorImpl<MachineOperand> &Addr,
507 const TargetRegisterClass *RC,
508 SmallVectorImpl<MachineInstr*> &NewMIs) const{
509 if (Addr[0].isFI()) {
510 if (StoreRegToStackSlot(MF, SrcReg, isKill,
511 Addr[0].getIndex(), RC, NewMIs)) {
512 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
513 FuncInfo->setSpillsCR();
519 DebugLoc DL = DebugLoc::getUnknownLoc();
521 if (RC == PPC::GPRCRegisterClass) {
523 } else if (RC == PPC::G8RCRegisterClass) {
525 } else if (RC == PPC::F8RCRegisterClass) {
527 } else if (RC == PPC::F4RCRegisterClass) {
529 } else if (RC == PPC::VRRCRegisterClass) {
532 assert(0 && "Unknown regclass!");
535 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
536 .addReg(SrcReg, getKillRegState(isKill));
537 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
538 MIB.addOperand(Addr[i]);
539 NewMIs.push_back(MIB);
544 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
545 unsigned DestReg, int FrameIdx,
546 const TargetRegisterClass *RC,
547 SmallVectorImpl<MachineInstr*> &NewMIs)const{
548 if (RC == PPC::GPRCRegisterClass) {
549 if (DestReg != PPC::LR) {
550 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
551 DestReg), FrameIdx));
553 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
554 PPC::R11), FrameIdx));
555 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
557 } else if (RC == PPC::G8RCRegisterClass) {
558 if (DestReg != PPC::LR8) {
559 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
562 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
563 PPC::R11), FrameIdx));
564 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
566 } else if (RC == PPC::F8RCRegisterClass) {
567 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
569 } else if (RC == PPC::F4RCRegisterClass) {
570 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
572 } else if (RC == PPC::CRRCRegisterClass) {
573 // FIXME: We use R0 here, because it isn't available for RA.
574 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
577 // If the reloaded register isn't CR0, shift the bits right so that they are
578 // in the right CR's slot.
579 if (DestReg != PPC::CR0) {
580 unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
581 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
582 NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
583 .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
586 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
587 } else if (RC == PPC::CRBITRCRegisterClass) {
590 if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
592 else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
594 else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
596 else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
598 else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
600 else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
602 else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
604 else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
607 return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
608 PPC::CRRCRegisterClass, NewMIs);
610 } else if (RC == PPC::VRRCRegisterClass) {
611 // We don't have indexed addressing for vector loads. Emit:
615 // FIXME: We use R0 here, because it isn't available for RA.
616 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
618 NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
621 assert(0 && "Unknown regclass!");
627 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
628 MachineBasicBlock::iterator MI,
629 unsigned DestReg, int FrameIdx,
630 const TargetRegisterClass *RC) const {
631 MachineFunction &MF = *MBB.getParent();
632 SmallVector<MachineInstr*, 4> NewMIs;
633 DebugLoc DL = DebugLoc::getUnknownLoc();
634 if (MI != MBB.end()) DL = MI->getDebugLoc();
635 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
636 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
637 MBB.insert(MI, NewMIs[i]);
640 void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
641 SmallVectorImpl<MachineOperand> &Addr,
642 const TargetRegisterClass *RC,
643 SmallVectorImpl<MachineInstr*> &NewMIs)const{
644 if (Addr[0].isFI()) {
645 LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
646 DestReg, Addr[0].getIndex(), RC, NewMIs);
651 if (RC == PPC::GPRCRegisterClass) {
652 assert(DestReg != PPC::LR && "Can't handle this yet!");
654 } else if (RC == PPC::G8RCRegisterClass) {
655 assert(DestReg != PPC::LR8 && "Can't handle this yet!");
657 } else if (RC == PPC::F8RCRegisterClass) {
659 } else if (RC == PPC::F4RCRegisterClass) {
661 } else if (RC == PPC::VRRCRegisterClass) {
664 assert(0 && "Unknown regclass!");
667 DebugLoc DL = DebugLoc::getUnknownLoc();
668 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
669 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
670 MIB.addOperand(Addr[i]);
671 NewMIs.push_back(MIB);
675 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
676 /// copy instructions, turning them into load/store instructions.
677 MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
679 const SmallVectorImpl<unsigned> &Ops,
680 int FrameIndex) const {
681 if (Ops.size() != 1) return NULL;
683 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
684 // it takes more than one instruction to store it.
685 unsigned Opc = MI->getOpcode();
686 unsigned OpNum = Ops[0];
688 MachineInstr *NewMI = NULL;
689 if ((Opc == PPC::OR &&
690 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
691 if (OpNum == 0) { // move -> store
692 unsigned InReg = MI->getOperand(1).getReg();
693 bool isKill = MI->getOperand(1).isKill();
694 bool isUndef = MI->getOperand(1).isUndef();
695 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
697 getKillRegState(isKill) |
698 getUndefRegState(isUndef)),
700 } else { // move -> load
701 unsigned OutReg = MI->getOperand(0).getReg();
702 bool isDead = MI->getOperand(0).isDead();
703 bool isUndef = MI->getOperand(0).isUndef();
704 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
707 getDeadRegState(isDead) |
708 getUndefRegState(isUndef)),
711 } else if ((Opc == PPC::OR8 &&
712 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
713 if (OpNum == 0) { // move -> store
714 unsigned InReg = MI->getOperand(1).getReg();
715 bool isKill = MI->getOperand(1).isKill();
716 bool isUndef = MI->getOperand(1).isUndef();
717 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
719 getKillRegState(isKill) |
720 getUndefRegState(isUndef)),
722 } else { // move -> load
723 unsigned OutReg = MI->getOperand(0).getReg();
724 bool isDead = MI->getOperand(0).isDead();
725 bool isUndef = MI->getOperand(0).isUndef();
726 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
729 getDeadRegState(isDead) |
730 getUndefRegState(isUndef)),
733 } else if (Opc == PPC::FMRD) {
734 if (OpNum == 0) { // move -> store
735 unsigned InReg = MI->getOperand(1).getReg();
736 bool isKill = MI->getOperand(1).isKill();
737 bool isUndef = MI->getOperand(1).isUndef();
738 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
740 getKillRegState(isKill) |
741 getUndefRegState(isUndef)),
743 } else { // move -> load
744 unsigned OutReg = MI->getOperand(0).getReg();
745 bool isDead = MI->getOperand(0).isDead();
746 bool isUndef = MI->getOperand(0).isUndef();
747 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
750 getDeadRegState(isDead) |
751 getUndefRegState(isUndef)),
754 } else if (Opc == PPC::FMRS) {
755 if (OpNum == 0) { // move -> store
756 unsigned InReg = MI->getOperand(1).getReg();
757 bool isKill = MI->getOperand(1).isKill();
758 bool isUndef = MI->getOperand(1).isUndef();
759 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
761 getKillRegState(isKill) |
762 getUndefRegState(isUndef)),
764 } else { // move -> load
765 unsigned OutReg = MI->getOperand(0).getReg();
766 bool isDead = MI->getOperand(0).isDead();
767 bool isUndef = MI->getOperand(0).isUndef();
768 NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
771 getDeadRegState(isDead) |
772 getUndefRegState(isUndef)),
780 bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
781 const SmallVectorImpl<unsigned> &Ops) const {
782 if (Ops.size() != 1) return false;
784 // Make sure this is a reg-reg copy. Note that we can't handle MCRF, because
785 // it takes more than one instruction to store it.
786 unsigned Opc = MI->getOpcode();
788 if ((Opc == PPC::OR &&
789 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
791 else if ((Opc == PPC::OR8 &&
792 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
794 else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
801 bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
802 if (MBB.empty()) return false;
804 switch (MBB.back().getOpcode()) {
805 case PPC::BLR: // Return.
806 case PPC::B: // Uncond branch.
807 case PPC::BCTR: // Indirect branch.
809 default: return false;
814 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
815 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
816 // Leave the CR# the same, but invert the condition.
817 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
821 /// GetInstSize - Return the number of bytes of code the specified
822 /// instruction may be. This returns the maximum number of bytes.
824 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
825 switch (MI->getOpcode()) {
826 case PPC::INLINEASM: { // Inline Asm: Variable size.
827 const MachineFunction *MF = MI->getParent()->getParent();
828 const char *AsmStr = MI->getOperand(0).getSymbolName();
829 return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
836 return 4; // PowerPC instructions are all 4 bytes