1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
40 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
41 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
42 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
43 class PPC970_MicroCode;
45 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
46 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
47 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
48 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
49 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
50 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
51 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
52 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
54 // Two joined instructions; used to emit two adjacent instructions as one.
55 // The itinerary from the first instruction is used for scheduling and
57 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
62 bit PPC64 = 0; // Default value, override with isPPC64
64 let Namespace = "PPC";
65 let Inst{0-5} = opcode1;
66 let Inst{32-37} = opcode2;
67 let OutOperandList = OOL;
68 let InOperandList = IOL;
69 let AsmString = asmstr;
72 bits<1> PPC970_First = 0;
73 bits<1> PPC970_Single = 0;
74 bits<1> PPC970_Cracked = 0;
75 bits<3> PPC970_Unit = 0;
77 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
78 /// these must be reflected there! See comments there for what these are.
79 let TSFlags{0} = PPC970_First;
80 let TSFlags{1} = PPC970_Single;
81 let TSFlags{2} = PPC970_Cracked;
82 let TSFlags{5-3} = PPC970_Unit;
86 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
87 InstrItinClass itin, list<dag> pattern>
88 : I<opcode, OOL, IOL, asmstr, itin> {
89 let Pattern = pattern;
97 class IForm_ext<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
98 string asmstr, InstrItinClass itin, list<dag> pattern>
99 : IForm<opcode, aa, lk, OOL, IOL, asmstr, itin, pattern> {
104 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
105 : I<opcode, OOL, IOL, asmstr, BrB> {
106 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
111 let BI{0-1} = BIBO{5-6};
112 let BI{2-4} = CR{0-2};
114 let Inst{6-10} = BIBO{4-0};
115 let Inst{11-15} = BI;
116 let Inst{16-29} = BD;
123 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
124 InstrItinClass itin, list<dag> pattern>
125 : I<opcode, OOL, IOL, asmstr, itin> {
130 let Pattern = pattern;
137 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
138 InstrItinClass itin, list<dag> pattern>
139 : I<opcode, OOL, IOL, asmstr, itin> {
143 let Pattern = pattern;
146 let Inst{11-15} = Addr{20-16}; // Base Reg
147 let Inst{16-31} = Addr{15-0}; // Displacement
150 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
151 InstrItinClass itin, list<dag> pattern>
152 : I<opcode, OOL, IOL, asmstr, itin> {
157 let Pattern = pattern;
165 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
166 InstrItinClass itin, list<dag> pattern>
167 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern>;
169 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
170 InstrItinClass itin, list<dag> pattern>
171 : I<opcode, OOL, IOL, asmstr, itin> {
175 let Pattern = pattern;
182 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
183 InstrItinClass itin, list<dag> pattern>
184 : I<opcode, OOL, IOL, asmstr, itin> {
189 let Pattern = pattern;
196 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
197 InstrItinClass itin, list<dag> pattern>
198 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
203 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
204 dag OOL, dag IOL, string asmstr,
205 InstrItinClass itin, list<dag> pattern>
206 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
210 let Pattern = pattern;
218 let Inst{43-47} = Addr{20-16}; // Base Reg
219 let Inst{48-63} = Addr{15-0}; // Displacement
222 // This is used to emit BL8+NOP.
223 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
224 dag OOL, dag IOL, string asmstr,
225 InstrItinClass itin, list<dag> pattern>
226 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
227 OOL, IOL, asmstr, itin, pattern> {
232 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
234 : I<opcode, OOL, IOL, asmstr, itin> {
243 let Inst{11-15} = RA;
247 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
249 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
253 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
257 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
259 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
265 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
266 InstrItinClass itin, list<dag> pattern>
267 : I<opcode, OOL, IOL, asmstr, itin> {
271 let Pattern = pattern;
273 let Inst{6-10} = RST;
274 let Inst{11-15} = DS_RA{18-14}; // Register #
275 let Inst{16-29} = DS_RA{13-0}; // Displacement.
276 let Inst{30-31} = xo;
279 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
280 InstrItinClass itin, list<dag> pattern>
281 : I<opcode, OOL, IOL, asmstr, itin> {
286 let Pattern = pattern;
288 let Inst{6-10} = RST;
289 let Inst{11-15} = RA;
290 let Inst{16-29} = DS;
291 let Inst{30-31} = xo;
295 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
296 InstrItinClass itin, list<dag> pattern>
297 : I<opcode, OOL, IOL, asmstr, itin> {
302 let Pattern = pattern;
304 bit RC = 0; // set by isDOT
306 let Inst{6-10} = RST;
309 let Inst{21-30} = xo;
313 // This is the same as XForm_base_r3xo, but the first two operands are swapped
314 // when code is emitted.
315 class XForm_base_r3xo_swapped
316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
323 bit RC = 0; // set by isDOT
325 let Inst{6-10} = RST;
328 let Inst{21-30} = xo;
333 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
334 InstrItinClass itin, list<dag> pattern>
335 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
337 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
338 InstrItinClass itin, list<dag> pattern>
339 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
340 let Pattern = pattern;
343 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
344 InstrItinClass itin, list<dag> pattern>
345 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
347 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
348 InstrItinClass itin, list<dag> pattern>
349 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
350 let Pattern = pattern;
353 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
354 InstrItinClass itin, list<dag> pattern>
355 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
357 let Pattern = pattern;
360 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
362 : I<opcode, OOL, IOL, asmstr, itin> {
371 let Inst{11-15} = RA;
372 let Inst{16-20} = RB;
373 let Inst{21-30} = xo;
377 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
379 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
383 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
385 : I<opcode, OOL, IOL, asmstr, itin> {
392 let Inst{11-15} = FRA;
393 let Inst{16-20} = FRB;
394 let Inst{21-30} = xo;
398 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
399 InstrItinClass itin, list<dag> pattern>
400 : I<opcode, OOL, IOL, asmstr, itin> {
401 let Pattern = pattern;
405 let Inst{21-30} = xo;
409 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
410 string asmstr, InstrItinClass itin, list<dag> pattern>
411 : I<opcode, OOL, IOL, asmstr, itin> {
412 let Pattern = pattern;
416 let Inst{21-30} = xo;
420 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
421 InstrItinClass itin, list<dag> pattern>
422 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
425 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 InstrItinClass itin, list<dag> pattern>
427 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
431 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
436 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
437 // numbers presumably relates to some document, but I haven't found it.
438 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
439 InstrItinClass itin, list<dag> pattern>
440 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
441 let Pattern = pattern;
443 bit RC = 0; // set by isDOT
445 let Inst{6-10} = RST;
447 let Inst{21-30} = xo;
450 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
451 InstrItinClass itin, list<dag> pattern>
452 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
453 let Pattern = pattern;
456 bit RC = 0; // set by isDOT
460 let Inst{21-30} = xo;
464 // DCB_Form - Form X instruction, used for dcb* instructions.
465 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
466 InstrItinClass itin, list<dag> pattern>
467 : I<31, OOL, IOL, asmstr, itin> {
471 let Pattern = pattern;
473 let Inst{6-10} = immfield;
476 let Inst{21-30} = xo;
481 // DSS_Form - Form X instruction, used for altivec dss* instructions.
482 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
483 InstrItinClass itin, list<dag> pattern>
484 : I<31, OOL, IOL, asmstr, itin> {
490 let Pattern = pattern;
494 let Inst{9-10} = STRM;
497 let Inst{21-30} = xo;
502 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
503 InstrItinClass itin, list<dag> pattern>
504 : I<opcode, OOL, IOL, asmstr, itin> {
509 let Pattern = pattern;
511 let Inst{6-10} = CRD;
512 let Inst{11-15} = CRA;
513 let Inst{16-20} = CRB;
514 let Inst{21-30} = xo;
518 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
519 InstrItinClass itin, list<dag> pattern>
520 : I<opcode, OOL, IOL, asmstr, itin> {
523 let Pattern = pattern;
525 let Inst{6-10} = CRD;
526 let Inst{11-15} = CRD;
527 let Inst{16-20} = CRD;
528 let Inst{21-30} = xo;
532 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
533 InstrItinClass itin, list<dag> pattern>
534 : I<opcode, OOL, IOL, asmstr, itin> {
539 let Pattern = pattern;
542 let Inst{11-15} = BI;
544 let Inst{19-20} = BH;
545 let Inst{21-30} = xo;
549 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
550 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
551 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
552 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
556 let BI{0-1} = BIBO{0-1};
562 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
563 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
564 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
570 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
572 : I<opcode, OOL, IOL, asmstr, itin> {
578 let Inst{11-13} = BFA;
581 let Inst{21-30} = xo;
586 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
588 : I<opcode, OOL, IOL, asmstr, itin> {
593 let Inst{11} = SPR{4};
594 let Inst{12} = SPR{3};
595 let Inst{13} = SPR{2};
596 let Inst{14} = SPR{1};
597 let Inst{15} = SPR{0};
598 let Inst{16} = SPR{9};
599 let Inst{17} = SPR{8};
600 let Inst{18} = SPR{7};
601 let Inst{19} = SPR{6};
602 let Inst{20} = SPR{5};
603 let Inst{21-30} = xo;
607 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
608 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
609 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
613 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
615 : I<opcode, OOL, IOL, asmstr, itin> {
620 let Inst{21-30} = xo;
624 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
626 : I<opcode, OOL, IOL, asmstr, itin> {
632 let Inst{12-19} = FXM;
634 let Inst{21-30} = xo;
638 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
640 : I<opcode, OOL, IOL, asmstr, itin> {
646 let Inst{12-19} = FXM;
648 let Inst{21-30} = xo;
652 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
654 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
656 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
657 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
658 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
663 // This is probably 1.7.9, but I don't have the reference that uses this
664 // numbering scheme...
665 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
666 string cstr, InstrItinClass itin, list<dag>pattern>
667 : I<opcode, OOL, IOL, asmstr, itin> {
671 bit RC = 0; // set by isDOT
672 let Pattern = pattern;
673 let Constraints = cstr;
678 let Inst{16-20} = RT;
679 let Inst{21-30} = xo;
683 // 1.7.10 XS-Form - SRADI.
684 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
685 InstrItinClass itin, list<dag> pattern>
686 : I<opcode, OOL, IOL, asmstr, itin> {
691 bit RC = 0; // set by isDOT
692 let Pattern = pattern;
696 let Inst{16-20} = SH{4,3,2,1,0};
697 let Inst{21-29} = xo;
698 let Inst{30} = SH{5};
703 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
704 InstrItinClass itin, list<dag> pattern>
705 : I<opcode, OOL, IOL, asmstr, itin> {
710 let Pattern = pattern;
712 bit RC = 0; // set by isDOT
715 let Inst{11-15} = RA;
716 let Inst{16-20} = RB;
718 let Inst{22-30} = xo;
722 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
723 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
724 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
729 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
730 InstrItinClass itin, list<dag> pattern>
731 : I<opcode, OOL, IOL, asmstr, itin> {
737 let Pattern = pattern;
739 bit RC = 0; // set by isDOT
741 let Inst{6-10} = FRT;
742 let Inst{11-15} = FRA;
743 let Inst{16-20} = FRB;
744 let Inst{21-25} = FRC;
745 let Inst{26-30} = xo;
749 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
750 InstrItinClass itin, list<dag> pattern>
751 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
755 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
756 InstrItinClass itin, list<dag> pattern>
757 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
761 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
762 InstrItinClass itin, list<dag> pattern>
763 : I<opcode, OOL, IOL, asmstr, itin> {
767 bits<7> BIBO; // 2 bits of BI and 5 bits of BO (must be 12).
770 let Pattern = pattern;
773 let Inst{11-15} = RA;
774 let Inst{16-20} = RB;
775 let Inst{21-23} = CR;
776 let Inst{24-25} = BIBO{6-5};
777 let Inst{26-30} = xo;
782 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
783 InstrItinClass itin, list<dag> pattern>
784 : I<opcode, OOL, IOL, asmstr, itin> {
791 let Pattern = pattern;
793 bit RC = 0; // set by isDOT
796 let Inst{11-15} = RA;
797 let Inst{16-20} = RB;
798 let Inst{21-25} = MB;
799 let Inst{26-30} = ME;
803 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
804 InstrItinClass itin, list<dag> pattern>
805 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
809 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
810 InstrItinClass itin, list<dag> pattern>
811 : I<opcode, OOL, IOL, asmstr, itin> {
817 let Pattern = pattern;
819 bit RC = 0; // set by isDOT
822 let Inst{11-15} = RA;
823 let Inst{16-20} = SH{4,3,2,1,0};
824 let Inst{21-26} = MBE{4,3,2,1,0,5};
825 let Inst{27-29} = xo;
826 let Inst{30} = SH{5};
834 // VAForm_1 - DACB ordering.
835 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
836 InstrItinClass itin, list<dag> pattern>
837 : I<4, OOL, IOL, asmstr, itin> {
843 let Pattern = pattern;
846 let Inst{11-15} = VA;
847 let Inst{16-20} = VB;
848 let Inst{21-25} = VC;
849 let Inst{26-31} = xo;
852 // VAForm_1a - DABC ordering.
853 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
854 InstrItinClass itin, list<dag> pattern>
855 : I<4, OOL, IOL, asmstr, itin> {
861 let Pattern = pattern;
864 let Inst{11-15} = VA;
865 let Inst{16-20} = VB;
866 let Inst{21-25} = VC;
867 let Inst{26-31} = xo;
870 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
871 InstrItinClass itin, list<dag> pattern>
872 : I<4, OOL, IOL, asmstr, itin> {
878 let Pattern = pattern;
881 let Inst{11-15} = VA;
882 let Inst{16-20} = VB;
884 let Inst{22-25} = SH;
885 let Inst{26-31} = xo;
889 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
890 InstrItinClass itin, list<dag> pattern>
891 : I<4, OOL, IOL, asmstr, itin> {
896 let Pattern = pattern;
899 let Inst{11-15} = VA;
900 let Inst{16-20} = VB;
901 let Inst{21-31} = xo;
904 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
905 InstrItinClass itin, list<dag> pattern>
906 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
912 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
913 InstrItinClass itin, list<dag> pattern>
914 : I<4, OOL, IOL, asmstr, itin> {
918 let Pattern = pattern;
922 let Inst{16-20} = VB;
923 let Inst{21-31} = xo;
926 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
927 InstrItinClass itin, list<dag> pattern>
928 : I<4, OOL, IOL, asmstr, itin> {
932 let Pattern = pattern;
935 let Inst{11-15} = IMM;
937 let Inst{21-31} = xo;
940 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
941 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
942 InstrItinClass itin, list<dag> pattern>
943 : I<4, OOL, IOL, asmstr, itin> {
946 let Pattern = pattern;
951 let Inst{21-31} = xo;
954 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
955 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
956 InstrItinClass itin, list<dag> pattern>
957 : I<4, OOL, IOL, asmstr, itin> {
960 let Pattern = pattern;
964 let Inst{16-20} = VB;
965 let Inst{21-31} = xo;
969 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
970 InstrItinClass itin, list<dag> pattern>
971 : I<4, OOL, IOL, asmstr, itin> {
977 let Pattern = pattern;
980 let Inst{11-15} = VA;
981 let Inst{16-20} = VB;
983 let Inst{22-31} = xo;
986 //===----------------------------------------------------------------------===//
987 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
988 : I<0, OOL, IOL, asmstr, NoItinerary> {
990 let Pattern = pattern;