1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class Format<bits<5> val> {
17 def Pseudo: Format<0>;
20 def Simm16 : Format<3>;
21 def PCRelimm24 : Format<5>;
22 def Imm24 : Format<6>;
24 def PCRelimm14 : Format<8>;
25 def Imm14 : Format<9>;
26 def Imm2 : Format<10>;
28 def Imm3 : Format<12>;
29 def Imm1 : Format<13>;
31 def Imm4 : Format<15>;
32 def Imm8 : Format<16>;
33 def Disimm16 : Format<17>;
34 def Disimm14 : Format<18>;
37 def Imm15 : Format<21>;
39 def Imm6 : Format<23>;
41 //===----------------------------------------------------------------------===//
43 // PowerPC instruction formats
45 class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
53 let Namespace = "PPC";
54 let Inst{0-5} = opcode;
56 let AsmString = asmstr;
60 class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
61 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
70 class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
71 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
78 let Inst{11-13} = CRNum;
79 let Inst{14-15} = BICode;
85 class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode,
86 bit ppc64, bit vmx, dag OL, string asmstr>
87 : BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
93 class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
94 : I<opcode, ppc64, vmx, OL, asmstr> {
104 class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
105 : I<opcode, ppc64, vmx, OL, asmstr> {
115 class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
116 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
118 class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
119 : I<opcode, ppc64, vmx, OL, asmstr> {
128 // Currently we make the use/def reg distinction in ISel, not tablegen
129 class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
130 : DForm_1<opcode, ppc64, vmx, OL, asmstr>;
132 class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
133 : I<opcode, ppc64, vmx, OL, asmstr> {
143 class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
144 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
150 class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
151 : I<opcode, ppc64, vmx, OL, asmstr> {
160 let Inst{11-15} = RA;
164 class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
165 : DForm_5<opcode, ppc64, vmx, OL, asmstr> {
169 class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
170 : DForm_5<opcode, ppc64, vmx, OL, asmstr>;
172 class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
173 : DForm_6<opcode, ppc64, vmx, OL, asmstr> {
177 class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
178 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
181 class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
182 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
186 class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
187 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
192 let Inst{6-10} = RST;
193 let Inst{11-15} = RA;
194 let Inst{16-29} = DS;
195 let Inst{30-31} = xo;
198 class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
199 dag OL, string asmstr>
200 : DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
203 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
204 dag OL, string asmstr>
205 : I<opcode, ppc64, vmx, OL, asmstr> {
210 let Inst{6-10} = RST;
213 let Inst{21-30} = xo;
217 // This is the same as XForm_base_r3xo, but the first two operands are swapped
218 // when code is emitted.
219 class XForm_base_r3xo_swapped
220 <bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
221 dag OL, string asmstr>
222 : I<opcode, ppc64, vmx, OL, asmstr> {
227 let Inst{6-10} = RST;
230 let Inst{21-30} = xo;
235 class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
236 dag OL, string asmstr>
237 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
239 class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
240 dag OL, string asmstr>
241 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
243 class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
244 dag OL, string asmstr>
245 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
247 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
248 dag OL, string asmstr>
249 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
252 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
253 dag OL, string asmstr>
254 : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
258 class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
259 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
268 let Inst{11-15} = RA;
269 let Inst{16-20} = RB;
270 let Inst{21-30} = xo;
274 class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
275 dag OL, string asmstr>
276 : XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
280 class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
281 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
288 let Inst{11-15} = FRA;
289 let Inst{16-20} = FRB;
290 let Inst{21-30} = xo;
294 class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
295 dag OL, string asmstr>
296 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
299 class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
300 dag OL, string asmstr>
301 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
305 class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
306 dag OL, string asmstr>
307 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
311 class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
312 dag OL, string asmstr>
313 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
316 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
317 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
323 let Inst{11-15} = BI;
325 let Inst{19-20} = BH;
326 let Inst{21-30} = xo;
330 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
331 bits<5> bi, bit lk, bit ppc64, bit vmx,
332 dag OL, string asmstr>
333 : XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
339 class XLForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
340 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
346 let Inst{11-13} = BFA;
349 let Inst{21-30} = xo;
354 class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
355 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
360 let Inst{11-20} = SPR;
361 let Inst{21-30} = xo;
365 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
366 bit vmx, dag OL, string asmstr>
367 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
371 class XFXForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
372 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
377 let Inst{21-30} = xo;
381 class XFXForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
382 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
388 let Inst{12-19} = FXM;
390 let Inst{21-30} = xo;
394 class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
395 dag OL, string asmstr>
396 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
398 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
399 bit ppc64, bit vmx, dag OL, string asmstr>
400 : XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
405 class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
406 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
413 let Inst{16-20} = SH{1-5};
414 let Inst{21-29} = xo;
415 let Inst{30} = SH{0};
420 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
421 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
427 let Inst{11-15} = RA;
428 let Inst{16-20} = RB;
430 let Inst{22-30} = xo;
434 class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
435 dag OL, string asmstr>
436 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
437 let Inst{11-15} = RB;
438 let Inst{16-20} = RA;
441 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
442 dag OL, string asmstr>
443 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
448 class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
449 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
455 let Inst{6-10} = FRT;
456 let Inst{11-15} = FRA;
457 let Inst{16-20} = FRB;
458 let Inst{21-25} = FRC;
459 let Inst{26-30} = xo;
463 class AForm_2<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
465 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
469 class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
471 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
476 class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
477 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
485 let Inst{11-15} = RA;
486 let Inst{16-20} = RB;
487 let Inst{21-25} = MB;
488 let Inst{26-30} = ME;
492 class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
493 dag OL, string asmstr>
494 : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> {
498 class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
499 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
506 let Inst{11-15} = RA;
507 let Inst{16-20} = SH{1-5};
508 let Inst{21-26} = MBE;
509 let Inst{27-29} = xo;
510 let Inst{30} = SH{0};
514 //===----------------------------------------------------------------------===//
516 class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {