1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 // DOT - This is a marker that should be added to instructions that set the
16 list<Register> Defs = [CR0];
21 class Format<bits<5> val> {
25 def Pseudo: Format<0>;
28 def Simm16 : Format<3>;
29 def PCRelimm24 : Format<5>;
30 def Imm24 : Format<6>;
32 def PCRelimm14 : Format<8>;
33 def Imm14 : Format<9>;
34 def Imm2 : Format<10>;
36 def Imm3 : Format<12>;
37 def Imm1 : Format<13>;
39 def Imm4 : Format<15>;
40 def Imm8 : Format<16>;
41 def Disimm16 : Format<17>;
42 def Disimm14 : Format<18>;
45 def Imm15 : Format<21>;
47 def Imm6 : Format<23>;
49 //===----------------------------------------------------------------------===//
51 // PowerPC instruction formats
53 class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
61 let Namespace = "PPC";
62 let Inst{0-5} = opcode;
64 let AsmString = asmstr;
68 class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
69 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
78 class BForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
79 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
86 let Inst{11-13} = CRNum;
87 let Inst{14-15} = BICode;
93 class BForm_ext<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode,
94 bit ppc64, bit vmx, dag OL, string asmstr>
95 : BForm<opcode, aa, lk, ppc64, vmx, OL, asmstr> {
101 class DForm_base<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
102 : I<opcode, ppc64, vmx, OL, asmstr> {
112 class DForm_1<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
113 : I<opcode, ppc64, vmx, OL, asmstr> {
123 class DForm_2<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
124 : DForm_base<opcode, ppc64, vmx, OL, asmstr>;
126 class DForm_2_r0<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
127 : I<opcode, ppc64, vmx, OL, asmstr> {
136 // Currently we make the use/def reg distinction in ISel, not tablegen
137 class DForm_3<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
138 : DForm_1<opcode, ppc64, vmx, OL, asmstr>;
140 class DForm_4<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
141 : I<opcode, ppc64, vmx, OL, asmstr> {
151 class DForm_4_zero<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
152 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
158 class DForm_5<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
159 : I<opcode, ppc64, vmx, OL, asmstr> {
168 let Inst{11-15} = RA;
172 class DForm_5_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
173 : DForm_5<opcode, ppc64, vmx, OL, asmstr> {
177 class DForm_6<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
178 : DForm_5<opcode, ppc64, vmx, OL, asmstr>;
180 class DForm_6_ext<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
181 : DForm_6<opcode, ppc64, vmx, OL, asmstr> {
185 class DForm_8<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
186 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
189 class DForm_9<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
190 : DForm_1<opcode, ppc64, vmx, OL, asmstr> {
194 class DSForm_1<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
195 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
200 let Inst{6-10} = RST;
201 let Inst{11-15} = RA;
202 let Inst{16-29} = DS;
203 let Inst{30-31} = xo;
206 class DSForm_2<bits<6> opcode, bits<2> xo, bit ppc64, bit vmx,
207 dag OL, string asmstr>
208 : DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
211 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
212 dag OL, string asmstr>
213 : I<opcode, ppc64, vmx, OL, asmstr> {
218 let Inst{6-10} = RST;
221 let Inst{21-30} = xo;
225 // This is the same as XForm_base_r3xo, but the first two operands are swapped
226 // when code is emitted.
227 class XForm_base_r3xo_swapped
228 <bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
229 dag OL, string asmstr>
230 : I<opcode, ppc64, vmx, OL, asmstr> {
236 let Inst{6-10} = RST;
239 let Inst{21-30} = xo;
244 class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
245 dag OL, string asmstr>
246 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
248 class XForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
249 dag OL, string asmstr>
250 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
255 class XForm_6<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
256 dag OL, string asmstr>
257 : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
260 class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
261 dag OL, string asmstr>
262 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
264 class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
265 dag OL, string asmstr>
266 : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
270 class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
271 dag OL, string asmstr>
272 : XForm_base_r3xo_swapped<opcode, xo, ppc64, vmx, OL, asmstr> {
277 class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
278 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
287 let Inst{11-15} = RA;
288 let Inst{16-20} = RB;
289 let Inst{21-30} = xo;
293 class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
294 dag OL, string asmstr>
295 : XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
299 class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
300 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
307 let Inst{11-15} = FRA;
308 let Inst{16-20} = FRB;
309 let Inst{21-30} = xo;
313 class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
314 dag OL, string asmstr>
315 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
318 class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
319 dag OL, string asmstr>
320 : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
324 class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
325 dag OL, string asmstr>
326 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
330 class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
331 dag OL, string asmstr>
332 : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
335 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
336 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
342 let Inst{11-15} = BI;
344 let Inst{19-20} = BH;
345 let Inst{21-30} = xo;
349 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
350 bits<5> bi, bit lk, bit ppc64, bit vmx,
351 dag OL, string asmstr>
352 : XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
359 class XFXForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
360 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
365 let Inst{11-20} = SPR;
366 let Inst{21-30} = xo;
370 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, bit ppc64,
371 bit vmx, dag OL, string asmstr>
372 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr> {
376 class XFXForm_7<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
377 dag OL, string asmstr>
378 : XFXForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
380 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
381 bit ppc64, bit vmx, dag OL, string asmstr>
382 : XFXForm_7<opcode, xo, ppc64, vmx, OL, asmstr> {
387 class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, bit ppc64, bit vmx,
388 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
395 let Inst{16-20} = SH{1-5};
396 let Inst{21-29} = xo;
397 let Inst{30} = SH{0};
402 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
403 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
409 let Inst{11-15} = RA;
410 let Inst{16-20} = RB;
412 let Inst{22-30} = xo;
416 class XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
417 dag OL, string asmstr>
418 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
419 let Inst{11-15} = RB;
420 let Inst{16-20} = RA;
423 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, bit rc, bit ppc64, bit vmx,
424 dag OL, string asmstr>
425 : XOForm_1<opcode, xo, oe, rc, ppc64, vmx, OL, asmstr> {
430 class AForm_1<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx,
431 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
437 let Inst{6-10} = FRT;
438 let Inst{11-15} = FRA;
439 let Inst{16-20} = FRB;
440 let Inst{21-25} = FRC;
441 let Inst{26-30} = xo;
445 class AForm_2<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
447 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
451 class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL,
453 : AForm_1<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
458 class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx,
459 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
467 let Inst{11-15} = RA;
468 let Inst{16-20} = RB;
469 let Inst{21-25} = MB;
470 let Inst{26-30} = ME;
474 class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx,
475 dag OL, string asmstr>
476 : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> {
480 class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
481 dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
488 let Inst{11-15} = RA;
489 let Inst{16-20} = SH{1-5};
490 let Inst{21-26} = MBE;
491 let Inst{27-29} = xo;
492 let Inst{30} = SH{0};
496 //===----------------------------------------------------------------------===//
498 class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {