1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
148 class BForm_3<bits<6> opcode, bit aa, bit lk,
149 dag OOL, dag IOL, string asmstr>
150 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
156 let Inst{11-15} = BI;
157 let Inst{16-29} = BD;
163 class SCForm<bits<6> opcode, bits<1> xo,
164 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
166 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
171 let Inst{20-26} = LEV;
176 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
190 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
191 InstrItinClass itin, list<dag> pattern>
192 : I<opcode, OOL, IOL, asmstr, itin> {
196 let Pattern = pattern;
199 let Inst{11-15} = Addr{20-16}; // Base Reg
200 let Inst{16-31} = Addr{15-0}; // Displacement
203 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
204 InstrItinClass itin, list<dag> pattern>
205 : I<opcode, OOL, IOL, asmstr, itin> {
210 let Pattern = pattern;
218 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
219 InstrItinClass itin, list<dag> pattern>
220 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
222 // Even though ADDICo does not really have an RC bit, provide
223 // the declaration of one here so that isDOT has something to set.
227 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : I<opcode, OOL, IOL, asmstr, itin> {
233 let Pattern = pattern;
240 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
241 InstrItinClass itin, list<dag> pattern>
242 : I<opcode, OOL, IOL, asmstr, itin> {
247 let Pattern = pattern;
254 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255 InstrItinClass itin, list<dag> pattern>
256 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
261 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
262 string asmstr, InstrItinClass itin,
264 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
270 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
271 dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
277 let Pattern = pattern;
285 let Inst{43-47} = Addr{20-16}; // Base Reg
286 let Inst{48-63} = Addr{15-0}; // Displacement
289 // This is used to emit BL8+NOP.
290 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
291 dag OOL, dag IOL, string asmstr,
292 InstrItinClass itin, list<dag> pattern>
293 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
294 OOL, IOL, asmstr, itin, pattern> {
299 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
301 : I<opcode, OOL, IOL, asmstr, itin> {
310 let Inst{11-15} = RA;
314 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
316 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
320 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
322 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
324 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
326 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
332 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
333 InstrItinClass itin, list<dag> pattern>
334 : I<opcode, OOL, IOL, asmstr, itin> {
338 let Pattern = pattern;
340 let Inst{6-10} = RST;
341 let Inst{11-15} = DS_RA{18-14}; // Register #
342 let Inst{16-29} = DS_RA{13-0}; // Displacement.
343 let Inst{30-31} = xo;
346 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
347 InstrItinClass itin, list<dag> pattern>
348 : I<opcode, OOL, IOL, asmstr, itin> {
353 let Pattern = pattern;
355 let Inst{6-10} = RST;
356 let Inst{11-15} = RA;
357 let Inst{16-29} = DS;
358 let Inst{30-31} = xo;
362 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
363 InstrItinClass itin, list<dag> pattern>
364 : I<opcode, OOL, IOL, asmstr, itin> {
369 let Pattern = pattern;
371 bit RC = 0; // set by isDOT
373 let Inst{6-10} = RST;
376 let Inst{21-30} = xo;
380 // This is the same as XForm_base_r3xo, but the first two operands are swapped
381 // when code is emitted.
382 class XForm_base_r3xo_swapped
383 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
385 : I<opcode, OOL, IOL, asmstr, itin> {
390 bit RC = 0; // set by isDOT
392 let Inst{6-10} = RST;
395 let Inst{21-30} = xo;
400 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
401 InstrItinClass itin, list<dag> pattern>
402 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
404 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
405 InstrItinClass itin, list<dag> pattern>
406 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
410 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
411 InstrItinClass itin, list<dag> pattern>
412 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
417 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
418 InstrItinClass itin, list<dag> pattern>
419 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
420 let Pattern = pattern;
423 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
424 InstrItinClass itin, list<dag> pattern>
425 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
427 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
428 InstrItinClass itin, list<dag> pattern>
429 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
430 let Pattern = pattern;
433 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
434 InstrItinClass itin, list<dag> pattern>
435 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
437 let Pattern = pattern;
440 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
442 : I<opcode, OOL, IOL, asmstr, itin> {
451 let Inst{11-15} = RA;
452 let Inst{16-20} = RB;
453 let Inst{21-30} = xo;
457 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
459 : I<opcode, OOL, IOL, asmstr, itin> {
465 let Inst{21-30} = xo;
468 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
470 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
474 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
476 : I<opcode, OOL, IOL, asmstr, itin> {
483 let Inst{11-15} = FRA;
484 let Inst{16-20} = FRB;
485 let Inst{21-30} = xo;
489 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
490 InstrItinClass itin, list<dag> pattern>
491 : I<opcode, OOL, IOL, asmstr, itin> {
492 let Pattern = pattern;
496 let Inst{21-30} = xo;
500 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
501 string asmstr, InstrItinClass itin, list<dag> pattern>
502 : I<opcode, OOL, IOL, asmstr, itin> {
505 let Pattern = pattern;
510 let Inst{21-30} = xo;
514 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
515 string asmstr, InstrItinClass itin, list<dag> pattern>
516 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
520 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
521 InstrItinClass itin, list<dag> pattern>
522 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
525 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
526 InstrItinClass itin, list<dag> pattern>
527 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
531 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
532 InstrItinClass itin, list<dag> pattern>
533 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
536 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
537 // numbers presumably relates to some document, but I haven't found it.
538 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
539 InstrItinClass itin, list<dag> pattern>
540 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
541 let Pattern = pattern;
543 bit RC = 0; // set by isDOT
545 let Inst{6-10} = RST;
547 let Inst{21-30} = xo;
550 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
551 InstrItinClass itin, list<dag> pattern>
552 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
553 let Pattern = pattern;
556 bit RC = 0; // set by isDOT
560 let Inst{21-30} = xo;
564 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
565 InstrItinClass itin, list<dag> pattern>
566 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
572 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
573 InstrItinClass itin, list<dag> pattern>
574 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
579 // DCB_Form - Form X instruction, used for dcb* instructions.
580 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
581 InstrItinClass itin, list<dag> pattern>
582 : I<31, OOL, IOL, asmstr, itin> {
586 let Pattern = pattern;
588 let Inst{6-10} = immfield;
591 let Inst{21-30} = xo;
596 // DSS_Form - Form X instruction, used for altivec dss* instructions.
597 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
598 InstrItinClass itin, list<dag> pattern>
599 : I<31, OOL, IOL, asmstr, itin> {
605 let Pattern = pattern;
609 let Inst{9-10} = STRM;
612 let Inst{21-30} = xo;
617 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
618 InstrItinClass itin, list<dag> pattern>
619 : I<opcode, OOL, IOL, asmstr, itin> {
624 let Pattern = pattern;
626 let Inst{6-10} = CRD;
627 let Inst{11-15} = CRA;
628 let Inst{16-20} = CRB;
629 let Inst{21-30} = xo;
633 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
634 InstrItinClass itin, list<dag> pattern>
635 : I<opcode, OOL, IOL, asmstr, itin> {
638 let Pattern = pattern;
640 let Inst{6-10} = CRD;
641 let Inst{11-15} = CRD;
642 let Inst{16-20} = CRD;
643 let Inst{21-30} = xo;
647 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
648 InstrItinClass itin, list<dag> pattern>
649 : I<opcode, OOL, IOL, asmstr, itin> {
654 let Pattern = pattern;
657 let Inst{11-15} = BI;
659 let Inst{19-20} = BH;
660 let Inst{21-30} = xo;
664 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
665 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
666 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
667 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
671 let BI{0-1} = BIBO{5-6};
672 let BI{2-4} = CR{0-2};
677 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
678 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
679 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
685 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
687 : I<opcode, OOL, IOL, asmstr, itin> {
693 let Inst{11-13} = BFA;
696 let Inst{21-30} = xo;
701 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
703 : I<opcode, OOL, IOL, asmstr, itin> {
708 let Inst{11} = SPR{4};
709 let Inst{12} = SPR{3};
710 let Inst{13} = SPR{2};
711 let Inst{14} = SPR{1};
712 let Inst{15} = SPR{0};
713 let Inst{16} = SPR{9};
714 let Inst{17} = SPR{8};
715 let Inst{18} = SPR{7};
716 let Inst{19} = SPR{6};
717 let Inst{20} = SPR{5};
718 let Inst{21-30} = xo;
722 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
723 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
724 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
728 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
730 : I<opcode, OOL, IOL, asmstr, itin> {
735 let Inst{21-30} = xo;
739 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
741 : I<opcode, OOL, IOL, asmstr, itin> {
747 let Inst{12-19} = FXM;
749 let Inst{21-30} = xo;
753 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
755 : I<opcode, OOL, IOL, asmstr, itin> {
761 let Inst{12-19} = FXM;
763 let Inst{21-30} = xo;
767 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
769 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
771 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
772 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
773 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
778 // This is probably 1.7.9, but I don't have the reference that uses this
779 // numbering scheme...
780 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
781 InstrItinClass itin, list<dag>pattern>
782 : I<opcode, OOL, IOL, asmstr, itin> {
786 bit RC = 0; // set by isDOT
787 let Pattern = pattern;
792 let Inst{16-20} = rT;
793 let Inst{21-30} = xo;
797 // 1.7.10 XS-Form - SRADI.
798 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
799 InstrItinClass itin, list<dag> pattern>
800 : I<opcode, OOL, IOL, asmstr, itin> {
805 bit RC = 0; // set by isDOT
806 let Pattern = pattern;
810 let Inst{16-20} = SH{4,3,2,1,0};
811 let Inst{21-29} = xo;
812 let Inst{30} = SH{5};
817 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
818 InstrItinClass itin, list<dag> pattern>
819 : I<opcode, OOL, IOL, asmstr, itin> {
824 let Pattern = pattern;
826 bit RC = 0; // set by isDOT
829 let Inst{11-15} = RA;
830 let Inst{16-20} = RB;
832 let Inst{22-30} = xo;
836 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
837 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
838 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
843 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
844 InstrItinClass itin, list<dag> pattern>
845 : I<opcode, OOL, IOL, asmstr, itin> {
851 let Pattern = pattern;
853 bit RC = 0; // set by isDOT
855 let Inst{6-10} = FRT;
856 let Inst{11-15} = FRA;
857 let Inst{16-20} = FRB;
858 let Inst{21-25} = FRC;
859 let Inst{26-30} = xo;
863 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
864 InstrItinClass itin, list<dag> pattern>
865 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
869 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
870 InstrItinClass itin, list<dag> pattern>
871 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
875 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
876 InstrItinClass itin, list<dag> pattern>
877 : I<opcode, OOL, IOL, asmstr, itin> {
883 let Pattern = pattern;
886 let Inst{11-15} = RA;
887 let Inst{16-20} = RB;
888 let Inst{21-25} = COND;
889 let Inst{26-30} = xo;
894 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
895 InstrItinClass itin, list<dag> pattern>
896 : I<opcode, OOL, IOL, asmstr, itin> {
903 let Pattern = pattern;
905 bit RC = 0; // set by isDOT
908 let Inst{11-15} = RA;
909 let Inst{16-20} = RB;
910 let Inst{21-25} = MB;
911 let Inst{26-30} = ME;
915 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
916 InstrItinClass itin, list<dag> pattern>
917 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
921 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
922 InstrItinClass itin, list<dag> pattern>
923 : I<opcode, OOL, IOL, asmstr, itin> {
929 let Pattern = pattern;
931 bit RC = 0; // set by isDOT
934 let Inst{11-15} = RA;
935 let Inst{16-20} = SH{4,3,2,1,0};
936 let Inst{21-26} = MBE{4,3,2,1,0,5};
937 let Inst{27-29} = xo;
938 let Inst{30} = SH{5};
942 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
943 InstrItinClass itin, list<dag> pattern>
944 : I<opcode, OOL, IOL, asmstr, itin> {
950 let Pattern = pattern;
952 bit RC = 0; // set by isDOT
955 let Inst{11-15} = RA;
956 let Inst{16-20} = RB;
957 let Inst{21-26} = MBE{4,3,2,1,0,5};
958 let Inst{27-30} = xo;
965 // VAForm_1 - DACB ordering.
966 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
967 InstrItinClass itin, list<dag> pattern>
968 : I<4, OOL, IOL, asmstr, itin> {
974 let Pattern = pattern;
977 let Inst{11-15} = VA;
978 let Inst{16-20} = VB;
979 let Inst{21-25} = VC;
980 let Inst{26-31} = xo;
983 // VAForm_1a - DABC ordering.
984 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
985 InstrItinClass itin, list<dag> pattern>
986 : I<4, OOL, IOL, asmstr, itin> {
992 let Pattern = pattern;
995 let Inst{11-15} = VA;
996 let Inst{16-20} = VB;
997 let Inst{21-25} = VC;
998 let Inst{26-31} = xo;
1001 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1002 InstrItinClass itin, list<dag> pattern>
1003 : I<4, OOL, IOL, asmstr, itin> {
1009 let Pattern = pattern;
1011 let Inst{6-10} = VD;
1012 let Inst{11-15} = VA;
1013 let Inst{16-20} = VB;
1015 let Inst{22-25} = SH;
1016 let Inst{26-31} = xo;
1020 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1021 InstrItinClass itin, list<dag> pattern>
1022 : I<4, OOL, IOL, asmstr, itin> {
1027 let Pattern = pattern;
1029 let Inst{6-10} = VD;
1030 let Inst{11-15} = VA;
1031 let Inst{16-20} = VB;
1032 let Inst{21-31} = xo;
1035 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1036 InstrItinClass itin, list<dag> pattern>
1037 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1043 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1044 InstrItinClass itin, list<dag> pattern>
1045 : I<4, OOL, IOL, asmstr, itin> {
1049 let Pattern = pattern;
1051 let Inst{6-10} = VD;
1052 let Inst{11-15} = 0;
1053 let Inst{16-20} = VB;
1054 let Inst{21-31} = xo;
1057 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1058 InstrItinClass itin, list<dag> pattern>
1059 : I<4, OOL, IOL, asmstr, itin> {
1063 let Pattern = pattern;
1065 let Inst{6-10} = VD;
1066 let Inst{11-15} = IMM;
1067 let Inst{16-20} = 0;
1068 let Inst{21-31} = xo;
1071 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1072 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1073 InstrItinClass itin, list<dag> pattern>
1074 : I<4, OOL, IOL, asmstr, itin> {
1077 let Pattern = pattern;
1079 let Inst{6-10} = VD;
1080 let Inst{11-15} = 0;
1081 let Inst{16-20} = 0;
1082 let Inst{21-31} = xo;
1085 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1086 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin, list<dag> pattern>
1088 : I<4, OOL, IOL, asmstr, itin> {
1091 let Pattern = pattern;
1094 let Inst{11-15} = 0;
1095 let Inst{16-20} = VB;
1096 let Inst{21-31} = xo;
1100 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1101 InstrItinClass itin, list<dag> pattern>
1102 : I<4, OOL, IOL, asmstr, itin> {
1108 let Pattern = pattern;
1110 let Inst{6-10} = VD;
1111 let Inst{11-15} = VA;
1112 let Inst{16-20} = VB;
1114 let Inst{22-31} = xo;
1117 //===----------------------------------------------------------------------===//
1118 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1119 : I<0, OOL, IOL, asmstr, NoItinerary> {
1120 let isCodeGenOnly = 1;
1122 let Pattern = pattern;