1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
148 class BForm_3<bits<6> opcode, bit aa, bit lk,
149 dag OOL, dag IOL, string asmstr>
150 : I<opcode, OOL, IOL, asmstr, BrB> {
156 let Inst{11-15} = BI;
157 let Inst{16-29} = BD;
163 class SCForm<bits<6> opcode, bits<1> xo,
164 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
166 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
171 let Inst{20-26} = LEV;
176 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
190 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
191 InstrItinClass itin, list<dag> pattern>
192 : I<opcode, OOL, IOL, asmstr, itin> {
196 let Pattern = pattern;
199 let Inst{11-15} = Addr{20-16}; // Base Reg
200 let Inst{16-31} = Addr{15-0}; // Displacement
203 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
204 InstrItinClass itin, list<dag> pattern>
205 : I<opcode, OOL, IOL, asmstr, itin> {
210 let Pattern = pattern;
218 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
219 InstrItinClass itin, list<dag> pattern>
220 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
222 // Even though ADDICo does not really have an RC bit, provide
223 // the declaration of one here so that isDOT has something to set.
227 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : I<opcode, OOL, IOL, asmstr, itin> {
233 let Pattern = pattern;
240 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
241 InstrItinClass itin, list<dag> pattern>
242 : I<opcode, OOL, IOL, asmstr, itin> {
247 let Pattern = pattern;
254 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255 InstrItinClass itin, list<dag> pattern>
256 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
261 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
262 dag OOL, dag IOL, string asmstr,
263 InstrItinClass itin, list<dag> pattern>
264 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
268 let Pattern = pattern;
276 let Inst{43-47} = Addr{20-16}; // Base Reg
277 let Inst{48-63} = Addr{15-0}; // Displacement
280 // This is used to emit BL8+NOP.
281 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
282 dag OOL, dag IOL, string asmstr,
283 InstrItinClass itin, list<dag> pattern>
284 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
285 OOL, IOL, asmstr, itin, pattern> {
290 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
292 : I<opcode, OOL, IOL, asmstr, itin> {
301 let Inst{11-15} = RA;
305 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
307 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
311 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
313 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
315 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
317 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
323 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
324 InstrItinClass itin, list<dag> pattern>
325 : I<opcode, OOL, IOL, asmstr, itin> {
329 let Pattern = pattern;
331 let Inst{6-10} = RST;
332 let Inst{11-15} = DS_RA{18-14}; // Register #
333 let Inst{16-29} = DS_RA{13-0}; // Displacement.
334 let Inst{30-31} = xo;
337 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
338 InstrItinClass itin, list<dag> pattern>
339 : I<opcode, OOL, IOL, asmstr, itin> {
344 let Pattern = pattern;
346 let Inst{6-10} = RST;
347 let Inst{11-15} = RA;
348 let Inst{16-29} = DS;
349 let Inst{30-31} = xo;
353 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
354 InstrItinClass itin, list<dag> pattern>
355 : I<opcode, OOL, IOL, asmstr, itin> {
360 let Pattern = pattern;
362 bit RC = 0; // set by isDOT
364 let Inst{6-10} = RST;
367 let Inst{21-30} = xo;
371 // This is the same as XForm_base_r3xo, but the first two operands are swapped
372 // when code is emitted.
373 class XForm_base_r3xo_swapped
374 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
376 : I<opcode, OOL, IOL, asmstr, itin> {
381 bit RC = 0; // set by isDOT
383 let Inst{6-10} = RST;
386 let Inst{21-30} = xo;
391 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
392 InstrItinClass itin, list<dag> pattern>
393 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
395 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
396 InstrItinClass itin, list<dag> pattern>
397 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
401 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
402 InstrItinClass itin, list<dag> pattern>
403 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
404 let Pattern = pattern;
407 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
411 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
412 InstrItinClass itin, list<dag> pattern>
413 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
414 let Pattern = pattern;
417 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
418 InstrItinClass itin, list<dag> pattern>
419 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
421 let Pattern = pattern;
424 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 : I<opcode, OOL, IOL, asmstr, itin> {
435 let Inst{11-15} = RA;
436 let Inst{16-20} = RB;
437 let Inst{21-30} = xo;
441 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
443 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
447 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
449 : I<opcode, OOL, IOL, asmstr, itin> {
456 let Inst{11-15} = FRA;
457 let Inst{16-20} = FRB;
458 let Inst{21-30} = xo;
462 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : I<opcode, OOL, IOL, asmstr, itin> {
465 let Pattern = pattern;
469 let Inst{21-30} = xo;
473 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
474 string asmstr, InstrItinClass itin, list<dag> pattern>
475 : I<opcode, OOL, IOL, asmstr, itin> {
478 let Pattern = pattern;
483 let Inst{21-30} = xo;
487 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
488 InstrItinClass itin, list<dag> pattern>
489 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
492 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
493 InstrItinClass itin, list<dag> pattern>
494 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
498 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
499 InstrItinClass itin, list<dag> pattern>
500 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
503 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
504 // numbers presumably relates to some document, but I haven't found it.
505 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
506 InstrItinClass itin, list<dag> pattern>
507 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
508 let Pattern = pattern;
510 bit RC = 0; // set by isDOT
512 let Inst{6-10} = RST;
514 let Inst{21-30} = xo;
517 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
518 InstrItinClass itin, list<dag> pattern>
519 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
520 let Pattern = pattern;
523 bit RC = 0; // set by isDOT
527 let Inst{21-30} = xo;
531 // DCB_Form - Form X instruction, used for dcb* instructions.
532 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
533 InstrItinClass itin, list<dag> pattern>
534 : I<31, OOL, IOL, asmstr, itin> {
538 let Pattern = pattern;
540 let Inst{6-10} = immfield;
543 let Inst{21-30} = xo;
548 // DSS_Form - Form X instruction, used for altivec dss* instructions.
549 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
550 InstrItinClass itin, list<dag> pattern>
551 : I<31, OOL, IOL, asmstr, itin> {
557 let Pattern = pattern;
561 let Inst{9-10} = STRM;
564 let Inst{21-30} = xo;
569 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
570 InstrItinClass itin, list<dag> pattern>
571 : I<opcode, OOL, IOL, asmstr, itin> {
576 let Pattern = pattern;
578 let Inst{6-10} = CRD;
579 let Inst{11-15} = CRA;
580 let Inst{16-20} = CRB;
581 let Inst{21-30} = xo;
585 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
586 InstrItinClass itin, list<dag> pattern>
587 : I<opcode, OOL, IOL, asmstr, itin> {
590 let Pattern = pattern;
592 let Inst{6-10} = CRD;
593 let Inst{11-15} = CRD;
594 let Inst{16-20} = CRD;
595 let Inst{21-30} = xo;
599 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
600 InstrItinClass itin, list<dag> pattern>
601 : I<opcode, OOL, IOL, asmstr, itin> {
606 let Pattern = pattern;
609 let Inst{11-15} = BI;
611 let Inst{19-20} = BH;
612 let Inst{21-30} = xo;
616 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
617 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
618 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
619 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
623 let BI{0-1} = BIBO{5-6};
624 let BI{2-4} = CR{0-2};
629 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
630 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
631 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
637 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
639 : I<opcode, OOL, IOL, asmstr, itin> {
645 let Inst{11-13} = BFA;
648 let Inst{21-30} = xo;
653 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
655 : I<opcode, OOL, IOL, asmstr, itin> {
660 let Inst{11} = SPR{4};
661 let Inst{12} = SPR{3};
662 let Inst{13} = SPR{2};
663 let Inst{14} = SPR{1};
664 let Inst{15} = SPR{0};
665 let Inst{16} = SPR{9};
666 let Inst{17} = SPR{8};
667 let Inst{18} = SPR{7};
668 let Inst{19} = SPR{6};
669 let Inst{20} = SPR{5};
670 let Inst{21-30} = xo;
674 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
675 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
676 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
680 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
682 : I<opcode, OOL, IOL, asmstr, itin> {
687 let Inst{21-30} = xo;
691 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
693 : I<opcode, OOL, IOL, asmstr, itin> {
699 let Inst{12-19} = FXM;
701 let Inst{21-30} = xo;
705 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
707 : I<opcode, OOL, IOL, asmstr, itin> {
713 let Inst{12-19} = FXM;
715 let Inst{21-30} = xo;
719 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
721 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
723 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
724 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
725 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
730 // This is probably 1.7.9, but I don't have the reference that uses this
731 // numbering scheme...
732 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
733 InstrItinClass itin, list<dag>pattern>
734 : I<opcode, OOL, IOL, asmstr, itin> {
738 bit RC = 0; // set by isDOT
739 let Pattern = pattern;
744 let Inst{16-20} = rT;
745 let Inst{21-30} = xo;
749 // 1.7.10 XS-Form - SRADI.
750 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
751 InstrItinClass itin, list<dag> pattern>
752 : I<opcode, OOL, IOL, asmstr, itin> {
757 bit RC = 0; // set by isDOT
758 let Pattern = pattern;
762 let Inst{16-20} = SH{4,3,2,1,0};
763 let Inst{21-29} = xo;
764 let Inst{30} = SH{5};
769 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
770 InstrItinClass itin, list<dag> pattern>
771 : I<opcode, OOL, IOL, asmstr, itin> {
776 let Pattern = pattern;
778 bit RC = 0; // set by isDOT
781 let Inst{11-15} = RA;
782 let Inst{16-20} = RB;
784 let Inst{22-30} = xo;
788 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
789 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
790 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
795 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
796 InstrItinClass itin, list<dag> pattern>
797 : I<opcode, OOL, IOL, asmstr, itin> {
803 let Pattern = pattern;
805 bit RC = 0; // set by isDOT
807 let Inst{6-10} = FRT;
808 let Inst{11-15} = FRA;
809 let Inst{16-20} = FRB;
810 let Inst{21-25} = FRC;
811 let Inst{26-30} = xo;
815 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
816 InstrItinClass itin, list<dag> pattern>
817 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
821 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
822 InstrItinClass itin, list<dag> pattern>
823 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
827 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
828 InstrItinClass itin, list<dag> pattern>
829 : I<opcode, OOL, IOL, asmstr, itin> {
835 let Pattern = pattern;
838 let Inst{11-15} = RA;
839 let Inst{16-20} = RB;
840 let Inst{21-25} = COND;
841 let Inst{26-30} = xo;
846 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
847 InstrItinClass itin, list<dag> pattern>
848 : I<opcode, OOL, IOL, asmstr, itin> {
855 let Pattern = pattern;
857 bit RC = 0; // set by isDOT
860 let Inst{11-15} = RA;
861 let Inst{16-20} = RB;
862 let Inst{21-25} = MB;
863 let Inst{26-30} = ME;
867 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
868 InstrItinClass itin, list<dag> pattern>
869 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
873 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
874 InstrItinClass itin, list<dag> pattern>
875 : I<opcode, OOL, IOL, asmstr, itin> {
881 let Pattern = pattern;
883 bit RC = 0; // set by isDOT
886 let Inst{11-15} = RA;
887 let Inst{16-20} = SH{4,3,2,1,0};
888 let Inst{21-26} = MBE{4,3,2,1,0,5};
889 let Inst{27-29} = xo;
890 let Inst{30} = SH{5};
894 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
895 InstrItinClass itin, list<dag> pattern>
896 : I<opcode, OOL, IOL, asmstr, itin> {
902 let Pattern = pattern;
904 bit RC = 0; // set by isDOT
907 let Inst{11-15} = RA;
908 let Inst{16-20} = RB;
909 let Inst{21-26} = MBE{4,3,2,1,0,5};
910 let Inst{27-30} = xo;
917 // VAForm_1 - DACB ordering.
918 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
919 InstrItinClass itin, list<dag> pattern>
920 : I<4, OOL, IOL, asmstr, itin> {
926 let Pattern = pattern;
929 let Inst{11-15} = VA;
930 let Inst{16-20} = VB;
931 let Inst{21-25} = VC;
932 let Inst{26-31} = xo;
935 // VAForm_1a - DABC ordering.
936 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
937 InstrItinClass itin, list<dag> pattern>
938 : I<4, OOL, IOL, asmstr, itin> {
944 let Pattern = pattern;
947 let Inst{11-15} = VA;
948 let Inst{16-20} = VB;
949 let Inst{21-25} = VC;
950 let Inst{26-31} = xo;
953 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
954 InstrItinClass itin, list<dag> pattern>
955 : I<4, OOL, IOL, asmstr, itin> {
961 let Pattern = pattern;
964 let Inst{11-15} = VA;
965 let Inst{16-20} = VB;
967 let Inst{22-25} = SH;
968 let Inst{26-31} = xo;
972 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
973 InstrItinClass itin, list<dag> pattern>
974 : I<4, OOL, IOL, asmstr, itin> {
979 let Pattern = pattern;
982 let Inst{11-15} = VA;
983 let Inst{16-20} = VB;
984 let Inst{21-31} = xo;
987 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
988 InstrItinClass itin, list<dag> pattern>
989 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
995 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
996 InstrItinClass itin, list<dag> pattern>
997 : I<4, OOL, IOL, asmstr, itin> {
1001 let Pattern = pattern;
1003 let Inst{6-10} = VD;
1004 let Inst{11-15} = 0;
1005 let Inst{16-20} = VB;
1006 let Inst{21-31} = xo;
1009 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1010 InstrItinClass itin, list<dag> pattern>
1011 : I<4, OOL, IOL, asmstr, itin> {
1015 let Pattern = pattern;
1017 let Inst{6-10} = VD;
1018 let Inst{11-15} = IMM;
1019 let Inst{16-20} = 0;
1020 let Inst{21-31} = xo;
1023 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1024 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1025 InstrItinClass itin, list<dag> pattern>
1026 : I<4, OOL, IOL, asmstr, itin> {
1029 let Pattern = pattern;
1031 let Inst{6-10} = VD;
1032 let Inst{11-15} = 0;
1033 let Inst{16-20} = 0;
1034 let Inst{21-31} = xo;
1037 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1038 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1039 InstrItinClass itin, list<dag> pattern>
1040 : I<4, OOL, IOL, asmstr, itin> {
1043 let Pattern = pattern;
1046 let Inst{11-15} = 0;
1047 let Inst{16-20} = VB;
1048 let Inst{21-31} = xo;
1052 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1053 InstrItinClass itin, list<dag> pattern>
1054 : I<4, OOL, IOL, asmstr, itin> {
1060 let Pattern = pattern;
1062 let Inst{6-10} = VD;
1063 let Inst{11-15} = VA;
1064 let Inst{16-20} = VB;
1066 let Inst{22-31} = xo;
1069 //===----------------------------------------------------------------------===//
1070 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1071 : I<0, OOL, IOL, asmstr, NoItinerary> {
1072 let isCodeGenOnly = 1;
1074 let Pattern = pattern;