1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
17 field bits<32> SoftFail = 0;
20 bit PPC64 = 0; // Default value, override with isPPC64
22 let Namespace = "PPC";
23 let Inst{0-5} = opcode;
24 let OutOperandList = OOL;
25 let InOperandList = IOL;
26 let AsmString = asmstr;
29 bits<1> PPC970_First = 0;
30 bits<1> PPC970_Single = 0;
31 bits<1> PPC970_Cracked = 0;
32 bits<3> PPC970_Unit = 0;
34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
35 /// these must be reflected there! See comments there for what these are.
36 let TSFlags{0} = PPC970_First;
37 let TSFlags{1} = PPC970_Single;
38 let TSFlags{2} = PPC970_Cracked;
39 let TSFlags{5-3} = PPC970_Unit;
41 // Fields used for relation models.
44 // For cases where multiple instruction definitions really represent the
45 // same underlying instruction but with one definition for 64-bit arguments
46 // and one for 32-bit arguments, this bit breaks the degeneracy between
47 // the two forms and allows TableGen to generate mapping tables.
48 bit Interpretation64Bit = 0;
51 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
52 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
53 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
54 class PPC970_MicroCode;
56 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
57 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
58 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
59 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
60 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
61 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
62 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
63 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
65 // Two joined instructions; used to emit two adjacent instructions as one.
66 // The itinerary from the first instruction is used for scheduling and
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
72 field bits<64> SoftFail = 0;
75 bit PPC64 = 0; // Default value, override with isPPC64
77 let Namespace = "PPC";
78 let Inst{0-5} = opcode1;
79 let Inst{32-37} = opcode2;
80 let OutOperandList = OOL;
81 let InOperandList = IOL;
82 let AsmString = asmstr;
85 bits<1> PPC970_First = 0;
86 bits<1> PPC970_Single = 0;
87 bits<1> PPC970_Cracked = 0;
88 bits<3> PPC970_Unit = 0;
90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
91 /// these must be reflected there! See comments there for what these are.
92 let TSFlags{0} = PPC970_First;
93 let TSFlags{1} = PPC970_Single;
94 let TSFlags{2} = PPC970_Cracked;
95 let TSFlags{5-3} = PPC970_Unit;
97 // Fields used for relation models.
99 bit Interpretation64Bit = 0;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
104 InstrItinClass itin, list<dag> pattern>
105 : I<opcode, OOL, IOL, asmstr, itin> {
106 let Pattern = pattern;
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
122 let BI{0-1} = BIBO{5-6};
123 let BI{2-4} = CR{0-2};
125 let Inst{6-10} = BIBO{4-0};
126 let Inst{11-15} = BI;
127 let Inst{16-29} = BD;
132 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
140 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
141 dag OOL, dag IOL, string asmstr>
142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
146 let Inst{11-15} = bi;
147 let Inst{16-29} = BD;
152 class BForm_3<bits<6> opcode, bit aa, bit lk,
153 dag OOL, dag IOL, string asmstr>
154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
160 let Inst{11-15} = BI;
161 let Inst{16-29} = BD;
166 class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk,
167 dag OOL, dag IOL, string asmstr>
168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
173 let Inst{11-15} = BI;
174 let Inst{16-29} = BD;
180 class SCForm<bits<6> opcode, bits<1> xo,
181 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
183 : I<opcode, OOL, IOL, asmstr, itin> {
186 let Pattern = pattern;
188 let Inst{20-26} = LEV;
193 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
194 InstrItinClass itin, list<dag> pattern>
195 : I<opcode, OOL, IOL, asmstr, itin> {
200 let Pattern = pattern;
207 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
208 InstrItinClass itin, list<dag> pattern>
209 : I<opcode, OOL, IOL, asmstr, itin> {
213 let Pattern = pattern;
216 let Inst{11-15} = Addr{20-16}; // Base Reg
217 let Inst{16-31} = Addr{15-0}; // Displacement
220 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
221 InstrItinClass itin, list<dag> pattern>
222 : I<opcode, OOL, IOL, asmstr, itin> {
227 let Pattern = pattern;
235 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
236 InstrItinClass itin, list<dag> pattern>
237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
239 // Even though ADDICo does not really have an RC bit, provide
240 // the declaration of one here so that isDOT has something to set.
244 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
245 InstrItinClass itin, list<dag> pattern>
246 : I<opcode, OOL, IOL, asmstr, itin> {
250 let Pattern = pattern;
257 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
258 InstrItinClass itin, list<dag> pattern>
259 : I<opcode, OOL, IOL, asmstr, itin> {
264 let Pattern = pattern;
271 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
272 InstrItinClass itin, list<dag> pattern>
273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
278 class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL,
279 string asmstr, InstrItinClass itin,
281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> {
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
288 dag OOL, dag IOL, string asmstr,
289 InstrItinClass itin, list<dag> pattern>
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
294 let Pattern = pattern;
302 let Inst{43-47} = Addr{20-16}; // Base Reg
303 let Inst{48-63} = Addr{15-0}; // Displacement
306 // This is used to emit BL8+NOP.
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
308 dag OOL, dag IOL, string asmstr,
309 InstrItinClass itin, list<dag> pattern>
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
311 OOL, IOL, asmstr, itin, pattern> {
316 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
318 : I<opcode, OOL, IOL, asmstr, itin> {
327 let Inst{11-15} = RA;
331 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
333 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
337 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
339 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
341 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
343 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
349 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
350 InstrItinClass itin, list<dag> pattern>
351 : I<opcode, OOL, IOL, asmstr, itin> {
355 let Pattern = pattern;
357 let Inst{6-10} = RST;
358 let Inst{11-15} = DS_RA{18-14}; // Register #
359 let Inst{16-29} = DS_RA{13-0}; // Displacement.
360 let Inst{30-31} = xo;
365 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
366 InstrItinClass itin, list<dag> pattern>
367 : I<opcode, OOL, IOL, asmstr, itin> {
372 let Pattern = pattern;
374 bit RC = 0; // set by isDOT
376 let Inst{6-10} = RST;
379 let Inst{21-30} = xo;
383 class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr,
384 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> {
388 // This is the same as XForm_base_r3xo, but the first two operands are swapped
389 // when code is emitted.
390 class XForm_base_r3xo_swapped
391 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
393 : I<opcode, OOL, IOL, asmstr, itin> {
398 bit RC = 0; // set by isDOT
400 let Inst{6-10} = RST;
403 let Inst{21-30} = xo;
408 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
409 InstrItinClass itin, list<dag> pattern>
410 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
412 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
413 InstrItinClass itin, list<dag> pattern>
414 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
418 class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
419 InstrItinClass itin, list<dag> pattern>
420 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
425 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 InstrItinClass itin, list<dag> pattern>
427 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
428 let Pattern = pattern;
431 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
432 InstrItinClass itin, list<dag> pattern>
433 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
435 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
436 InstrItinClass itin, list<dag> pattern>
437 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
438 let Pattern = pattern;
441 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
442 InstrItinClass itin, list<dag> pattern>
443 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
445 let Pattern = pattern;
448 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
450 : I<opcode, OOL, IOL, asmstr, itin> {
459 let Inst{11-15} = RA;
460 let Inst{16-20} = RB;
461 let Inst{21-30} = xo;
465 class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
467 : I<opcode, OOL, IOL, asmstr, itin> {
472 let Inst{12-15} = SR;
473 let Inst{21-30} = xo;
476 class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
478 : I<opcode, OOL, IOL, asmstr, itin> {
482 let Inst{21-30} = xo;
485 class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
487 : I<opcode, OOL, IOL, asmstr, itin> {
492 let Inst{16-20} = RB;
493 let Inst{21-30} = xo;
496 class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
498 : I<opcode, OOL, IOL, asmstr, itin> {
504 let Inst{21-30} = xo;
507 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
509 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
513 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
515 : I<opcode, OOL, IOL, asmstr, itin> {
522 let Inst{11-15} = FRA;
523 let Inst{16-20} = FRB;
524 let Inst{21-30} = xo;
528 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
529 InstrItinClass itin, list<dag> pattern>
530 : I<opcode, OOL, IOL, asmstr, itin> {
531 let Pattern = pattern;
535 let Inst{21-30} = xo;
539 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
540 string asmstr, InstrItinClass itin, list<dag> pattern>
541 : I<opcode, OOL, IOL, asmstr, itin> {
544 let Pattern = pattern;
549 let Inst{21-30} = xo;
553 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
554 string asmstr, InstrItinClass itin, list<dag> pattern>
555 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
559 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
560 InstrItinClass itin, list<dag> pattern>
561 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
564 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
565 InstrItinClass itin, list<dag> pattern>
566 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
570 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
571 InstrItinClass itin, list<dag> pattern>
572 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
575 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
576 // numbers presumably relates to some document, but I haven't found it.
577 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
578 InstrItinClass itin, list<dag> pattern>
579 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
580 let Pattern = pattern;
582 bit RC = 0; // set by isDOT
584 let Inst{6-10} = RST;
586 let Inst{21-30} = xo;
589 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
590 InstrItinClass itin, list<dag> pattern>
591 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
592 let Pattern = pattern;
595 bit RC = 0; // set by isDOT
599 let Inst{21-30} = xo;
603 class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
604 InstrItinClass itin, list<dag> pattern>
605 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
611 class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
612 InstrItinClass itin, list<dag> pattern>
613 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
619 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
620 InstrItinClass itin, list<dag> pattern>
621 : I<opcode, OOL, IOL, asmstr, itin> {
626 let Pattern = pattern;
628 let Inst{6-10} = XT{4-0};
631 let Inst{21-30} = xo;
632 let Inst{31} = XT{5};
635 class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
636 InstrItinClass itin, list<dag> pattern>
637 : I<opcode, OOL, IOL, asmstr, itin> {
641 let Pattern = pattern;
643 let Inst{6-10} = XT{4-0};
645 let Inst{16-20} = XB{4-0};
646 let Inst{21-29} = xo;
647 let Inst{30} = XB{5};
648 let Inst{31} = XT{5};
651 class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
652 InstrItinClass itin, list<dag> pattern>
653 : I<opcode, OOL, IOL, asmstr, itin> {
657 let Pattern = pattern;
661 let Inst{16-20} = XB{4-0};
662 let Inst{21-29} = xo;
663 let Inst{30} = XB{5};
667 class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
668 InstrItinClass itin, list<dag> pattern>
669 : I<opcode, OOL, IOL, asmstr, itin> {
674 let Pattern = pattern;
676 let Inst{6-10} = XT{4-0};
679 let Inst{16-20} = XB{4-0};
680 let Inst{21-29} = xo;
681 let Inst{30} = XB{5};
682 let Inst{31} = XT{5};
685 class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
686 InstrItinClass itin, list<dag> pattern>
687 : I<opcode, OOL, IOL, asmstr, itin> {
692 let Pattern = pattern;
694 let Inst{6-10} = XT{4-0};
695 let Inst{11-15} = XA{4-0};
696 let Inst{16-20} = XB{4-0};
697 let Inst{21-28} = xo;
698 let Inst{29} = XA{5};
699 let Inst{30} = XB{5};
700 let Inst{31} = XT{5};
703 class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
704 InstrItinClass itin, list<dag> pattern>
705 : I<opcode, OOL, IOL, asmstr, itin> {
710 let Pattern = pattern;
714 let Inst{11-15} = XA{4-0};
715 let Inst{16-20} = XB{4-0};
716 let Inst{21-28} = xo;
717 let Inst{29} = XA{5};
718 let Inst{30} = XB{5};
722 class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
723 InstrItinClass itin, list<dag> pattern>
724 : I<opcode, OOL, IOL, asmstr, itin> {
730 let Pattern = pattern;
732 let Inst{6-10} = XT{4-0};
733 let Inst{11-15} = XA{4-0};
734 let Inst{16-20} = XB{4-0};
737 let Inst{24-28} = xo;
738 let Inst{29} = XA{5};
739 let Inst{30} = XB{5};
740 let Inst{31} = XT{5};
743 class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr,
744 InstrItinClass itin, list<dag> pattern>
745 : I<opcode, OOL, IOL, asmstr, itin> {
750 let Pattern = pattern;
752 bit RC = 0; // set by isDOT
754 let Inst{6-10} = XT{4-0};
755 let Inst{11-15} = XA{4-0};
756 let Inst{16-20} = XB{4-0};
758 let Inst{22-28} = xo;
759 let Inst{29} = XA{5};
760 let Inst{30} = XB{5};
761 let Inst{31} = XT{5};
764 class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
765 InstrItinClass itin, list<dag> pattern>
766 : I<opcode, OOL, IOL, asmstr, itin> {
772 let Pattern = pattern;
774 let Inst{6-10} = XT{4-0};
775 let Inst{11-15} = XA{4-0};
776 let Inst{16-20} = XB{4-0};
777 let Inst{21-25} = XC{4-0};
778 let Inst{26-27} = xo;
779 let Inst{28} = XC{5};
780 let Inst{29} = XA{5};
781 let Inst{30} = XB{5};
782 let Inst{31} = XT{5};
785 // DCB_Form - Form X instruction, used for dcb* instructions.
786 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
787 InstrItinClass itin, list<dag> pattern>
788 : I<31, OOL, IOL, asmstr, itin> {
792 let Pattern = pattern;
794 let Inst{6-10} = immfield;
797 let Inst{21-30} = xo;
802 // DSS_Form - Form X instruction, used for altivec dss* instructions.
803 class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
804 InstrItinClass itin, list<dag> pattern>
805 : I<31, OOL, IOL, asmstr, itin> {
810 let Pattern = pattern;
814 let Inst{9-10} = STRM;
817 let Inst{21-30} = xo;
822 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
823 InstrItinClass itin, list<dag> pattern>
824 : I<opcode, OOL, IOL, asmstr, itin> {
829 let Pattern = pattern;
831 let Inst{6-10} = CRD;
832 let Inst{11-15} = CRA;
833 let Inst{16-20} = CRB;
834 let Inst{21-30} = xo;
838 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
839 InstrItinClass itin, list<dag> pattern>
840 : I<opcode, OOL, IOL, asmstr, itin> {
843 let Pattern = pattern;
845 let Inst{6-10} = CRD;
846 let Inst{11-15} = CRD;
847 let Inst{16-20} = CRD;
848 let Inst{21-30} = xo;
852 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
853 InstrItinClass itin, list<dag> pattern>
854 : I<opcode, OOL, IOL, asmstr, itin> {
859 let Pattern = pattern;
862 let Inst{11-15} = BI;
864 let Inst{19-20} = BH;
865 let Inst{21-30} = xo;
869 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
870 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
871 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
872 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
876 let BI{0-1} = BIBO{5-6};
877 let BI{2-4} = CR{0-2};
881 class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk,
882 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
883 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
888 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
889 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
890 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
896 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
898 : I<opcode, OOL, IOL, asmstr, itin> {
904 let Inst{11-13} = BFA;
907 let Inst{21-30} = xo;
912 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
914 : I<opcode, OOL, IOL, asmstr, itin> {
919 let Inst{11} = SPR{4};
920 let Inst{12} = SPR{3};
921 let Inst{13} = SPR{2};
922 let Inst{14} = SPR{1};
923 let Inst{15} = SPR{0};
924 let Inst{16} = SPR{9};
925 let Inst{17} = SPR{8};
926 let Inst{18} = SPR{7};
927 let Inst{19} = SPR{6};
928 let Inst{20} = SPR{5};
929 let Inst{21-30} = xo;
933 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
934 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
935 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
939 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
941 : I<opcode, OOL, IOL, asmstr, itin> {
946 let Inst{21-30} = xo;
950 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
952 : I<opcode, OOL, IOL, asmstr, itin> {
958 let Inst{12-19} = FXM;
960 let Inst{21-30} = xo;
964 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
966 : I<opcode, OOL, IOL, asmstr, itin> {
972 let Inst{12-19} = FXM;
974 let Inst{21-30} = xo;
978 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
980 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
982 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
983 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
984 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
989 // This is probably 1.7.9, but I don't have the reference that uses this
990 // numbering scheme...
991 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
992 InstrItinClass itin, list<dag>pattern>
993 : I<opcode, OOL, IOL, asmstr, itin> {
997 bit RC = 0; // set by isDOT
998 let Pattern = pattern;
1001 let Inst{7-14} = FM;
1003 let Inst{16-20} = rT;
1004 let Inst{21-30} = xo;
1008 // 1.7.10 XS-Form - SRADI.
1009 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
1010 InstrItinClass itin, list<dag> pattern>
1011 : I<opcode, OOL, IOL, asmstr, itin> {
1016 bit RC = 0; // set by isDOT
1017 let Pattern = pattern;
1019 let Inst{6-10} = RS;
1020 let Inst{11-15} = A;
1021 let Inst{16-20} = SH{4,3,2,1,0};
1022 let Inst{21-29} = xo;
1023 let Inst{30} = SH{5};
1028 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
1029 InstrItinClass itin, list<dag> pattern>
1030 : I<opcode, OOL, IOL, asmstr, itin> {
1035 let Pattern = pattern;
1037 bit RC = 0; // set by isDOT
1039 let Inst{6-10} = RT;
1040 let Inst{11-15} = RA;
1041 let Inst{16-20} = RB;
1043 let Inst{22-30} = xo;
1047 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
1048 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
1049 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
1054 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1055 InstrItinClass itin, list<dag> pattern>
1056 : I<opcode, OOL, IOL, asmstr, itin> {
1062 let Pattern = pattern;
1064 bit RC = 0; // set by isDOT
1066 let Inst{6-10} = FRT;
1067 let Inst{11-15} = FRA;
1068 let Inst{16-20} = FRB;
1069 let Inst{21-25} = FRC;
1070 let Inst{26-30} = xo;
1074 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1075 InstrItinClass itin, list<dag> pattern>
1076 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1080 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1081 InstrItinClass itin, list<dag> pattern>
1082 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
1086 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
1087 InstrItinClass itin, list<dag> pattern>
1088 : I<opcode, OOL, IOL, asmstr, itin> {
1094 let Pattern = pattern;
1096 let Inst{6-10} = RT;
1097 let Inst{11-15} = RA;
1098 let Inst{16-20} = RB;
1099 let Inst{21-25} = COND;
1100 let Inst{26-30} = xo;
1105 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1106 InstrItinClass itin, list<dag> pattern>
1107 : I<opcode, OOL, IOL, asmstr, itin> {
1114 let Pattern = pattern;
1116 bit RC = 0; // set by isDOT
1118 let Inst{6-10} = RS;
1119 let Inst{11-15} = RA;
1120 let Inst{16-20} = RB;
1121 let Inst{21-25} = MB;
1122 let Inst{26-30} = ME;
1126 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
1127 InstrItinClass itin, list<dag> pattern>
1128 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
1132 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
1133 InstrItinClass itin, list<dag> pattern>
1134 : I<opcode, OOL, IOL, asmstr, itin> {
1140 let Pattern = pattern;
1142 bit RC = 0; // set by isDOT
1144 let Inst{6-10} = RS;
1145 let Inst{11-15} = RA;
1146 let Inst{16-20} = SH{4,3,2,1,0};
1147 let Inst{21-26} = MBE{4,3,2,1,0,5};
1148 let Inst{27-29} = xo;
1149 let Inst{30} = SH{5};
1153 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
1154 InstrItinClass itin, list<dag> pattern>
1155 : I<opcode, OOL, IOL, asmstr, itin> {
1161 let Pattern = pattern;
1163 bit RC = 0; // set by isDOT
1165 let Inst{6-10} = RS;
1166 let Inst{11-15} = RA;
1167 let Inst{16-20} = RB;
1168 let Inst{21-26} = MBE{4,3,2,1,0,5};
1169 let Inst{27-30} = xo;
1176 // VAForm_1 - DACB ordering.
1177 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
1178 InstrItinClass itin, list<dag> pattern>
1179 : I<4, OOL, IOL, asmstr, itin> {
1185 let Pattern = pattern;
1187 let Inst{6-10} = VD;
1188 let Inst{11-15} = VA;
1189 let Inst{16-20} = VB;
1190 let Inst{21-25} = VC;
1191 let Inst{26-31} = xo;
1194 // VAForm_1a - DABC ordering.
1195 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
1196 InstrItinClass itin, list<dag> pattern>
1197 : I<4, OOL, IOL, asmstr, itin> {
1203 let Pattern = pattern;
1205 let Inst{6-10} = VD;
1206 let Inst{11-15} = VA;
1207 let Inst{16-20} = VB;
1208 let Inst{21-25} = VC;
1209 let Inst{26-31} = xo;
1212 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
1213 InstrItinClass itin, list<dag> pattern>
1214 : I<4, OOL, IOL, asmstr, itin> {
1220 let Pattern = pattern;
1222 let Inst{6-10} = VD;
1223 let Inst{11-15} = VA;
1224 let Inst{16-20} = VB;
1226 let Inst{22-25} = SH;
1227 let Inst{26-31} = xo;
1231 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1232 InstrItinClass itin, list<dag> pattern>
1233 : I<4, OOL, IOL, asmstr, itin> {
1238 let Pattern = pattern;
1240 let Inst{6-10} = VD;
1241 let Inst{11-15} = VA;
1242 let Inst{16-20} = VB;
1243 let Inst{21-31} = xo;
1246 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1247 InstrItinClass itin, list<dag> pattern>
1248 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1254 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1255 InstrItinClass itin, list<dag> pattern>
1256 : I<4, OOL, IOL, asmstr, itin> {
1260 let Pattern = pattern;
1262 let Inst{6-10} = VD;
1263 let Inst{11-15} = 0;
1264 let Inst{16-20} = VB;
1265 let Inst{21-31} = xo;
1268 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1269 InstrItinClass itin, list<dag> pattern>
1270 : I<4, OOL, IOL, asmstr, itin> {
1274 let Pattern = pattern;
1276 let Inst{6-10} = VD;
1277 let Inst{11-15} = IMM;
1278 let Inst{16-20} = 0;
1279 let Inst{21-31} = xo;
1282 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1283 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1284 InstrItinClass itin, list<dag> pattern>
1285 : I<4, OOL, IOL, asmstr, itin> {
1288 let Pattern = pattern;
1290 let Inst{6-10} = VD;
1291 let Inst{11-15} = 0;
1292 let Inst{16-20} = 0;
1293 let Inst{21-31} = xo;
1296 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1297 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1298 InstrItinClass itin, list<dag> pattern>
1299 : I<4, OOL, IOL, asmstr, itin> {
1302 let Pattern = pattern;
1305 let Inst{11-15} = 0;
1306 let Inst{16-20} = VB;
1307 let Inst{21-31} = xo;
1311 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1312 InstrItinClass itin, list<dag> pattern>
1313 : I<4, OOL, IOL, asmstr, itin> {
1319 let Pattern = pattern;
1321 let Inst{6-10} = VD;
1322 let Inst{11-15} = VA;
1323 let Inst{16-20} = VB;
1325 let Inst{22-31} = xo;
1328 //===----------------------------------------------------------------------===//
1329 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1330 : I<0, OOL, IOL, asmstr, NoItinerary> {
1331 let isCodeGenOnly = 1;
1333 let Pattern = pattern;