1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // PowerPC instruction formats
14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
18 bit PPC64 = 0; // Default value, override with isPPC64
20 let Namespace = "PPC";
21 let Inst{0-5} = opcode;
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
27 bits<1> PPC970_First = 0;
28 bits<1> PPC970_Single = 0;
29 bits<1> PPC970_Cracked = 0;
30 bits<3> PPC970_Unit = 0;
32 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
33 /// these must be reflected there! See comments there for what these are.
34 let TSFlags{0} = PPC970_First;
35 let TSFlags{1} = PPC970_Single;
36 let TSFlags{2} = PPC970_Cracked;
37 let TSFlags{5-3} = PPC970_Unit;
39 // Fields used for relation models.
42 // For cases where multiple instruction definitions really represent the
43 // same underlying instruction but with one definition for 64-bit arguments
44 // and one for 32-bit arguments, this bit breaks the degeneracy between
45 // the two forms and allows TableGen to generate mapping tables.
46 bit Interpretation64Bit = 0;
49 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
50 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
51 class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
52 class PPC970_MicroCode;
54 class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; }
55 class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; }
56 class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; }
57 class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; }
58 class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; }
59 class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; }
60 class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; }
61 class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; }
63 // Two joined instructions; used to emit two adjacent instructions as one.
64 // The itinerary from the first instruction is used for scheduling and
66 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
71 bit PPC64 = 0; // Default value, override with isPPC64
73 let Namespace = "PPC";
74 let Inst{0-5} = opcode1;
75 let Inst{32-37} = opcode2;
76 let OutOperandList = OOL;
77 let InOperandList = IOL;
78 let AsmString = asmstr;
81 bits<1> PPC970_First = 0;
82 bits<1> PPC970_Single = 0;
83 bits<1> PPC970_Cracked = 0;
84 bits<3> PPC970_Unit = 0;
86 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to
87 /// these must be reflected there! See comments there for what these are.
88 let TSFlags{0} = PPC970_First;
89 let TSFlags{1} = PPC970_Single;
90 let TSFlags{2} = PPC970_Cracked;
91 let TSFlags{5-3} = PPC970_Unit;
93 // Fields used for relation models.
95 bit Interpretation64Bit = 0;
99 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
100 InstrItinClass itin, list<dag> pattern>
101 : I<opcode, OOL, IOL, asmstr, itin> {
102 let Pattern = pattern;
111 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
112 : I<opcode, OOL, IOL, asmstr, BrB> {
113 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
118 let BI{0-1} = BIBO{5-6};
119 let BI{2-4} = CR{0-2};
121 let Inst{6-10} = BIBO{4-0};
122 let Inst{11-15} = BI;
123 let Inst{16-29} = BD;
128 class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
130 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
136 class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
137 dag OOL, dag IOL, string asmstr>
138 : I<opcode, OOL, IOL, asmstr, BrB> {
142 let Inst{11-15} = bi;
143 let Inst{16-29} = BD;
148 class BForm_3<bits<6> opcode, bit aa, bit lk,
149 dag OOL, dag IOL, string asmstr>
150 : I<opcode, OOL, IOL, asmstr, BrB> {
156 let Inst{11-15} = BI;
157 let Inst{16-29} = BD;
163 class SCForm<bits<6> opcode, bits<1> xo,
164 dag OOL, dag IOL, string asmstr, InstrItinClass itin,
166 : I<opcode, OOL, IOL, asmstr, itin> {
169 let Pattern = pattern;
171 let Inst{20-26} = LEV;
176 class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
177 InstrItinClass itin, list<dag> pattern>
178 : I<opcode, OOL, IOL, asmstr, itin> {
183 let Pattern = pattern;
190 class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
191 InstrItinClass itin, list<dag> pattern>
192 : I<opcode, OOL, IOL, asmstr, itin> {
196 let Pattern = pattern;
199 let Inst{11-15} = Addr{20-16}; // Base Reg
200 let Inst{16-31} = Addr{15-0}; // Displacement
203 class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
204 InstrItinClass itin, list<dag> pattern>
205 : I<opcode, OOL, IOL, asmstr, itin> {
210 let Pattern = pattern;
218 class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
219 InstrItinClass itin, list<dag> pattern>
220 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
222 // Even though ADDICo does not really have an RC bit, provide
223 // the declaration of one here so that isDOT has something to set.
227 class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
228 InstrItinClass itin, list<dag> pattern>
229 : I<opcode, OOL, IOL, asmstr, itin> {
233 let Pattern = pattern;
240 class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
241 InstrItinClass itin, list<dag> pattern>
242 : I<opcode, OOL, IOL, asmstr, itin> {
247 let Pattern = pattern;
254 class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
255 InstrItinClass itin, list<dag> pattern>
256 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
261 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
262 dag OOL, dag IOL, string asmstr,
263 InstrItinClass itin, list<dag> pattern>
264 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
268 let Pattern = pattern;
276 let Inst{43-47} = Addr{20-16}; // Base Reg
277 let Inst{48-63} = Addr{15-0}; // Displacement
280 // This is used to emit BL8+NOP.
281 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
282 dag OOL, dag IOL, string asmstr,
283 InstrItinClass itin, list<dag> pattern>
284 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
285 OOL, IOL, asmstr, itin, pattern> {
290 class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
292 : I<opcode, OOL, IOL, asmstr, itin> {
301 let Inst{11-15} = RA;
305 class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
307 : DForm_5<opcode, OOL, IOL, asmstr, itin> {
311 class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
313 : DForm_5<opcode, OOL, IOL, asmstr, itin>;
315 class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
317 : DForm_6<opcode, OOL, IOL, asmstr, itin> {
323 class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
324 InstrItinClass itin, list<dag> pattern>
325 : I<opcode, OOL, IOL, asmstr, itin> {
329 let Pattern = pattern;
331 let Inst{6-10} = RST;
332 let Inst{11-15} = DS_RA{18-14}; // Register #
333 let Inst{16-29} = DS_RA{13-0}; // Displacement.
334 let Inst{30-31} = xo;
337 class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
338 InstrItinClass itin, list<dag> pattern>
339 : I<opcode, OOL, IOL, asmstr, itin> {
344 let Pattern = pattern;
346 let Inst{6-10} = RST;
347 let Inst{11-15} = RA;
348 let Inst{16-29} = DS;
349 let Inst{30-31} = xo;
353 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
354 InstrItinClass itin, list<dag> pattern>
355 : I<opcode, OOL, IOL, asmstr, itin> {
360 let Pattern = pattern;
362 bit RC = 0; // set by isDOT
364 let Inst{6-10} = RST;
367 let Inst{21-30} = xo;
371 // This is the same as XForm_base_r3xo, but the first two operands are swapped
372 // when code is emitted.
373 class XForm_base_r3xo_swapped
374 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
376 : I<opcode, OOL, IOL, asmstr, itin> {
381 bit RC = 0; // set by isDOT
383 let Inst{6-10} = RST;
386 let Inst{21-30} = xo;
391 class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
392 InstrItinClass itin, list<dag> pattern>
393 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
395 class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
396 InstrItinClass itin, list<dag> pattern>
397 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
401 class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
402 InstrItinClass itin, list<dag> pattern>
403 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
404 let Pattern = pattern;
407 class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
408 InstrItinClass itin, list<dag> pattern>
409 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
411 class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
412 InstrItinClass itin, list<dag> pattern>
413 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
414 let Pattern = pattern;
417 class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
418 InstrItinClass itin, list<dag> pattern>
419 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
421 let Pattern = pattern;
424 class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
426 : I<opcode, OOL, IOL, asmstr, itin> {
435 let Inst{11-15} = RA;
436 let Inst{16-20} = RB;
437 let Inst{21-30} = xo;
441 class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
443 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
447 class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
449 : I<opcode, OOL, IOL, asmstr, itin> {
456 let Inst{11-15} = FRA;
457 let Inst{16-20} = FRB;
458 let Inst{21-30} = xo;
462 class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
463 InstrItinClass itin, list<dag> pattern>
464 : I<opcode, OOL, IOL, asmstr, itin> {
465 let Pattern = pattern;
469 let Inst{21-30} = xo;
473 class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
474 string asmstr, InstrItinClass itin, list<dag> pattern>
475 : I<opcode, OOL, IOL, asmstr, itin> {
478 let Pattern = pattern;
483 let Inst{21-30} = xo;
487 class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
488 string asmstr, InstrItinClass itin, list<dag> pattern>
489 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
493 class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
494 InstrItinClass itin, list<dag> pattern>
495 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
498 class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
499 InstrItinClass itin, list<dag> pattern>
500 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
504 class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
505 InstrItinClass itin, list<dag> pattern>
506 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
509 // This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of
510 // numbers presumably relates to some document, but I haven't found it.
511 class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
512 InstrItinClass itin, list<dag> pattern>
513 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
514 let Pattern = pattern;
516 bit RC = 0; // set by isDOT
518 let Inst{6-10} = RST;
520 let Inst{21-30} = xo;
523 class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
524 InstrItinClass itin, list<dag> pattern>
525 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
526 let Pattern = pattern;
529 bit RC = 0; // set by isDOT
533 let Inst{21-30} = xo;
537 // DCB_Form - Form X instruction, used for dcb* instructions.
538 class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
539 InstrItinClass itin, list<dag> pattern>
540 : I<31, OOL, IOL, asmstr, itin> {
544 let Pattern = pattern;
546 let Inst{6-10} = immfield;
549 let Inst{21-30} = xo;
554 // DSS_Form - Form X instruction, used for altivec dss* instructions.
555 class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
556 InstrItinClass itin, list<dag> pattern>
557 : I<31, OOL, IOL, asmstr, itin> {
563 let Pattern = pattern;
567 let Inst{9-10} = STRM;
570 let Inst{21-30} = xo;
575 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
576 InstrItinClass itin, list<dag> pattern>
577 : I<opcode, OOL, IOL, asmstr, itin> {
582 let Pattern = pattern;
584 let Inst{6-10} = CRD;
585 let Inst{11-15} = CRA;
586 let Inst{16-20} = CRB;
587 let Inst{21-30} = xo;
591 class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
592 InstrItinClass itin, list<dag> pattern>
593 : I<opcode, OOL, IOL, asmstr, itin> {
596 let Pattern = pattern;
598 let Inst{6-10} = CRD;
599 let Inst{11-15} = CRD;
600 let Inst{16-20} = CRD;
601 let Inst{21-30} = xo;
605 class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr,
606 InstrItinClass itin, list<dag> pattern>
607 : I<opcode, OOL, IOL, asmstr, itin> {
612 let Pattern = pattern;
615 let Inst{11-15} = BI;
617 let Inst{19-20} = BH;
618 let Inst{21-30} = xo;
622 class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
623 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
624 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
625 bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
629 let BI{0-1} = BIBO{5-6};
630 let BI{2-4} = CR{0-2};
635 class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk,
636 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
637 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
643 class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
645 : I<opcode, OOL, IOL, asmstr, itin> {
651 let Inst{11-13} = BFA;
654 let Inst{21-30} = xo;
659 class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
661 : I<opcode, OOL, IOL, asmstr, itin> {
666 let Inst{11} = SPR{4};
667 let Inst{12} = SPR{3};
668 let Inst{13} = SPR{2};
669 let Inst{14} = SPR{1};
670 let Inst{15} = SPR{0};
671 let Inst{16} = SPR{9};
672 let Inst{17} = SPR{8};
673 let Inst{18} = SPR{7};
674 let Inst{19} = SPR{6};
675 let Inst{20} = SPR{5};
676 let Inst{21-30} = xo;
680 class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
681 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
682 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
686 class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
688 : I<opcode, OOL, IOL, asmstr, itin> {
693 let Inst{21-30} = xo;
697 class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
699 : I<opcode, OOL, IOL, asmstr, itin> {
705 let Inst{12-19} = FXM;
707 let Inst{21-30} = xo;
711 class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
713 : I<opcode, OOL, IOL, asmstr, itin> {
719 let Inst{12-19} = FXM;
721 let Inst{21-30} = xo;
725 class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
727 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
729 class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr,
730 dag OOL, dag IOL, string asmstr, InstrItinClass itin>
731 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
736 // This is probably 1.7.9, but I don't have the reference that uses this
737 // numbering scheme...
738 class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
739 InstrItinClass itin, list<dag>pattern>
740 : I<opcode, OOL, IOL, asmstr, itin> {
744 bit RC = 0; // set by isDOT
745 let Pattern = pattern;
750 let Inst{16-20} = rT;
751 let Inst{21-30} = xo;
755 // 1.7.10 XS-Form - SRADI.
756 class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
757 InstrItinClass itin, list<dag> pattern>
758 : I<opcode, OOL, IOL, asmstr, itin> {
763 bit RC = 0; // set by isDOT
764 let Pattern = pattern;
768 let Inst{16-20} = SH{4,3,2,1,0};
769 let Inst{21-29} = xo;
770 let Inst{30} = SH{5};
775 class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
776 InstrItinClass itin, list<dag> pattern>
777 : I<opcode, OOL, IOL, asmstr, itin> {
782 let Pattern = pattern;
784 bit RC = 0; // set by isDOT
787 let Inst{11-15} = RA;
788 let Inst{16-20} = RB;
790 let Inst{22-30} = xo;
794 class XOForm_3<bits<6> opcode, bits<9> xo, bit oe,
795 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
796 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
801 class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
802 InstrItinClass itin, list<dag> pattern>
803 : I<opcode, OOL, IOL, asmstr, itin> {
809 let Pattern = pattern;
811 bit RC = 0; // set by isDOT
813 let Inst{6-10} = FRT;
814 let Inst{11-15} = FRA;
815 let Inst{16-20} = FRB;
816 let Inst{21-25} = FRC;
817 let Inst{26-30} = xo;
821 class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
822 InstrItinClass itin, list<dag> pattern>
823 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
827 class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
828 InstrItinClass itin, list<dag> pattern>
829 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
833 class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
834 InstrItinClass itin, list<dag> pattern>
835 : I<opcode, OOL, IOL, asmstr, itin> {
841 let Pattern = pattern;
844 let Inst{11-15} = RA;
845 let Inst{16-20} = RB;
846 let Inst{21-25} = COND;
847 let Inst{26-30} = xo;
852 class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
853 InstrItinClass itin, list<dag> pattern>
854 : I<opcode, OOL, IOL, asmstr, itin> {
861 let Pattern = pattern;
863 bit RC = 0; // set by isDOT
866 let Inst{11-15} = RA;
867 let Inst{16-20} = RB;
868 let Inst{21-25} = MB;
869 let Inst{26-30} = ME;
873 class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
874 InstrItinClass itin, list<dag> pattern>
875 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
879 class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
880 InstrItinClass itin, list<dag> pattern>
881 : I<opcode, OOL, IOL, asmstr, itin> {
887 let Pattern = pattern;
889 bit RC = 0; // set by isDOT
892 let Inst{11-15} = RA;
893 let Inst{16-20} = SH{4,3,2,1,0};
894 let Inst{21-26} = MBE{4,3,2,1,0,5};
895 let Inst{27-29} = xo;
896 let Inst{30} = SH{5};
900 class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
901 InstrItinClass itin, list<dag> pattern>
902 : I<opcode, OOL, IOL, asmstr, itin> {
908 let Pattern = pattern;
910 bit RC = 0; // set by isDOT
913 let Inst{11-15} = RA;
914 let Inst{16-20} = RB;
915 let Inst{21-26} = MBE{4,3,2,1,0,5};
916 let Inst{27-30} = xo;
923 // VAForm_1 - DACB ordering.
924 class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
925 InstrItinClass itin, list<dag> pattern>
926 : I<4, OOL, IOL, asmstr, itin> {
932 let Pattern = pattern;
935 let Inst{11-15} = VA;
936 let Inst{16-20} = VB;
937 let Inst{21-25} = VC;
938 let Inst{26-31} = xo;
941 // VAForm_1a - DABC ordering.
942 class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
943 InstrItinClass itin, list<dag> pattern>
944 : I<4, OOL, IOL, asmstr, itin> {
950 let Pattern = pattern;
953 let Inst{11-15} = VA;
954 let Inst{16-20} = VB;
955 let Inst{21-25} = VC;
956 let Inst{26-31} = xo;
959 class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
960 InstrItinClass itin, list<dag> pattern>
961 : I<4, OOL, IOL, asmstr, itin> {
967 let Pattern = pattern;
970 let Inst{11-15} = VA;
971 let Inst{16-20} = VB;
973 let Inst{22-25} = SH;
974 let Inst{26-31} = xo;
978 class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
979 InstrItinClass itin, list<dag> pattern>
980 : I<4, OOL, IOL, asmstr, itin> {
985 let Pattern = pattern;
988 let Inst{11-15} = VA;
989 let Inst{16-20} = VB;
990 let Inst{21-31} = xo;
993 class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
994 InstrItinClass itin, list<dag> pattern>
995 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1001 class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1002 InstrItinClass itin, list<dag> pattern>
1003 : I<4, OOL, IOL, asmstr, itin> {
1007 let Pattern = pattern;
1009 let Inst{6-10} = VD;
1010 let Inst{11-15} = 0;
1011 let Inst{16-20} = VB;
1012 let Inst{21-31} = xo;
1015 class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1016 InstrItinClass itin, list<dag> pattern>
1017 : I<4, OOL, IOL, asmstr, itin> {
1021 let Pattern = pattern;
1023 let Inst{6-10} = VD;
1024 let Inst{11-15} = IMM;
1025 let Inst{16-20} = 0;
1026 let Inst{21-31} = xo;
1029 /// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1030 class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1031 InstrItinClass itin, list<dag> pattern>
1032 : I<4, OOL, IOL, asmstr, itin> {
1035 let Pattern = pattern;
1037 let Inst{6-10} = VD;
1038 let Inst{11-15} = 0;
1039 let Inst{16-20} = 0;
1040 let Inst{21-31} = xo;
1043 /// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1044 class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1045 InstrItinClass itin, list<dag> pattern>
1046 : I<4, OOL, IOL, asmstr, itin> {
1049 let Pattern = pattern;
1052 let Inst{11-15} = 0;
1053 let Inst{16-20} = VB;
1054 let Inst{21-31} = xo;
1058 class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1059 InstrItinClass itin, list<dag> pattern>
1060 : I<4, OOL, IOL, asmstr, itin> {
1066 let Pattern = pattern;
1068 let Inst{6-10} = VD;
1069 let Inst{11-15} = VA;
1070 let Inst{16-20} = VB;
1072 let Inst{22-31} = xo;
1075 //===----------------------------------------------------------------------===//
1076 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1077 : I<0, OOL, IOL, asmstr, NoItinerary> {
1078 let isCodeGenOnly = 1;
1080 let Pattern = pattern;