1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 /// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
19 /// shuffle mask for the VPKUHUM or VPKUWUM instructions.
20 def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
21 return PPC::isVPKUHUMShuffleMask(N, false);
23 def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
24 return PPC::isVPKUWUMShuffleMask(N, false);
27 def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
28 return PPC::isVPKUHUMShuffleMask(N, true);
30 def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
31 return PPC::isVPKUWUMShuffleMask(N, true);
35 def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
36 return PPC::isVMRGLShuffleMask(N, 1, false);
38 def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
39 return PPC::isVMRGLShuffleMask(N, 2, false);
41 def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
42 return PPC::isVMRGLShuffleMask(N, 4, false);
44 def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
45 return PPC::isVMRGHShuffleMask(N, 1, false);
47 def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
48 return PPC::isVMRGHShuffleMask(N, 2, false);
50 def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
51 return PPC::isVMRGHShuffleMask(N, 4, false);
54 def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
55 return PPC::isVMRGLShuffleMask(N, 1, true);
57 def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
58 return PPC::isVMRGLShuffleMask(N, 2, true);
60 def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
61 return PPC::isVMRGLShuffleMask(N, 4, true);
63 def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
64 return PPC::isVMRGHShuffleMask(N, 1, true);
66 def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
67 return PPC::isVMRGHShuffleMask(N, 2, true);
69 def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
70 return PPC::isVMRGHShuffleMask(N, 4, true);
74 def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
75 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
77 def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
78 return PPC::isVSLDOIShuffleMask(N, false) != -1;
81 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
82 /// vector_shuffle(X,undef,mask) by the dag combiner.
83 def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
84 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
86 def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
87 return PPC::isVSLDOIShuffleMask(N, true) != -1;
88 }], VSLDOI_unary_get_imm>;
91 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
92 def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
93 return getI32Imm(PPC::getVSPLTImmediate(N, 1));
95 def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
96 return PPC::isSplatShuffleMask(N, 1);
98 def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
99 return getI32Imm(PPC::getVSPLTImmediate(N, 2));
101 def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
102 return PPC::isSplatShuffleMask(N, 2);
104 def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
105 return getI32Imm(PPC::getVSPLTImmediate(N, 4));
107 def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
108 return PPC::isSplatShuffleMask(N, 4);
112 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
113 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
114 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
116 def vecspltisb : PatLeaf<(build_vector), [{
117 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).Val != 0;
118 }], VSPLTISB_get_imm>;
120 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
121 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
122 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
124 def vecspltish : PatLeaf<(build_vector), [{
125 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).Val != 0;
126 }], VSPLTISH_get_imm>;
128 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
129 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
130 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
132 def vecspltisw : PatLeaf<(build_vector), [{
133 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
134 }], VSPLTISW_get_imm>;
136 //===----------------------------------------------------------------------===//
137 // Helpers for defining instructions that directly correspond to intrinsics.
139 // VA1a_Int - A VAForm_1a intrinsic definition.
140 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
141 : VAForm_1a<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
142 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
143 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
145 // VX1_Int - A VXForm_1 intrinsic definition.
146 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
147 : VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
148 !strconcat(opc, " $vD, $vA, $vB"), VecFP,
149 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
151 // VX2_Int - A VXForm_2 intrinsic definition.
152 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
153 : VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
154 !strconcat(opc, " $vD, $vB"), VecFP,
155 [(set VRRC:$vD, (IntID VRRC:$vB))]>;
157 //===----------------------------------------------------------------------===//
158 // Instruction Definitions.
160 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; IMPLICIT_DEF_VRRC $rD",
161 [(set VRRC:$rD, (v4i32 (undef)))]>;
163 let noResults = 1 in {
164 def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
165 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
166 def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
167 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
168 def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
169 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
172 def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
173 "mfvcr $vD", LdStGeneral,
174 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>;
175 def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
176 "mtvcr $vB", LdStGeneral,
177 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
179 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
180 def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
181 "lvebx $vD, $src", LdStGeneral,
182 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
183 def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
184 "lvehx $vD, $src", LdStGeneral,
185 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
186 def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
187 "lvewx $vD, $src", LdStGeneral,
188 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
189 def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
190 "lvx $vD, $src", LdStGeneral,
191 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
192 def LVXL : XForm_1<31, 359, (ops VRRC:$vD, memrr:$src),
193 "lvxl $vD, $src", LdStGeneral,
194 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
197 def LVSL : XForm_1<31, 6, (ops VRRC:$vD, memrr:$src),
198 "lvsl $vD, $src", LdStGeneral,
199 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
201 def LVSR : XForm_1<31, 38, (ops VRRC:$vD, memrr:$src),
202 "lvsr $vD, $src", LdStGeneral,
203 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
206 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
207 def STVEBX: XForm_8<31, 135, (ops VRRC:$rS, memrr:$dst),
208 "stvebx $rS, $dst", LdStGeneral,
209 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
210 def STVEHX: XForm_8<31, 167, (ops VRRC:$rS, memrr:$dst),
211 "stvehx $rS, $dst", LdStGeneral,
212 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>;
213 def STVEWX: XForm_8<31, 199, (ops VRRC:$rS, memrr:$dst),
214 "stvewx $rS, $dst", LdStGeneral,
215 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>;
216 def STVX : XForm_8<31, 231, (ops VRRC:$rS, memrr:$dst),
217 "stvx $rS, $dst", LdStGeneral,
218 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>;
219 def STVXL : XForm_8<31, 487, (ops VRRC:$rS, memrr:$dst),
220 "stvxl $rS, $dst", LdStGeneral,
221 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>;
224 let PPC970_Unit = 5 in { // VALU Operations.
225 // VA-Form instructions. 3-input AltiVec ops.
226 def VMADDFP : VAForm_1<46, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
227 "vmaddfp $vD, $vA, $vC, $vB", VecFP,
228 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC),
230 Requires<[FPContractions]>;
231 def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
232 "vnmsubfp $vD, $vA, $vC, $vB", VecFP,
233 [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
235 Requires<[FPContractions]>;
237 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>;
238 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>;
239 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>;
240 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>;
241 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
244 def VSLDOI : VAForm_2<44, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, u5imm:$SH),
245 "vsldoi $vD, $vA, $vB, $SH", VecFP,
247 (vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
248 VSLDOI_shuffle_mask:$SH))]>;
250 // VX-Form instructions. AltiVec arithmetic ops.
251 def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
252 "vaddfp $vD, $vA, $vB", VecFP,
253 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
255 def VADDUBM : VXForm_1<0, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
256 "vaddubm $vD, $vA, $vB", VecGeneral,
257 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>;
258 def VADDUHM : VXForm_1<64, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
259 "vadduhm $vD, $vA, $vB", VecGeneral,
260 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>;
261 def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
262 "vadduwm $vD, $vA, $vB", VecGeneral,
263 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
265 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>;
266 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>;
267 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>;
268 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>;
269 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>;
270 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>;
271 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>;
274 def VAND : VXForm_1<1028, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
275 "vand $vD, $vA, $vB", VecFP,
276 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>;
277 def VANDC : VXForm_1<1092, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
278 "vandc $vD, $vA, $vB", VecFP,
279 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), (vnot VRRC:$vB)))]>;
281 def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
282 "vcfsx $vD, $vB, $UIMM", VecFP,
284 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
285 def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
286 "vcfux $vD, $vB, $UIMM", VecFP,
288 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
289 def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
290 "vctsxs $vD, $vB, $UIMM", VecFP,
292 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>;
293 def VCTUXS : VXForm_1<906, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
294 "vctuxs $vD, $vB, $UIMM", VecFP,
296 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
297 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
298 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
300 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>;
301 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>;
302 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>;
303 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>;
304 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>;
305 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>;
307 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>;
308 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>;
309 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>;
310 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>;
311 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>;
312 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>;
313 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>;
314 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>;
315 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>;
316 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>;
317 def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>;
318 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>;
319 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
320 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
322 def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
323 "vmrghb $vD, $vA, $vB", VecFP,
324 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
325 VRRC:$vB, VMRGHB_shuffle_mask))]>;
326 def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
327 "vmrghh $vD, $vA, $vB", VecFP,
328 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
329 VRRC:$vB, VMRGHH_shuffle_mask))]>;
330 def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
331 "vmrghw $vD, $vA, $vB", VecFP,
332 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
333 VRRC:$vB, VMRGHW_shuffle_mask))]>;
334 def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
335 "vmrglb $vD, $vA, $vB", VecFP,
336 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
337 VRRC:$vB, VMRGLB_shuffle_mask))]>;
338 def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
339 "vmrglh $vD, $vA, $vB", VecFP,
340 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
341 VRRC:$vB, VMRGLH_shuffle_mask))]>;
342 def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
343 "vmrglw $vD, $vA, $vB", VecFP,
344 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
345 VRRC:$vB, VMRGLW_shuffle_mask))]>;
347 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
348 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
349 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>;
350 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
351 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
352 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
354 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
355 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
356 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
357 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
358 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
359 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
360 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
361 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
363 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
364 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
365 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
366 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
367 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
368 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
370 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
372 def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
373 "vsubfp $vD, $vA, $vB", VecGeneral,
374 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
375 def VSUBUBM : VXForm_1<1024, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
376 "vsububm $vD, $vA, $vB", VecGeneral,
377 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>;
378 def VSUBUHM : VXForm_1<1088, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
379 "vsubuhm $vD, $vA, $vB", VecGeneral,
380 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>;
381 def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
382 "vsubuwm $vD, $vA, $vB", VecGeneral,
383 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
385 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
386 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
387 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
388 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
389 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
390 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
391 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
392 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
393 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
394 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
395 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
397 def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
398 "vnor $vD, $vA, $vB", VecFP,
399 [(set VRRC:$vD, (vnot (or (v4i32 VRRC:$vA), VRRC:$vB)))]>;
400 def VOR : VXForm_1<1156, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
401 "vor $vD, $vA, $vB", VecFP,
402 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>;
403 def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
404 "vxor $vD, $vA, $vB", VecFP,
405 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
407 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
408 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
409 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
411 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >;
412 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
413 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
414 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
415 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
417 def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
418 "vspltb $vD, $vB, $UIMM", VecPerm,
419 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
420 VSPLTB_shuffle_mask:$UIMM))]>;
421 def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
422 "vsplth $vD, $vB, $UIMM", VecPerm,
423 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
424 VSPLTH_shuffle_mask:$UIMM))]>;
425 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
426 "vspltw $vD, $vB, $UIMM", VecPerm,
427 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
428 VSPLTW_shuffle_mask:$UIMM))]>;
430 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
431 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
432 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
433 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
434 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
435 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
436 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
437 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
440 def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
441 "vspltisb $vD, $SIMM", VecPerm,
442 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>;
443 def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
444 "vspltish $vD, $SIMM", VecPerm,
445 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>;
446 def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
447 "vspltisw $vD, $SIMM", VecPerm,
448 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>;
451 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
452 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
453 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
454 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
455 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
456 def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
457 "vpkuhum $vD, $vA, $vB", VecFP,
458 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
459 VRRC:$vB, VPKUHUM_shuffle_mask))]>;
460 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
461 def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
462 "vpkuwum $vD, $vA, $vB", VecFP,
463 [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
464 VRRC:$vB, VPKUWUM_shuffle_mask))]>;
465 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
468 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>;
469 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>;
470 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>;
471 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>;
472 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>;
473 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>;
476 // Altivec Comparisons.
478 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
479 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
480 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>;
481 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
482 : VXRForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFPCompare,
483 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> {
488 // f32 element comparisons.0
489 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
490 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
491 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
492 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
493 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
494 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
495 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
496 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
498 // i8 element comparisons.
499 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
500 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
501 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
502 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
503 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
504 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
506 // i16 element comparisons.
507 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
508 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
509 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
510 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
511 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
512 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
514 // i32 element comparisons.
515 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
516 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
517 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
518 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
519 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
520 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
522 def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
523 "vxor $vD, $vD, $vD", VecFP,
524 [(set VRRC:$vD, (v4i32 immAllZerosV))]>;
527 //===----------------------------------------------------------------------===//
528 // Additional Altivec Patterns
532 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
533 def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>;
534 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
535 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
536 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM),
537 (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
538 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM),
539 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
540 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM),
541 (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
544 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VRRC)>;
545 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VRRC)>;
546 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VRRC)>;
549 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
552 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
553 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
556 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
557 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
558 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
560 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
561 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
562 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
564 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
565 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
566 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
568 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
569 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
570 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
574 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
575 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
576 (VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
577 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
578 (VPKUWUM VRRC:$vA, VRRC:$vA)>;
579 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
580 (VPKUHUM VRRC:$vA, VRRC:$vA)>;
583 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
584 (VMRGLB VRRC:$vA, VRRC:$vA)>;
585 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
586 (VMRGLH VRRC:$vA, VRRC:$vA)>;
587 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
588 (VMRGLW VRRC:$vA, VRRC:$vA)>;
589 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
590 (VMRGHB VRRC:$vA, VRRC:$vA)>;
591 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
592 (VMRGHH VRRC:$vA, VRRC:$vA)>;
593 def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
594 (VMRGHW VRRC:$vA, VRRC:$vA)>;
596 // Logical Operations
597 def : Pat<(v4i32 (vnot VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
598 def : Pat<(v4i32 (vnot_conv VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>;
600 def : Pat<(v4i32 (vnot_conv (or VRRC:$A, VRRC:$B))),
601 (VNOR VRRC:$A, VRRC:$B)>;
602 def : Pat<(v4i32 (and VRRC:$A, (vnot_conv VRRC:$B))),
603 (VANDC VRRC:$A, VRRC:$B)>;
605 def : Pat<(fmul VRRC:$vA, VRRC:$vB),
606 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>;
608 // Fused multiply add and multiply sub for packed float. These are represented
609 // separately from the real instructions above, for operations that must have
610 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
611 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
612 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
613 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
614 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
616 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
617 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
618 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
619 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
621 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC),
622 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>;