1 //===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Altivec extension to the PowerPC instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Altivec transformation functions and pattern fragments.
18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be
20 def vnot_ppc : PatFrag<(ops node:$in),
21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>;
23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
24 (vector_shuffle node:$lhs, node:$rhs), [{
25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false,
28 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
29 (vector_shuffle node:$lhs, node:$rhs), [{
30 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false,
33 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
34 (vector_shuffle node:$lhs, node:$rhs), [{
35 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true,
38 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
39 (vector_shuffle node:$lhs, node:$rhs), [{
40 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true,
45 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
49 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
53 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
55 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
57 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
61 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
65 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
66 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
67 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
71 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
72 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
75 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
76 (vector_shuffle node:$lhs, node:$rhs), [{
77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
79 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
80 (vector_shuffle node:$lhs, node:$rhs), [{
81 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
83 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
84 (vector_shuffle node:$lhs, node:$rhs), [{
85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
87 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
88 (vector_shuffle node:$lhs, node:$rhs), [{
89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
91 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
92 (vector_shuffle node:$lhs, node:$rhs), [{
93 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
97 // These fragments are provided for little-endian, where the inputs must be
98 // swapped for correct semantics.
99 def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
100 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
101 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
103 def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
104 (vector_shuffle node:$lhs, node:$rhs), [{
105 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
107 def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
108 (vector_shuffle node:$lhs, node:$rhs), [{
109 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
111 def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
112 (vector_shuffle node:$lhs, node:$rhs), [{
113 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
115 def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
116 (vector_shuffle node:$lhs, node:$rhs), [{
117 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
119 def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
120 (vector_shuffle node:$lhs, node:$rhs), [{
121 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
125 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
126 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false, *CurDAG));
128 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
129 (vector_shuffle node:$lhs, node:$rhs), [{
130 return PPC::isVSLDOIShuffleMask(N, false, *CurDAG) != -1;
134 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
135 /// vector_shuffle(X,undef,mask) by the dag combiner.
136 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
137 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true, *CurDAG));
139 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
140 (vector_shuffle node:$lhs, node:$rhs), [{
141 return PPC::isVSLDOIShuffleMask(N, true, *CurDAG) != -1;
142 }], VSLDOI_unary_get_imm>;
145 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
146 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
147 return getI32Imm(PPC::getVSPLTImmediate(N, 1, *CurDAG));
149 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
150 (vector_shuffle node:$lhs, node:$rhs), [{
151 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
153 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
154 return getI32Imm(PPC::getVSPLTImmediate(N, 2, *CurDAG));
156 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
157 (vector_shuffle node:$lhs, node:$rhs), [{
158 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
160 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
161 return getI32Imm(PPC::getVSPLTImmediate(N, 4, *CurDAG));
163 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
164 (vector_shuffle node:$lhs, node:$rhs), [{
165 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
169 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm.
170 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{
171 return PPC::get_VSPLTI_elt(N, 1, *CurDAG);
173 def vecspltisb : PatLeaf<(build_vector), [{
174 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0;
175 }], VSPLTISB_get_imm>;
177 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm.
178 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{
179 return PPC::get_VSPLTI_elt(N, 2, *CurDAG);
181 def vecspltish : PatLeaf<(build_vector), [{
182 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0;
183 }], VSPLTISH_get_imm>;
185 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm.
186 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{
187 return PPC::get_VSPLTI_elt(N, 4, *CurDAG);
189 def vecspltisw : PatLeaf<(build_vector), [{
190 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0;
191 }], VSPLTISW_get_imm>;
193 //===----------------------------------------------------------------------===//
194 // Helpers for defining instructions that directly correspond to intrinsics.
196 // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
197 class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
198 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
199 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
200 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
202 // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
203 // inputs doesn't match the type of the output.
204 class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
206 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
207 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
208 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
210 // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
211 // input types and an output type.
212 class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
213 ValueType In1Ty, ValueType In2Ty>
214 : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
215 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
217 (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
219 // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
220 class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
221 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
222 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
223 [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
225 // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
226 // inputs doesn't match the type of the output.
227 class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
229 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
230 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
231 [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
233 // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
234 // input types and an output type.
235 class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
236 ValueType In1Ty, ValueType In2Ty>
237 : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
238 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
239 [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
241 // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
242 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
243 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
244 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
245 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
247 // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
248 // inputs doesn't match the type of the output.
249 class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
251 : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
252 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
253 [(set OutTy:$vD, (IntID InTy:$vB))]>;
255 //===----------------------------------------------------------------------===//
256 // Instruction Definitions.
258 def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
259 let Predicates = [HasAltivec] in {
261 let isCodeGenOnly = 1 in {
262 def DSS : DSS_Form<822, (outs),
263 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
264 "dss $STRM", IIC_LdStLoad /*FIXME*/, []>,
265 Deprecated<DeprecatedDST>;
266 def DSSALL : DSS_Form<822, (outs),
267 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
268 "dssall", IIC_LdStLoad /*FIXME*/, []>,
269 Deprecated<DeprecatedDST>;
270 def DST : DSS_Form<342, (outs),
271 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
272 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
273 Deprecated<DeprecatedDST>;
274 def DSTT : DSS_Form<342, (outs),
275 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
276 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
277 Deprecated<DeprecatedDST>;
278 def DSTST : DSS_Form<374, (outs),
279 (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
280 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
281 Deprecated<DeprecatedDST>;
282 def DSTSTT : DSS_Form<374, (outs),
283 (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
284 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
285 Deprecated<DeprecatedDST>;
287 def DST64 : DSS_Form<342, (outs),
288 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
289 "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
290 Deprecated<DeprecatedDST>;
291 def DSTT64 : DSS_Form<342, (outs),
292 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
293 "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
294 Deprecated<DeprecatedDST>;
295 def DSTST64 : DSS_Form<374, (outs),
296 (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
297 "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
298 Deprecated<DeprecatedDST>;
299 def DSTSTT64 : DSS_Form<374, (outs),
300 (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
301 "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
302 Deprecated<DeprecatedDST>;
305 def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
306 "mfvscr $vD", IIC_LdStStore,
307 [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
308 def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
309 "mtvscr $vB", IIC_LdStLoad,
310 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
312 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
313 def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
314 "lvebx $vD, $src", IIC_LdStLoad,
315 [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
316 def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
317 "lvehx $vD, $src", IIC_LdStLoad,
318 [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
319 def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
320 "lvewx $vD, $src", IIC_LdStLoad,
321 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
322 def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
323 "lvx $vD, $src", IIC_LdStLoad,
324 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
325 def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
326 "lvxl $vD, $src", IIC_LdStLoad,
327 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
330 def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
331 "lvsl $vD, $src", IIC_LdStLoad,
332 [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
334 def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
335 "lvsr $vD, $src", IIC_LdStLoad,
336 [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
339 let PPC970_Unit = 2 in { // Stores.
340 def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
341 "stvebx $rS, $dst", IIC_LdStStore,
342 [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
343 def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
344 "stvehx $rS, $dst", IIC_LdStStore,
345 [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
346 def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
347 "stvewx $rS, $dst", IIC_LdStStore,
348 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
349 def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
350 "stvx $rS, $dst", IIC_LdStStore,
351 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
352 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
353 "stvxl $rS, $dst", IIC_LdStStore,
354 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
357 let PPC970_Unit = 5 in { // VALU Operations.
358 // VA-Form instructions. 3-input AltiVec ops.
359 let isCommutable = 1 in {
360 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
361 "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
363 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
365 // FIXME: The fma+fneg pattern won't match because fneg is not legal.
366 def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
367 "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
368 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
369 (fneg v4f32:$vB))))]>;
371 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
372 def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs,
374 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
377 def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
378 v4i32, v4i32, v16i8>;
379 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
382 def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
383 "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
385 (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
387 // VX-Form instructions. AltiVec arithmetic ops.
388 let isCommutable = 1 in {
389 def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
390 "vaddfp $vD, $vA, $vB", IIC_VecFP,
391 [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
393 def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
394 "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
395 [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
396 def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
397 "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
398 [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
399 def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
400 "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
401 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
403 def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
404 def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>;
405 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
406 def VADDSWS : VX1_Int_Ty<896, "vaddsws", int_ppc_altivec_vaddsws, v4i32>;
407 def VADDUBS : VX1_Int_Ty<512, "vaddubs", int_ppc_altivec_vaddubs, v16i8>;
408 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
409 def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
412 let isCommutable = 1 in
413 def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
414 "vand $vD, $vA, $vB", IIC_VecFP,
415 [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
416 def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
417 "vandc $vD, $vA, $vB", IIC_VecFP,
418 [(set v4i32:$vD, (and v4i32:$vA,
419 (vnot_ppc v4i32:$vB)))]>;
421 def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
422 "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
424 (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
425 def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
426 "vcfux $vD, $vB, $UIMM", IIC_VecFP,
428 (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
429 def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
430 "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
432 (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
433 def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
434 "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
436 (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
438 // Defines with the UIM field set to 0 for floating-point
439 // to integer (fp_to_sint/fp_to_uint) conversions and integer
440 // to floating-point (sint_to_fp/uint_to_fp) conversions.
441 let isCodeGenOnly = 1, VA = 0 in {
442 def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
443 "vcfsx $vD, $vB, 0", IIC_VecFP,
445 (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
446 def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
447 "vctuxs $vD, $vB, 0", IIC_VecFP,
449 (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
450 def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
451 "vcfux $vD, $vB, 0", IIC_VecFP,
453 (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
454 def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
455 "vctsxs $vD, $vB, 0", IIC_VecFP,
457 (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
459 def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>;
460 def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>;
462 let isCommutable = 1 in {
463 def VAVGSB : VX1_Int_Ty<1282, "vavgsb", int_ppc_altivec_vavgsb, v16i8>;
464 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
465 def VAVGSW : VX1_Int_Ty<1410, "vavgsw", int_ppc_altivec_vavgsw, v4i32>;
466 def VAVGUB : VX1_Int_Ty<1026, "vavgub", int_ppc_altivec_vavgub, v16i8>;
467 def VAVGUH : VX1_Int_Ty<1090, "vavguh", int_ppc_altivec_vavguh, v8i16>;
468 def VAVGUW : VX1_Int_Ty<1154, "vavguw", int_ppc_altivec_vavguw, v4i32>;
470 def VMAXFP : VX1_Int_Ty<1034, "vmaxfp", int_ppc_altivec_vmaxfp, v4f32>;
471 def VMAXSB : VX1_Int_Ty< 258, "vmaxsb", int_ppc_altivec_vmaxsb, v16i8>;
472 def VMAXSH : VX1_Int_Ty< 322, "vmaxsh", int_ppc_altivec_vmaxsh, v8i16>;
473 def VMAXSW : VX1_Int_Ty< 386, "vmaxsw", int_ppc_altivec_vmaxsw, v4i32>;
474 def VMAXUB : VX1_Int_Ty< 2, "vmaxub", int_ppc_altivec_vmaxub, v16i8>;
475 def VMAXUH : VX1_Int_Ty< 66, "vmaxuh", int_ppc_altivec_vmaxuh, v8i16>;
476 def VMAXUW : VX1_Int_Ty< 130, "vmaxuw", int_ppc_altivec_vmaxuw, v4i32>;
477 def VMINFP : VX1_Int_Ty<1098, "vminfp", int_ppc_altivec_vminfp, v4f32>;
478 def VMINSB : VX1_Int_Ty< 770, "vminsb", int_ppc_altivec_vminsb, v16i8>;
479 def VMINSH : VX1_Int_Ty< 834, "vminsh", int_ppc_altivec_vminsh, v8i16>;
480 def VMINSW : VX1_Int_Ty< 898, "vminsw", int_ppc_altivec_vminsw, v4i32>;
481 def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
482 def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
483 def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
486 def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
487 "vmrghb $vD, $vA, $vB", IIC_VecFP,
488 [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
489 def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
490 "vmrghh $vD, $vA, $vB", IIC_VecFP,
491 [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
492 def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
493 "vmrghw $vD, $vA, $vB", IIC_VecFP,
494 [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
495 def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
496 "vmrglb $vD, $vA, $vB", IIC_VecFP,
497 [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
498 def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
499 "vmrglh $vD, $vA, $vB", IIC_VecFP,
500 [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
501 def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
502 "vmrglw $vD, $vA, $vB", IIC_VecFP,
503 [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
505 def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
506 v4i32, v16i8, v4i32>;
507 def VMSUMSHM : VA1a_Int_Ty3<40, "vmsumshm", int_ppc_altivec_vmsumshm,
508 v4i32, v8i16, v4i32>;
509 def VMSUMSHS : VA1a_Int_Ty3<41, "vmsumshs", int_ppc_altivec_vmsumshs,
510 v4i32, v8i16, v4i32>;
511 def VMSUMUBM : VA1a_Int_Ty3<36, "vmsumubm", int_ppc_altivec_vmsumubm,
512 v4i32, v16i8, v4i32>;
513 def VMSUMUHM : VA1a_Int_Ty3<38, "vmsumuhm", int_ppc_altivec_vmsumuhm,
514 v4i32, v8i16, v4i32>;
515 def VMSUMUHS : VA1a_Int_Ty3<39, "vmsumuhs", int_ppc_altivec_vmsumuhs,
516 v4i32, v8i16, v4i32>;
518 let isCommutable = 1 in {
519 def VMULESB : VX1_Int_Ty2<776, "vmulesb", int_ppc_altivec_vmulesb,
521 def VMULESH : VX1_Int_Ty2<840, "vmulesh", int_ppc_altivec_vmulesh,
523 def VMULEUB : VX1_Int_Ty2<520, "vmuleub", int_ppc_altivec_vmuleub,
525 def VMULEUH : VX1_Int_Ty2<584, "vmuleuh", int_ppc_altivec_vmuleuh,
527 def VMULOSB : VX1_Int_Ty2<264, "vmulosb", int_ppc_altivec_vmulosb,
529 def VMULOSH : VX1_Int_Ty2<328, "vmulosh", int_ppc_altivec_vmulosh,
531 def VMULOUB : VX1_Int_Ty2< 8, "vmuloub", int_ppc_altivec_vmuloub,
533 def VMULOUH : VX1_Int_Ty2< 72, "vmulouh", int_ppc_altivec_vmulouh,
537 def VREFP : VX2_Int_SP<266, "vrefp", int_ppc_altivec_vrefp>;
538 def VRFIM : VX2_Int_SP<714, "vrfim", int_ppc_altivec_vrfim>;
539 def VRFIN : VX2_Int_SP<522, "vrfin", int_ppc_altivec_vrfin>;
540 def VRFIP : VX2_Int_SP<650, "vrfip", int_ppc_altivec_vrfip>;
541 def VRFIZ : VX2_Int_SP<586, "vrfiz", int_ppc_altivec_vrfiz>;
542 def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
544 def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
546 def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
547 "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
548 [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
549 def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
550 "vsububm $vD, $vA, $vB", IIC_VecGeneral,
551 [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
552 def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
553 "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
554 [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
555 def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
556 "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
557 [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
559 def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
560 def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>;
561 def VSUBSWS : VX1_Int_Ty<1920, "vsubsws" , int_ppc_altivec_vsubsws, v4i32>;
562 def VSUBUBS : VX1_Int_Ty<1536, "vsububs" , int_ppc_altivec_vsububs, v16i8>;
563 def VSUBUHS : VX1_Int_Ty<1600, "vsubuhs" , int_ppc_altivec_vsubuhs, v8i16>;
564 def VSUBUWS : VX1_Int_Ty<1664, "vsubuws" , int_ppc_altivec_vsubuws, v4i32>;
566 def VSUMSWS : VX1_Int_Ty<1928, "vsumsws" , int_ppc_altivec_vsumsws, v4i32>;
567 def VSUM2SWS: VX1_Int_Ty<1672, "vsum2sws", int_ppc_altivec_vsum2sws, v4i32>;
569 def VSUM4SBS: VX1_Int_Ty3<1800, "vsum4sbs", int_ppc_altivec_vsum4sbs,
570 v4i32, v16i8, v4i32>;
571 def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
572 v4i32, v8i16, v4i32>;
573 def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
574 v4i32, v16i8, v4i32>;
576 def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
577 "vnor $vD, $vA, $vB", IIC_VecFP,
578 [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
580 let isCommutable = 1 in {
581 def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
582 "vor $vD, $vA, $vB", IIC_VecFP,
583 [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
584 def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
585 "vxor $vD, $vA, $vB", IIC_VecFP,
586 [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
589 def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
590 def VRLH : VX1_Int_Ty< 68, "vrlh", int_ppc_altivec_vrlh, v8i16>;
591 def VRLW : VX1_Int_Ty< 132, "vrlw", int_ppc_altivec_vrlw, v4i32>;
593 def VSL : VX1_Int_Ty< 452, "vsl" , int_ppc_altivec_vsl, v4i32 >;
594 def VSLO : VX1_Int_Ty<1036, "vslo", int_ppc_altivec_vslo, v4i32>;
596 def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
597 def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
598 def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
600 def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
601 "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
603 (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
604 def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
605 "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
607 (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
608 def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
609 "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
611 (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
613 def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>;
614 def VSRO : VX1_Int_Ty<1100, "vsro" , int_ppc_altivec_vsro, v4i32>;
616 def VSRAB : VX1_Int_Ty< 772, "vsrab", int_ppc_altivec_vsrab, v16i8>;
617 def VSRAH : VX1_Int_Ty< 836, "vsrah", int_ppc_altivec_vsrah, v8i16>;
618 def VSRAW : VX1_Int_Ty< 900, "vsraw", int_ppc_altivec_vsraw, v4i32>;
619 def VSRB : VX1_Int_Ty< 516, "vsrb" , int_ppc_altivec_vsrb , v16i8>;
620 def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
621 def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
624 def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
625 "vspltisb $vD, $SIMM", IIC_VecPerm,
626 [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
627 def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
628 "vspltish $vD, $SIMM", IIC_VecPerm,
629 [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
630 def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
631 "vspltisw $vD, $SIMM", IIC_VecPerm,
632 [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
635 def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx,
637 def VPKSHSS : VX1_Int_Ty2<398, "vpkshss", int_ppc_altivec_vpkshss,
639 def VPKSHUS : VX1_Int_Ty2<270, "vpkshus", int_ppc_altivec_vpkshus,
641 def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
643 def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
645 def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
646 "vpkuhum $vD, $vA, $vB", IIC_VecFP,
648 (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
649 def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
651 def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
652 "vpkuwum $vD, $vA, $vB", IIC_VecFP,
654 (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
655 def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
659 def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx,
661 def VUPKHSB : VX2_Int_Ty2<526, "vupkhsb", int_ppc_altivec_vupkhsb,
663 def VUPKHSH : VX2_Int_Ty2<590, "vupkhsh", int_ppc_altivec_vupkhsh,
665 def VUPKLPX : VX2_Int_Ty2<974, "vupklpx", int_ppc_altivec_vupklpx,
667 def VUPKLSB : VX2_Int_Ty2<654, "vupklsb", int_ppc_altivec_vupklsb,
669 def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
673 // Altivec Comparisons.
675 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
676 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
678 [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
679 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
680 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
682 [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
687 // f32 element comparisons.0
688 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>;
689 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
690 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
691 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
692 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
693 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
694 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
695 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
697 // i8 element comparisons.
698 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>;
699 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>;
700 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
701 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
702 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
703 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
705 // i16 element comparisons.
706 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
707 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
708 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
709 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
710 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
711 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
713 // i32 element comparisons.
714 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
715 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
716 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
717 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
718 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
719 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
721 let isCodeGenOnly = 1 in {
722 def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
723 "vxor $vD, $vD, $vD", IIC_VecFP,
724 [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
725 def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
726 "vxor $vD, $vD, $vD", IIC_VecFP,
727 [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
728 def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
729 "vxor $vD, $vD, $vD", IIC_VecFP,
730 [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
733 def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
734 "vspltisw $vD, -1", IIC_VecFP,
735 [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
736 def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
737 "vspltisw $vD, -1", IIC_VecFP,
738 [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
739 def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
740 "vspltisw $vD, -1", IIC_VecFP,
741 [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
744 } // VALU Operations.
746 //===----------------------------------------------------------------------===//
747 // Additional Altivec Patterns
751 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
752 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
755 def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM),
756 (DST 0, imm:$STRM, $rA, $rB)>;
757 def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM),
758 (DSTT 1, imm:$STRM, $rA, $rB)>;
759 def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM),
760 (DSTST 0, imm:$STRM, $rA, $rB)>;
761 def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM),
762 (DSTSTT 1, imm:$STRM, $rA, $rB)>;
765 def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM),
766 (DST64 0, imm:$STRM, $rA, $rB)>;
767 def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM),
768 (DSTT64 1, imm:$STRM, $rA, $rB)>;
769 def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM),
770 (DSTST64 0, imm:$STRM, $rA, $rB)>;
771 def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM),
772 (DSTSTT64 1, imm:$STRM, $rA, $rB)>;
775 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
778 def : Pat<(store v4i32:$rS, xoaddr:$dst),
779 (STVX $rS, xoaddr:$dst)>;
782 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>;
783 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>;
784 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>;
786 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>;
787 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>;
788 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>;
790 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>;
791 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>;
792 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>;
794 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>;
795 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>;
796 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
800 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
801 def:Pat<(vsldoi_unary_shuffle:$in v16i8:$vA, undef),
802 (VSLDOI $vA, $vA, (VSLDOI_unary_get_imm $in))>;
803 def:Pat<(vpkuwum_unary_shuffle v16i8:$vA, undef),
805 def:Pat<(vpkuhum_unary_shuffle v16i8:$vA, undef),
809 def:Pat<(vmrglb_unary_shuffle v16i8:$vA, undef),
811 def:Pat<(vmrglh_unary_shuffle v16i8:$vA, undef),
813 def:Pat<(vmrglw_unary_shuffle v16i8:$vA, undef),
815 def:Pat<(vmrghb_unary_shuffle v16i8:$vA, undef),
817 def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
819 def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
822 // Match vmrg*(y,x), i.e., swapped operands. These fragments
823 // are matched for little-endian, where the inputs must be
824 // swapped for correct semantics.
825 def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
827 def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
829 def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
831 def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
833 def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
835 def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
838 // Logical Operations
839 def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
841 def : Pat<(vnot_ppc (or v4i32:$A, v4i32:$B)),
843 def : Pat<(and v4i32:$A, (vnot_ppc v4i32:$B)),
846 def : Pat<(fmul v4f32:$vA, v4f32:$vB),
848 (v4i32 (VSLW (V_SETALLONES), (V_SETALLONES))))>;
850 // Fused multiply add and multiply sub for packed float. These are represented
851 // separately from the real instructions above, for operations that must have
852 // the additional precision, such as Newton-Rhapson (used by divide, sqrt)
853 def : Pat<(PPCvmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
854 (VMADDFP $A, $B, $C)>;
855 def : Pat<(PPCvnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
856 (VNMSUBFP $A, $B, $C)>;
858 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
859 (VMADDFP $A, $B, $C)>;
860 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
861 (VNMSUBFP $A, $B, $C)>;
863 def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC),
864 (VPERM $vA, $vB, $vC)>;
866 def : Pat<(PPCfre v4f32:$A), (VREFP $A)>;
867 def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>;
870 def : Pat<(v16i8 (shl v16i8:$vA, v16i8:$vB)),
871 (v16i8 (VSLB $vA, $vB))>;
872 def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),
873 (v8i16 (VSLH $vA, $vB))>;
874 def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),
875 (v4i32 (VSLW $vA, $vB))>;
877 def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),
878 (v16i8 (VSRB $vA, $vB))>;
879 def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),
880 (v8i16 (VSRH $vA, $vB))>;
881 def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),
882 (v4i32 (VSRW $vA, $vB))>;
884 def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),
885 (v16i8 (VSRAB $vA, $vB))>;
886 def : Pat<(v8i16 (sra v8i16:$vA, v8i16:$vB)),
887 (v8i16 (VSRAH $vA, $vB))>;
888 def : Pat<(v4i32 (sra v4i32:$vA, v4i32:$vB)),
889 (v4i32 (VSRAW $vA, $vB))>;
891 // Float to integer and integer to float conversions
892 def : Pat<(v4i32 (fp_to_sint v4f32:$vA)),
894 def : Pat<(v4i32 (fp_to_uint v4f32:$vA)),
896 def : Pat<(v4f32 (sint_to_fp v4i32:$vA)),
898 def : Pat<(v4f32 (uint_to_fp v4i32:$vA)),
901 // Floating-point rounding
902 def : Pat<(v4f32 (ffloor v4f32:$vA)),
904 def : Pat<(v4f32 (fceil v4f32:$vA)),
906 def : Pat<(v4f32 (ftrunc v4f32:$vA)),
908 def : Pat<(v4f32 (fnearbyint v4f32:$vA)),