1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isReturn = 1, Uses = [LR8, RM] in
85 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
86 [(retflag)]>, Requires<[In64BitMode]>;
87 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
88 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
90 Requires<[In64BitMode]>;
91 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
92 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
94 Requires<[In64BitMode]>;
96 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 12, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
99 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
100 "bcctr 4, $bi, 0", IIC_BrB, []>,
101 Requires<[In64BitMode]>;
106 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
109 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
110 let Defs = [CTR8], Uses = [CTR8] in {
111 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
113 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
117 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
118 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
119 "bdzlr", IIC_BrB, []>;
120 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
121 "bdnzlr", IIC_BrB, []>;
127 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
128 // Convenient aliases for call instructions
130 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
131 "bl $func", IIC_BrB, []>; // See Pat patterns below.
133 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
134 "bl $func", IIC_BrB, []>;
136 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
137 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
139 let Uses = [RM], isCodeGenOnly = 1 in {
140 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
141 (outs), (ins calltarget:$func),
142 "bl $func\n\tnop", IIC_BrB, []>;
144 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
145 (outs), (ins tlscall:$func),
146 "bl $func\n\tnop", IIC_BrB, []>;
148 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
149 (outs), (ins abscalltarget:$func),
150 "bla $func\n\tnop", IIC_BrB,
151 [(PPCcall_nop (i64 imm:$func))]>;
153 let Uses = [CTR8, RM] in {
154 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
155 "bctrl", IIC_BrB, [(PPCbctrl)]>,
156 Requires<[In64BitMode]>;
158 let isCodeGenOnly = 1 in {
159 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
160 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
162 Requires<[In64BitMode]>;
164 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 12, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
167 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
168 "bcctrl 4, $bi, 0", IIC_BrB, []>,
169 Requires<[In64BitMode]>;
174 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
175 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
176 def BCTRL8_LDinto_toc :
177 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
179 "bctrl\n\tld 2, $src", IIC_BrB,
180 [(PPCbctrl_load_toc ixaddr:$src)]>,
181 Requires<[In64BitMode]>;
184 } // Interpretation64Bit
186 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
187 // previous definition must be marked as CodeGen only to prevent decoding
189 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
190 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
191 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
192 "bl $func", IIC_BrB, []>;
195 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
196 (BL8 tglobaladdr:$dst)>;
197 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
198 (BL8_NOP tglobaladdr:$dst)>;
200 def : Pat<(PPCcall (i64 texternalsym:$dst)),
201 (BL8 texternalsym:$dst)>;
202 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
203 (BL8_NOP texternalsym:$dst)>;
205 def : Pat<(PPCcall_nop_tls texternalsym:$func, tglobaltlsaddr:$sym),
206 (BL8_NOP_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
209 let usesCustomInserter = 1 in {
210 let Defs = [CR0] in {
211 def ATOMIC_LOAD_ADD_I64 : Pseudo<
212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
213 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
214 def ATOMIC_LOAD_SUB_I64 : Pseudo<
215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
216 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
217 def ATOMIC_LOAD_OR_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
219 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
220 def ATOMIC_LOAD_XOR_I64 : Pseudo<
221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
222 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
223 def ATOMIC_LOAD_AND_I64 : Pseudo<
224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
225 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
226 def ATOMIC_LOAD_NAND_I64 : Pseudo<
227 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
228 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
230 def ATOMIC_CMP_SWAP_I64 : Pseudo<
231 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
232 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
234 def ATOMIC_SWAP_I64 : Pseudo<
235 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
236 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
240 // Instructions to support atomic operations
241 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
242 "ldarx $rD, $ptr", IIC_LdStLDARX,
243 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
246 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
247 "stdcx. $rS, $dst", IIC_LdStSTDCX,
248 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
251 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
252 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
253 def TCRETURNdi8 :Pseudo< (outs),
254 (ins calltarget:$dst, i32imm:$offset),
255 "#TC_RETURNd8 $dst $offset",
258 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
259 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
260 "#TC_RETURNa8 $func $offset",
261 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
263 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
264 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
265 "#TC_RETURNr8 $dst $offset",
268 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
269 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
270 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
272 Requires<[In64BitMode]>;
274 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
275 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
276 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
280 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
281 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
282 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
285 } // Interpretation64Bit
287 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
288 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
290 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
291 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
293 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
294 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
297 // 64-bit CR instructions
298 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
299 let hasSideEffects = 0 in {
300 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
301 "mtocrf $FXM, $ST", IIC_BrMCRX>,
302 PPC970_DGroup_First, PPC970_Unit_CRU;
304 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
305 "mtcrf $FXM, $rS", IIC_BrMCRX>,
306 PPC970_MicroCode, PPC970_Unit_CRU;
308 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
309 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
310 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
311 PPC970_DGroup_First, PPC970_Unit_CRU;
313 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
314 "mfcr $rT", IIC_SprMFCR>,
315 PPC970_MicroCode, PPC970_Unit_CRU;
316 } // hasSideEffects = 0
318 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
320 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
322 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
323 Requires<[In64BitMode]>;
324 let isTerminator = 1 in
325 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
326 "#EH_SJLJ_LONGJMP64",
327 [(PPCeh_sjlj_longjmp addr:$buf)]>,
328 Requires<[In64BitMode]>;
331 //===----------------------------------------------------------------------===//
332 // 64-bit SPR manipulation instrs.
334 let Uses = [CTR8] in {
335 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
336 "mfctr $rT", IIC_SprMFSPR>,
337 PPC970_DGroup_First, PPC970_Unit_FXU;
339 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
340 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
341 "mtctr $rS", IIC_SprMTSPR>,
342 PPC970_DGroup_First, PPC970_Unit_FXU;
344 let hasSideEffects = 1, Defs = [CTR8] in {
345 let Pattern = [(int_ppc_mtctr i64:$rS)] in
346 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
347 "mtctr $rS", IIC_SprMTSPR>,
348 PPC970_DGroup_First, PPC970_Unit_FXU;
351 let Pattern = [(set i64:$rT, readcyclecounter)] in
352 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
353 "mfspr $rT, 268", IIC_SprMFTB>,
354 PPC970_DGroup_First, PPC970_Unit_FXU;
355 // Note that encoding mftb using mfspr is now the preferred form,
356 // and has been since at least ISA v2.03. The mftb instruction has
357 // now been phased out. Using mfspr, however, is known not to work on
360 let Defs = [X1], Uses = [X1] in
361 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
363 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
365 let Defs = [LR8] in {
366 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
367 "mtlr $rS", IIC_SprMTSPR>,
368 PPC970_DGroup_First, PPC970_Unit_FXU;
370 let Uses = [LR8] in {
371 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
372 "mflr $rT", IIC_SprMFSPR>,
373 PPC970_DGroup_First, PPC970_Unit_FXU;
375 } // Interpretation64Bit
377 //===----------------------------------------------------------------------===//
378 // Fixed point instructions.
381 let PPC970_Unit = 1 in { // FXU Operations.
382 let Interpretation64Bit = 1 in {
383 let hasSideEffects = 0 in {
384 let isCodeGenOnly = 1 in {
386 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
387 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
388 "li $rD, $imm", IIC_IntSimple,
389 [(set i64:$rD, imm64SExt16:$imm)]>;
390 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
391 "lis $rD, $imm", IIC_IntSimple,
392 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
396 let isCommutable = 1 in {
397 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
398 "nand", "$rA, $rS, $rB", IIC_IntSimple,
399 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
400 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
401 "and", "$rA, $rS, $rB", IIC_IntSimple,
402 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
404 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
405 "andc", "$rA, $rS, $rB", IIC_IntSimple,
406 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
407 let isCommutable = 1 in {
408 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
409 "or", "$rA, $rS, $rB", IIC_IntSimple,
410 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
411 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
412 "nor", "$rA, $rS, $rB", IIC_IntSimple,
413 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
415 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
416 "orc", "$rA, $rS, $rB", IIC_IntSimple,
417 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
418 let isCommutable = 1 in {
419 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
420 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
421 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
422 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
423 "xor", "$rA, $rS, $rB", IIC_IntSimple,
424 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
425 } // let isCommutable = 1
427 // Logical ops with immediate.
428 let Defs = [CR0] in {
429 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
430 "andi. $dst, $src1, $src2", IIC_IntGeneral,
431 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
433 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
434 "andis. $dst, $src1, $src2", IIC_IntGeneral,
435 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
438 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
439 "ori $dst, $src1, $src2", IIC_IntSimple,
440 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
441 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
442 "oris $dst, $src1, $src2", IIC_IntSimple,
443 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
444 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
445 "xori $dst, $src1, $src2", IIC_IntSimple,
446 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
447 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
448 "xoris $dst, $src1, $src2", IIC_IntSimple,
449 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
451 let isCommutable = 1 in
452 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
453 "add", "$rT, $rA, $rB", IIC_IntSimple,
454 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
455 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
456 // initial-exec thread-local storage model.
457 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
458 "add $rT, $rA, $rB", IIC_IntSimple,
459 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
461 let isCommutable = 1 in
462 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
463 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
464 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
465 PPC970_DGroup_Cracked;
467 let Defs = [CARRY] in
468 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
469 "addic $rD, $rA, $imm", IIC_IntGeneral,
470 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
471 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
472 "addi $rD, $rA, $imm", IIC_IntSimple,
473 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
474 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
475 "addis $rD, $rA, $imm", IIC_IntSimple,
476 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
478 let Defs = [CARRY] in {
479 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
480 "subfic $rD, $rA, $imm", IIC_IntGeneral,
481 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
482 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
483 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
484 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
485 PPC970_DGroup_Cracked;
487 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
488 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
489 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
490 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
491 "neg", "$rT, $rA", IIC_IntSimple,
492 [(set i64:$rT, (ineg i64:$rA))]>;
493 let Uses = [CARRY] in {
494 let isCommutable = 1 in
495 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
496 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
497 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
498 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
499 "addme", "$rT, $rA", IIC_IntGeneral,
500 [(set i64:$rT, (adde i64:$rA, -1))]>;
501 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
502 "addze", "$rT, $rA", IIC_IntGeneral,
503 [(set i64:$rT, (adde i64:$rA, 0))]>;
504 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
505 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
506 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
507 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
508 "subfme", "$rT, $rA", IIC_IntGeneral,
509 [(set i64:$rT, (sube -1, i64:$rA))]>;
510 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
511 "subfze", "$rT, $rA", IIC_IntGeneral,
512 [(set i64:$rT, (sube 0, i64:$rA))]>;
516 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
517 // previous definition must be marked as CodeGen only to prevent decoding
519 let isAsmParserOnly = 1 in
520 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
521 "add $rT, $rA, $rB", IIC_IntSimple, []>;
523 let isCommutable = 1 in {
524 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
525 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
526 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
527 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
528 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
529 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
532 } // Interpretation64Bit
534 let isCompare = 1, hasSideEffects = 0 in {
535 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
536 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
537 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
538 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
539 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
540 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
541 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
542 "cmpldi $dst, $src1, $src2",
543 IIC_IntCompare>, isPPC64;
546 let hasSideEffects = 0 in {
547 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
548 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
549 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
550 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
551 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
552 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
553 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
554 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
555 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
557 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
558 defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS),
559 "cntlzw", "$rA, $rS", IIC_IntGeneral, []>;
561 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
562 "extsb", "$rA, $rS", IIC_IntSimple,
563 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
564 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
565 "extsh", "$rA, $rS", IIC_IntSimple,
566 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
568 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
569 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
570 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
571 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
572 } // Interpretation64Bit
575 let isCodeGenOnly = 1 in {
576 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
577 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
578 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
579 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
580 } // isCodeGenOnly for fast-isel
582 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
583 "extsw", "$rA, $rS", IIC_IntSimple,
584 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
585 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
586 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
587 "extsw", "$rA, $rS", IIC_IntSimple,
588 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
590 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
591 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
592 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
593 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
594 "cntlzd", "$rA, $rS", IIC_IntGeneral,
595 [(set i64:$rA, (ctlz i64:$rS))]>;
596 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
597 "popcntd $rA, $rS", IIC_IntGeneral,
598 [(set i64:$rA, (ctpop i64:$rS))]>;
600 let isCodeGenOnly = 1, isCommutable = 1 in
601 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
602 "cmpb $rA, $rS, $rB", IIC_IntGeneral,
603 [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
605 // popcntw also does a population count on the high 32 bits (storing the
606 // results in the high 32-bits of the output). We'll ignore that here (which is
607 // safe because we never separately use the high part of the 64-bit registers).
608 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
609 "popcntw $rA, $rS", IIC_IntGeneral,
610 [(set i32:$rA, (ctpop i32:$rS))]>;
612 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
613 "divd", "$rT, $rA, $rB", IIC_IntDivD,
614 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
615 PPC970_DGroup_First, PPC970_DGroup_Cracked;
616 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
617 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
618 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
619 PPC970_DGroup_First, PPC970_DGroup_Cracked;
620 let isCommutable = 1 in
621 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
622 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
623 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
624 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
625 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
626 "mulli $rD, $rA, $imm", IIC_IntMulLI,
627 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
630 let hasSideEffects = 0 in {
631 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
632 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
633 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
634 []>, isPPC64, RegConstraint<"$rSi = $rA">,
637 // Rotate instructions.
638 defm RLDCL : MDSForm_1r<30, 8,
639 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
640 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
642 defm RLDCR : MDSForm_1r<30, 9,
643 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
644 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
646 defm RLDICL : MDForm_1r<30, 0,
647 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
648 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
651 let isCodeGenOnly = 1 in
652 def RLDICL_32_64 : MDForm_1<30, 0,
654 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
655 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
658 defm RLDICR : MDForm_1r<30, 1,
659 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
660 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
662 defm RLDIC : MDForm_1r<30, 2,
663 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
664 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
667 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
668 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
669 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
670 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
673 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
674 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
675 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
678 // RLWIMI can be commuted if the rotate amount is zero.
679 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
680 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
681 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
682 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
683 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
684 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
687 def ISEL8 : AForm_4<31, 15,
688 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
689 "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
691 } // Interpretation64Bit
692 } // hasSideEffects = 0
693 } // End FXU Operations.
696 //===----------------------------------------------------------------------===//
697 // Load/Store instructions.
701 // Sign extending loads.
702 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
703 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
704 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
705 "lha $rD, $src", IIC_LdStLHA,
706 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
707 PPC970_DGroup_Cracked;
708 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
709 "lwa $rD, $src", IIC_LdStLWA,
711 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
712 PPC970_DGroup_Cracked;
713 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
714 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
715 "lhax $rD, $src", IIC_LdStLHA,
716 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
717 PPC970_DGroup_Cracked;
718 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
719 "lwax $rD, $src", IIC_LdStLHA,
720 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
721 PPC970_DGroup_Cracked;
723 let isCodeGenOnly = 1, mayLoad = 1 in {
724 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
725 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
726 PPC970_DGroup_Cracked;
727 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
728 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
729 PPC970_DGroup_Cracked;
730 } // end fast-isel isCodeGenOnly
733 let mayLoad = 1, hasSideEffects = 0 in {
734 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
735 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
737 "lhau $rD, $addr", IIC_LdStLHAU,
738 []>, RegConstraint<"$addr.reg = $ea_result">,
739 NoEncode<"$ea_result">;
742 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
743 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
745 "lhaux $rD, $addr", IIC_LdStLHAUX,
746 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
747 NoEncode<"$ea_result">;
748 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
750 "lwaux $rD, $addr", IIC_LdStLHAUX,
751 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
752 NoEncode<"$ea_result">, isPPC64;
756 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
757 // Zero extending loads.
758 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
759 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
760 "lbz $rD, $src", IIC_LdStLoad,
761 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
762 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
763 "lhz $rD, $src", IIC_LdStLoad,
764 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
765 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
766 "lwz $rD, $src", IIC_LdStLoad,
767 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
769 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
770 "lbzx $rD, $src", IIC_LdStLoad,
771 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
772 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
773 "lhzx $rD, $src", IIC_LdStLoad,
774 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
775 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
776 "lwzx $rD, $src", IIC_LdStLoad,
777 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
781 let mayLoad = 1, hasSideEffects = 0 in {
782 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
783 "lbzu $rD, $addr", IIC_LdStLoadUpd,
784 []>, RegConstraint<"$addr.reg = $ea_result">,
785 NoEncode<"$ea_result">;
786 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
787 "lhzu $rD, $addr", IIC_LdStLoadUpd,
788 []>, RegConstraint<"$addr.reg = $ea_result">,
789 NoEncode<"$ea_result">;
790 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
791 "lwzu $rD, $addr", IIC_LdStLoadUpd,
792 []>, RegConstraint<"$addr.reg = $ea_result">,
793 NoEncode<"$ea_result">;
795 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
797 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
798 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
799 NoEncode<"$ea_result">;
800 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
802 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
803 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
804 NoEncode<"$ea_result">;
805 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
807 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
808 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
809 NoEncode<"$ea_result">;
812 } // Interpretation64Bit
815 // Full 8-byte loads.
816 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
817 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
818 "ld $rD, $src", IIC_LdStLD,
819 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
820 // The following four definitions are selected for small code model only.
821 // Otherwise, we need to create two instructions to form a 32-bit offset,
822 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
823 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
826 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
827 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
830 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
831 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
834 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
835 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
838 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
840 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
841 "ldx $rD, $src", IIC_LdStLD,
842 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
843 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
844 "ldbrx $rD, $src", IIC_LdStLoad,
845 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
847 let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
848 def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
849 "lhbrx $rD, $src", IIC_LdStLoad, []>;
850 def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
851 "lwbrx $rD, $src", IIC_LdStLoad, []>;
854 let mayLoad = 1, hasSideEffects = 0 in {
855 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
856 "ldu $rD, $addr", IIC_LdStLDU,
857 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
858 NoEncode<"$ea_result">;
860 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
862 "ldux $rD, $addr", IIC_LdStLDUX,
863 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
864 NoEncode<"$ea_result">, isPPC64;
868 // Support for medium and large code model.
869 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
872 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
874 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
877 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
878 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
881 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
883 // Support for thread-local storage.
884 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
887 (PPCaddisGotTprelHA i64:$reg,
888 tglobaltlsaddr:$disp))]>,
890 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
893 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
895 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
896 (ADD8TLS $in, tglobaltlsaddr:$g)>;
897 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
900 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
902 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
905 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
907 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
910 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
912 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
915 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
917 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
920 (PPCaddisDtprelHA i64:$reg,
921 tglobaltlsaddr:$disp))]>,
923 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
926 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
929 let PPC970_Unit = 2 in {
930 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
931 // Truncating stores.
932 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
933 "stb $rS, $src", IIC_LdStStore,
934 [(truncstorei8 i64:$rS, iaddr:$src)]>;
935 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
936 "sth $rS, $src", IIC_LdStStore,
937 [(truncstorei16 i64:$rS, iaddr:$src)]>;
938 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
939 "stw $rS, $src", IIC_LdStStore,
940 [(truncstorei32 i64:$rS, iaddr:$src)]>;
941 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
942 "stbx $rS, $dst", IIC_LdStStore,
943 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
944 PPC970_DGroup_Cracked;
945 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
946 "sthx $rS, $dst", IIC_LdStStore,
947 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
948 PPC970_DGroup_Cracked;
949 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
950 "stwx $rS, $dst", IIC_LdStStore,
951 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
952 PPC970_DGroup_Cracked;
953 } // Interpretation64Bit
955 // Normal 8-byte stores.
956 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
957 "std $rS, $dst", IIC_LdStSTD,
958 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
959 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
960 "stdx $rS, $dst", IIC_LdStSTD,
961 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
962 PPC970_DGroup_Cracked;
963 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
964 "stdbrx $rS, $dst", IIC_LdStStore,
965 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
966 PPC970_DGroup_Cracked;
969 // Stores with Update (pre-inc).
970 let PPC970_Unit = 2, mayStore = 1 in {
971 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
972 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
973 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
974 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
975 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
976 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
977 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
978 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
979 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
980 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
982 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
983 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
984 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
985 PPC970_DGroup_Cracked;
986 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
987 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
988 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
989 PPC970_DGroup_Cracked;
990 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
991 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
992 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
993 PPC970_DGroup_Cracked;
994 } // Interpretation64Bit
996 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
997 "stdu $rS, $dst", IIC_LdStSTDU, []>,
998 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
1001 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
1002 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
1003 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
1004 PPC970_DGroup_Cracked, isPPC64;
1007 // Patterns to match the pre-inc stores. We can't put the patterns on
1008 // the instruction definitions directly as ISel wants the address base
1009 // and offset to be separate operands, not a single complex operand.
1010 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1011 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1012 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1013 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1014 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1015 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1016 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1017 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1019 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1020 (STBUX8 $rS, $ptrreg, $ptroff)>;
1021 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1022 (STHUX8 $rS, $ptrreg, $ptroff)>;
1023 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1024 (STWUX8 $rS, $ptrreg, $ptroff)>;
1025 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1026 (STDUX $rS, $ptrreg, $ptroff)>;
1029 //===----------------------------------------------------------------------===//
1030 // Floating point instructions.
1034 let PPC970_Unit = 3, hasSideEffects = 0,
1035 Uses = [RM] in { // FPU Operations.
1036 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1037 "fcfid", "$frD, $frB", IIC_FPGeneral,
1038 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1039 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1040 "fctid", "$frD, $frB", IIC_FPGeneral,
1042 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1043 "fctidz", "$frD, $frB", IIC_FPGeneral,
1044 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1046 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1047 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1048 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1049 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1050 "fcfids", "$frD, $frB", IIC_FPGeneral,
1051 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1052 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1053 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1054 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1055 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1056 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1057 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1058 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1059 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1060 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1064 //===----------------------------------------------------------------------===//
1065 // Instruction Patterns
1068 // Extensions and truncates to/from 32-bit regs.
1069 def : Pat<(i64 (zext i32:$in)),
1070 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1072 def : Pat<(i64 (anyext i32:$in)),
1073 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1074 def : Pat<(i32 (trunc i64:$in)),
1075 (EXTRACT_SUBREG $in, sub_32)>;
1077 // Implement the 'not' operation with the NOR instruction.
1078 // (we could use the default xori pattern, but nor has lower latency on some
1079 // cores (such as the A2)).
1080 def i64not : OutPatFrag<(ops node:$in),
1082 def : Pat<(not i64:$in),
1085 // Extending loads with i64 targets.
1086 def : Pat<(zextloadi1 iaddr:$src),
1088 def : Pat<(zextloadi1 xaddr:$src),
1089 (LBZX8 xaddr:$src)>;
1090 def : Pat<(extloadi1 iaddr:$src),
1092 def : Pat<(extloadi1 xaddr:$src),
1093 (LBZX8 xaddr:$src)>;
1094 def : Pat<(extloadi8 iaddr:$src),
1096 def : Pat<(extloadi8 xaddr:$src),
1097 (LBZX8 xaddr:$src)>;
1098 def : Pat<(extloadi16 iaddr:$src),
1100 def : Pat<(extloadi16 xaddr:$src),
1101 (LHZX8 xaddr:$src)>;
1102 def : Pat<(extloadi32 iaddr:$src),
1104 def : Pat<(extloadi32 xaddr:$src),
1105 (LWZX8 xaddr:$src)>;
1107 // Standard shifts. These are represented separately from the real shifts above
1108 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1110 def : Pat<(sra i64:$rS, i32:$rB),
1112 def : Pat<(srl i64:$rS, i32:$rB),
1114 def : Pat<(shl i64:$rS, i32:$rB),
1118 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1119 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1120 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1121 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1124 def : Pat<(rotl i64:$in, i32:$sh),
1125 (RLDCL $in, $sh, 0)>;
1126 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1127 (RLDICL $in, imm:$imm, 0)>;
1129 // Hi and Lo for Darwin Global Addresses.
1130 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1131 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1132 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1133 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1134 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1135 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1136 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1137 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1138 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1139 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1140 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1141 (ADDI8 $in, tglobaltlsaddr:$g)>;
1142 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1143 (ADDIS8 $in, tglobaladdr:$g)>;
1144 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1145 (ADDIS8 $in, tconstpool:$g)>;
1146 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1147 (ADDIS8 $in, tjumptable:$g)>;
1148 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1149 (ADDIS8 $in, tblockaddress:$g)>;
1151 // Patterns to match r+r indexed loads and stores for
1152 // addresses without at least 4-byte alignment.
1153 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1154 (LWAX xoaddr:$src)>;
1155 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1157 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1158 (STDX $rS, xoaddr:$dst)>;
1160 // 64-bits atomic loads and stores
1161 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1162 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1164 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1165 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;