1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
87 Requires<[In64BitMode]>;
88 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
91 Requires<[In64BitMode]>;
93 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
94 "bcctr 12, $bi, 0", IIC_BrB, []>,
95 Requires<[In64BitMode]>;
96 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 4, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
106 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
107 let Defs = [CTR8], Uses = [CTR8] in {
108 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
110 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
114 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
115 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
116 "bdzlr", IIC_BrB, []>;
117 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 "bdnzlr", IIC_BrB, []>;
124 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
125 // Convenient aliases for call instructions
127 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
128 "bl $func", IIC_BrB, []>; // See Pat patterns below.
130 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
131 "bl $func", IIC_BrB, []>;
133 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
134 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
136 let Uses = [RM], isCodeGenOnly = 1 in {
137 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
138 (outs), (ins calltarget:$func),
139 "bl $func\n\tnop", IIC_BrB, []>;
141 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
142 (outs), (ins tlscall:$func),
143 "bl $func\n\tnop", IIC_BrB, []>;
145 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
146 (outs), (ins abscalltarget:$func),
147 "bla $func\n\tnop", IIC_BrB,
148 [(PPCcall_nop (i64 imm:$func))]>;
150 let Uses = [CTR8, RM] in {
151 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
152 "bctrl", IIC_BrB, [(PPCbctrl)]>,
153 Requires<[In64BitMode]>;
155 let isCodeGenOnly = 1 in {
156 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
157 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
159 Requires<[In64BitMode]>;
161 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
162 "bcctrl 12, $bi, 0", IIC_BrB, []>,
163 Requires<[In64BitMode]>;
164 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 4, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
171 let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1,
172 Defs = [LR8, X2], Uses = [CTR8, RM], RST = 2 in {
173 def BCTRL8_LDinto_toc :
174 XLForm_2_ext_and_DSForm_1<19, 528, 20, 0, 1, 58, 0, (outs),
176 "bctrl\n\tld 2, $src", IIC_BrB,
177 [(PPCbctrl_load_toc ixaddr:$src)]>,
178 Requires<[In64BitMode]>;
181 } // Interpretation64Bit
183 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
184 // previous definition must be marked as CodeGen only to prevent decoding
186 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
187 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
188 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
189 "bl $func", IIC_BrB, []>;
192 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
193 (BL8 tglobaladdr:$dst)>;
194 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
195 (BL8_NOP tglobaladdr:$dst)>;
197 def : Pat<(PPCcall (i64 texternalsym:$dst)),
198 (BL8 texternalsym:$dst)>;
199 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
200 (BL8_NOP texternalsym:$dst)>;
202 def : Pat<(PPCcall_nop_tls texternalsym:$func, tglobaltlsaddr:$sym),
203 (BL8_NOP_TLS texternalsym:$func, tglobaltlsaddr:$sym)>;
206 let usesCustomInserter = 1 in {
207 let Defs = [CR0] in {
208 def ATOMIC_LOAD_ADD_I64 : Pseudo<
209 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
210 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
211 def ATOMIC_LOAD_SUB_I64 : Pseudo<
212 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
213 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
214 def ATOMIC_LOAD_OR_I64 : Pseudo<
215 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
216 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
217 def ATOMIC_LOAD_XOR_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
219 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
220 def ATOMIC_LOAD_AND_I64 : Pseudo<
221 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
222 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
223 def ATOMIC_LOAD_NAND_I64 : Pseudo<
224 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
225 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
227 def ATOMIC_CMP_SWAP_I64 : Pseudo<
228 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
229 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
231 def ATOMIC_SWAP_I64 : Pseudo<
232 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
233 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
237 // Instructions to support atomic operations
238 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
239 "ldarx $rD, $ptr", IIC_LdStLDARX,
240 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
243 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
244 "stdcx. $rS, $dst", IIC_LdStSTDCX,
245 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
248 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
249 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
250 def TCRETURNdi8 :Pseudo< (outs),
251 (ins calltarget:$dst, i32imm:$offset),
252 "#TC_RETURNd8 $dst $offset",
255 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
256 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
257 "#TC_RETURNa8 $func $offset",
258 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
260 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
261 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
262 "#TC_RETURNr8 $dst $offset",
265 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
266 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
267 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
269 Requires<[In64BitMode]>;
271 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
272 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
273 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
277 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
278 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
279 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
282 } // Interpretation64Bit
284 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
285 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
287 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
288 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
290 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
291 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
294 // 64-bit CR instructions
295 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
296 let hasSideEffects = 0 in {
297 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
298 "mtocrf $FXM, $ST", IIC_BrMCRX>,
299 PPC970_DGroup_First, PPC970_Unit_CRU;
301 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
302 "mtcrf $FXM, $rS", IIC_BrMCRX>,
303 PPC970_MicroCode, PPC970_Unit_CRU;
305 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
306 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
307 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
308 PPC970_DGroup_First, PPC970_Unit_CRU;
310 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
311 "mfcr $rT", IIC_SprMFCR>,
312 PPC970_MicroCode, PPC970_Unit_CRU;
313 } // hasSideEffects = 0
315 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
317 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
319 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
320 Requires<[In64BitMode]>;
321 let isTerminator = 1 in
322 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
323 "#EH_SJLJ_LONGJMP64",
324 [(PPCeh_sjlj_longjmp addr:$buf)]>,
325 Requires<[In64BitMode]>;
328 //===----------------------------------------------------------------------===//
329 // 64-bit SPR manipulation instrs.
331 let Uses = [CTR8] in {
332 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
333 "mfctr $rT", IIC_SprMFSPR>,
334 PPC970_DGroup_First, PPC970_Unit_FXU;
336 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
337 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
338 "mtctr $rS", IIC_SprMTSPR>,
339 PPC970_DGroup_First, PPC970_Unit_FXU;
341 let hasSideEffects = 1, Defs = [CTR8] in {
342 let Pattern = [(int_ppc_mtctr i64:$rS)] in
343 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
344 "mtctr $rS", IIC_SprMTSPR>,
345 PPC970_DGroup_First, PPC970_Unit_FXU;
348 let Pattern = [(set i64:$rT, readcyclecounter)] in
349 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
350 "mfspr $rT, 268", IIC_SprMFTB>,
351 PPC970_DGroup_First, PPC970_Unit_FXU;
352 // Note that encoding mftb using mfspr is now the preferred form,
353 // and has been since at least ISA v2.03. The mftb instruction has
354 // now been phased out. Using mfspr, however, is known not to work on
357 let Defs = [X1], Uses = [X1] in
358 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
360 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
362 let Defs = [LR8] in {
363 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
364 "mtlr $rS", IIC_SprMTSPR>,
365 PPC970_DGroup_First, PPC970_Unit_FXU;
367 let Uses = [LR8] in {
368 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
369 "mflr $rT", IIC_SprMFSPR>,
370 PPC970_DGroup_First, PPC970_Unit_FXU;
372 } // Interpretation64Bit
374 //===----------------------------------------------------------------------===//
375 // Fixed point instructions.
378 let PPC970_Unit = 1 in { // FXU Operations.
379 let Interpretation64Bit = 1 in {
380 let hasSideEffects = 0 in {
381 let isCodeGenOnly = 1 in {
383 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
384 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
385 "li $rD, $imm", IIC_IntSimple,
386 [(set i64:$rD, imm64SExt16:$imm)]>;
387 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
388 "lis $rD, $imm", IIC_IntSimple,
389 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
393 let isCommutable = 1 in {
394 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
395 "nand", "$rA, $rS, $rB", IIC_IntSimple,
396 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
397 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
398 "and", "$rA, $rS, $rB", IIC_IntSimple,
399 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
401 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
402 "andc", "$rA, $rS, $rB", IIC_IntSimple,
403 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
404 let isCommutable = 1 in {
405 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
406 "or", "$rA, $rS, $rB", IIC_IntSimple,
407 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
408 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
409 "nor", "$rA, $rS, $rB", IIC_IntSimple,
410 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
412 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
413 "orc", "$rA, $rS, $rB", IIC_IntSimple,
414 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
415 let isCommutable = 1 in {
416 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
417 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
418 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
419 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
420 "xor", "$rA, $rS, $rB", IIC_IntSimple,
421 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
422 } // let isCommutable = 1
424 // Logical ops with immediate.
425 let Defs = [CR0] in {
426 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
427 "andi. $dst, $src1, $src2", IIC_IntGeneral,
428 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
430 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
431 "andis. $dst, $src1, $src2", IIC_IntGeneral,
432 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
435 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
436 "ori $dst, $src1, $src2", IIC_IntSimple,
437 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
438 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
439 "oris $dst, $src1, $src2", IIC_IntSimple,
440 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
441 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
442 "xori $dst, $src1, $src2", IIC_IntSimple,
443 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
444 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
445 "xoris $dst, $src1, $src2", IIC_IntSimple,
446 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
448 let isCommutable = 1 in
449 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
450 "add", "$rT, $rA, $rB", IIC_IntSimple,
451 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
452 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
453 // initial-exec thread-local storage model.
454 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
455 "add $rT, $rA, $rB", IIC_IntSimple,
456 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
458 let isCommutable = 1 in
459 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
460 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
461 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
462 PPC970_DGroup_Cracked;
464 let Defs = [CARRY] in
465 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
466 "addic $rD, $rA, $imm", IIC_IntGeneral,
467 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
468 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
469 "addi $rD, $rA, $imm", IIC_IntSimple,
470 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
471 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
472 "addis $rD, $rA, $imm", IIC_IntSimple,
473 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
475 let Defs = [CARRY] in {
476 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
477 "subfic $rD, $rA, $imm", IIC_IntGeneral,
478 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
479 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
480 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
481 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
482 PPC970_DGroup_Cracked;
484 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
485 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
486 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
487 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
488 "neg", "$rT, $rA", IIC_IntSimple,
489 [(set i64:$rT, (ineg i64:$rA))]>;
490 let Uses = [CARRY] in {
491 let isCommutable = 1 in
492 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
493 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
494 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
495 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
496 "addme", "$rT, $rA", IIC_IntGeneral,
497 [(set i64:$rT, (adde i64:$rA, -1))]>;
498 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
499 "addze", "$rT, $rA", IIC_IntGeneral,
500 [(set i64:$rT, (adde i64:$rA, 0))]>;
501 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
502 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
503 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
504 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
505 "subfme", "$rT, $rA", IIC_IntGeneral,
506 [(set i64:$rT, (sube -1, i64:$rA))]>;
507 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
508 "subfze", "$rT, $rA", IIC_IntGeneral,
509 [(set i64:$rT, (sube 0, i64:$rA))]>;
513 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
514 // previous definition must be marked as CodeGen only to prevent decoding
516 let isAsmParserOnly = 1 in
517 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
518 "add $rT, $rA, $rB", IIC_IntSimple, []>;
520 let isCommutable = 1 in {
521 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
522 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
523 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
524 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
525 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
526 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
529 } // Interpretation64Bit
531 let isCompare = 1, hasSideEffects = 0 in {
532 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
533 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
534 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
535 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
536 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
537 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
538 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
539 "cmpldi $dst, $src1, $src2",
540 IIC_IntCompare>, isPPC64;
543 let hasSideEffects = 0 in {
544 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
545 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
546 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
547 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
548 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
549 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
550 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
551 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
552 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
554 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
555 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
556 "extsb", "$rA, $rS", IIC_IntSimple,
557 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
558 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
559 "extsh", "$rA, $rS", IIC_IntSimple,
560 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
562 defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
563 "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
564 defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
565 "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>;
566 } // Interpretation64Bit
569 let isCodeGenOnly = 1 in {
570 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
571 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
572 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
573 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
574 } // isCodeGenOnly for fast-isel
576 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
577 "extsw", "$rA, $rS", IIC_IntSimple,
578 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
579 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
580 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
581 "extsw", "$rA, $rS", IIC_IntSimple,
582 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
584 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
585 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
586 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
587 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
588 "cntlzd", "$rA, $rS", IIC_IntGeneral,
589 [(set i64:$rA, (ctlz i64:$rS))]>;
590 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
591 "popcntd $rA, $rS", IIC_IntGeneral,
592 [(set i64:$rA, (ctpop i64:$rS))]>;
594 // popcntw also does a population count on the high 32 bits (storing the
595 // results in the high 32-bits of the output). We'll ignore that here (which is
596 // safe because we never separately use the high part of the 64-bit registers).
597 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
598 "popcntw $rA, $rS", IIC_IntGeneral,
599 [(set i32:$rA, (ctpop i32:$rS))]>;
601 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
602 "divd", "$rT, $rA, $rB", IIC_IntDivD,
603 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
604 PPC970_DGroup_First, PPC970_DGroup_Cracked;
605 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
606 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
607 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
608 PPC970_DGroup_First, PPC970_DGroup_Cracked;
609 let isCommutable = 1 in
610 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
611 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
612 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
613 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
614 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
615 "mulli $rD, $rA, $imm", IIC_IntMulLI,
616 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
619 let hasSideEffects = 0 in {
620 let isCommutable = 1 in {
621 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
622 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
623 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
624 []>, isPPC64, RegConstraint<"$rSi = $rA">,
628 // Rotate instructions.
629 defm RLDCL : MDSForm_1r<30, 8,
630 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
631 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
633 defm RLDCR : MDSForm_1r<30, 9,
634 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
635 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
637 defm RLDICL : MDForm_1r<30, 0,
638 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
639 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
642 let isCodeGenOnly = 1 in
643 def RLDICL_32_64 : MDForm_1<30, 0,
645 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
646 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
649 defm RLDICR : MDForm_1r<30, 1,
650 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
651 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
653 defm RLDIC : MDForm_1r<30, 2,
654 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
655 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
658 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
659 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
660 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
661 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
664 defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA),
665 (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME),
666 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral,
669 // RLWIMI can be commuted if the rotate amount is zero.
670 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
671 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
672 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
673 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
674 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
675 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
678 def ISEL8 : AForm_4<31, 15,
679 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
680 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
682 } // Interpretation64Bit
683 } // hasSideEffects = 0
684 } // End FXU Operations.
687 //===----------------------------------------------------------------------===//
688 // Load/Store instructions.
692 // Sign extending loads.
693 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
694 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
695 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
696 "lha $rD, $src", IIC_LdStLHA,
697 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
698 PPC970_DGroup_Cracked;
699 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
700 "lwa $rD, $src", IIC_LdStLWA,
702 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
703 PPC970_DGroup_Cracked;
704 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
705 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
706 "lhax $rD, $src", IIC_LdStLHA,
707 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
708 PPC970_DGroup_Cracked;
709 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
710 "lwax $rD, $src", IIC_LdStLHA,
711 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
712 PPC970_DGroup_Cracked;
714 let isCodeGenOnly = 1, mayLoad = 1 in {
715 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
716 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
717 PPC970_DGroup_Cracked;
718 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
719 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
720 PPC970_DGroup_Cracked;
721 } // end fast-isel isCodeGenOnly
724 let mayLoad = 1, hasSideEffects = 0 in {
725 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
726 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
728 "lhau $rD, $addr", IIC_LdStLHAU,
729 []>, RegConstraint<"$addr.reg = $ea_result">,
730 NoEncode<"$ea_result">;
733 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
734 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
736 "lhaux $rD, $addr", IIC_LdStLHAUX,
737 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
738 NoEncode<"$ea_result">;
739 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
741 "lwaux $rD, $addr", IIC_LdStLHAUX,
742 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
743 NoEncode<"$ea_result">, isPPC64;
747 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
748 // Zero extending loads.
749 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
750 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
751 "lbz $rD, $src", IIC_LdStLoad,
752 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
753 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
754 "lhz $rD, $src", IIC_LdStLoad,
755 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
756 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
757 "lwz $rD, $src", IIC_LdStLoad,
758 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
760 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
761 "lbzx $rD, $src", IIC_LdStLoad,
762 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
763 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
764 "lhzx $rD, $src", IIC_LdStLoad,
765 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
766 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
767 "lwzx $rD, $src", IIC_LdStLoad,
768 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
772 let mayLoad = 1, hasSideEffects = 0 in {
773 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
774 "lbzu $rD, $addr", IIC_LdStLoadUpd,
775 []>, RegConstraint<"$addr.reg = $ea_result">,
776 NoEncode<"$ea_result">;
777 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
778 "lhzu $rD, $addr", IIC_LdStLoadUpd,
779 []>, RegConstraint<"$addr.reg = $ea_result">,
780 NoEncode<"$ea_result">;
781 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
782 "lwzu $rD, $addr", IIC_LdStLoadUpd,
783 []>, RegConstraint<"$addr.reg = $ea_result">,
784 NoEncode<"$ea_result">;
786 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
788 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
789 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
790 NoEncode<"$ea_result">;
791 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
793 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
794 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
795 NoEncode<"$ea_result">;
796 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
798 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
799 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
800 NoEncode<"$ea_result">;
803 } // Interpretation64Bit
806 // Full 8-byte loads.
807 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
808 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
809 "ld $rD, $src", IIC_LdStLD,
810 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
811 // The following four definitions are selected for small code model only.
812 // Otherwise, we need to create two instructions to form a 32-bit offset,
813 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
814 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
817 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
818 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
821 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
822 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
825 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
826 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
829 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
831 let hasSideEffects = 1, isCodeGenOnly = 1, RST = 2, Defs = [X2] in
832 def LDinto_toc: DSForm_1<58, 0, (outs), (ins memrix:$src),
833 "ld 2, $src", IIC_LdStLD,
834 [(PPCload_toc ixaddr:$src)]>, isPPC64;
836 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
837 "ldx $rD, $src", IIC_LdStLD,
838 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
839 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
840 "ldbrx $rD, $src", IIC_LdStLoad,
841 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
843 let mayLoad = 1, hasSideEffects = 0 in {
844 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
845 "ldu $rD, $addr", IIC_LdStLDU,
846 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
847 NoEncode<"$ea_result">;
849 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
851 "ldux $rD, $addr", IIC_LdStLDUX,
852 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
853 NoEncode<"$ea_result">, isPPC64;
857 def : Pat<(PPCload ixaddr:$src),
859 def : Pat<(PPCload xaddr:$src),
862 // Support for medium and large code model.
863 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
866 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
868 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
871 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
872 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
875 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
877 // Support for thread-local storage.
878 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
881 (PPCaddisGotTprelHA i64:$reg,
882 tglobaltlsaddr:$disp))]>,
884 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
887 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
889 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
890 (ADD8TLS $in, tglobaltlsaddr:$g)>;
891 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
894 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
896 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
899 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
901 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
904 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
906 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
909 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
911 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
914 (PPCaddisDtprelHA i64:$reg,
915 tglobaltlsaddr:$disp))]>,
917 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
920 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
923 let PPC970_Unit = 2 in {
924 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
925 // Truncating stores.
926 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
927 "stb $rS, $src", IIC_LdStStore,
928 [(truncstorei8 i64:$rS, iaddr:$src)]>;
929 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
930 "sth $rS, $src", IIC_LdStStore,
931 [(truncstorei16 i64:$rS, iaddr:$src)]>;
932 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
933 "stw $rS, $src", IIC_LdStStore,
934 [(truncstorei32 i64:$rS, iaddr:$src)]>;
935 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
936 "stbx $rS, $dst", IIC_LdStStore,
937 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
938 PPC970_DGroup_Cracked;
939 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
940 "sthx $rS, $dst", IIC_LdStStore,
941 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
942 PPC970_DGroup_Cracked;
943 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
944 "stwx $rS, $dst", IIC_LdStStore,
945 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
946 PPC970_DGroup_Cracked;
947 } // Interpretation64Bit
949 // Normal 8-byte stores.
950 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
951 "std $rS, $dst", IIC_LdStSTD,
952 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
953 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
954 "stdx $rS, $dst", IIC_LdStSTD,
955 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
956 PPC970_DGroup_Cracked;
957 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
958 "stdbrx $rS, $dst", IIC_LdStStore,
959 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
960 PPC970_DGroup_Cracked;
963 // Stores with Update (pre-inc).
964 let PPC970_Unit = 2, mayStore = 1 in {
965 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
966 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
967 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
968 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
969 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
970 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
971 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
972 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
973 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
974 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
976 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
977 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
978 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
979 PPC970_DGroup_Cracked;
980 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
981 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
982 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
983 PPC970_DGroup_Cracked;
984 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
985 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
986 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
987 PPC970_DGroup_Cracked;
988 } // Interpretation64Bit
990 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
991 "stdu $rS, $dst", IIC_LdStSTDU, []>,
992 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
995 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
996 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
997 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
998 PPC970_DGroup_Cracked, isPPC64;
1001 // Patterns to match the pre-inc stores. We can't put the patterns on
1002 // the instruction definitions directly as ISel wants the address base
1003 // and offset to be separate operands, not a single complex operand.
1004 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1005 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1006 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1007 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1008 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1009 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
1010 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
1011 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1013 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1014 (STBUX8 $rS, $ptrreg, $ptroff)>;
1015 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1016 (STHUX8 $rS, $ptrreg, $ptroff)>;
1017 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1018 (STWUX8 $rS, $ptrreg, $ptroff)>;
1019 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1020 (STDUX $rS, $ptrreg, $ptroff)>;
1023 //===----------------------------------------------------------------------===//
1024 // Floating point instructions.
1028 let PPC970_Unit = 3, hasSideEffects = 0,
1029 Uses = [RM] in { // FPU Operations.
1030 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1031 "fcfid", "$frD, $frB", IIC_FPGeneral,
1032 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1033 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1034 "fctid", "$frD, $frB", IIC_FPGeneral,
1036 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1037 "fctidz", "$frD, $frB", IIC_FPGeneral,
1038 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1040 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1041 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1042 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1043 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1044 "fcfids", "$frD, $frB", IIC_FPGeneral,
1045 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1046 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1047 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1048 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1049 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1050 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1051 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1052 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1053 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1054 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1058 //===----------------------------------------------------------------------===//
1059 // Instruction Patterns
1062 // Extensions and truncates to/from 32-bit regs.
1063 def : Pat<(i64 (zext i32:$in)),
1064 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1066 def : Pat<(i64 (anyext i32:$in)),
1067 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1068 def : Pat<(i32 (trunc i64:$in)),
1069 (EXTRACT_SUBREG $in, sub_32)>;
1071 // Implement the 'not' operation with the NOR instruction.
1072 // (we could use the default xori pattern, but nor has lower latency on some
1073 // cores (such as the A2)).
1074 def i64not : OutPatFrag<(ops node:$in),
1076 def : Pat<(not i64:$in),
1079 // Extending loads with i64 targets.
1080 def : Pat<(zextloadi1 iaddr:$src),
1082 def : Pat<(zextloadi1 xaddr:$src),
1083 (LBZX8 xaddr:$src)>;
1084 def : Pat<(extloadi1 iaddr:$src),
1086 def : Pat<(extloadi1 xaddr:$src),
1087 (LBZX8 xaddr:$src)>;
1088 def : Pat<(extloadi8 iaddr:$src),
1090 def : Pat<(extloadi8 xaddr:$src),
1091 (LBZX8 xaddr:$src)>;
1092 def : Pat<(extloadi16 iaddr:$src),
1094 def : Pat<(extloadi16 xaddr:$src),
1095 (LHZX8 xaddr:$src)>;
1096 def : Pat<(extloadi32 iaddr:$src),
1098 def : Pat<(extloadi32 xaddr:$src),
1099 (LWZX8 xaddr:$src)>;
1101 // Standard shifts. These are represented separately from the real shifts above
1102 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1104 def : Pat<(sra i64:$rS, i32:$rB),
1106 def : Pat<(srl i64:$rS, i32:$rB),
1108 def : Pat<(shl i64:$rS, i32:$rB),
1112 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1113 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1114 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1115 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1118 def : Pat<(rotl i64:$in, i32:$sh),
1119 (RLDCL $in, $sh, 0)>;
1120 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1121 (RLDICL $in, imm:$imm, 0)>;
1123 // Hi and Lo for Darwin Global Addresses.
1124 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1125 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1126 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1127 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1128 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1129 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1130 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1131 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1132 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1133 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1134 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1135 (ADDI8 $in, tglobaltlsaddr:$g)>;
1136 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1137 (ADDIS8 $in, tglobaladdr:$g)>;
1138 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1139 (ADDIS8 $in, tconstpool:$g)>;
1140 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1141 (ADDIS8 $in, tjumptable:$g)>;
1142 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1143 (ADDIS8 $in, tblockaddress:$g)>;
1145 // Patterns to match r+r indexed loads and stores for
1146 // addresses without at least 4-byte alignment.
1147 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1148 (LWAX xoaddr:$src)>;
1149 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1151 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1152 (STDX $rS, xoaddr:$dst)>;
1154 // 64-bits atomic loads and stores
1155 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1156 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1158 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1159 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;