1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def tlsreg : Operand<i64> {
40 let EncoderMethod = "getTLSRegEncoding";
42 def tlsgd : Operand<i64> {}
43 def tlscall : Operand<i64> {
44 let PrintMethod = "printTLSCall";
45 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
46 let EncoderMethod = "getTLSCallEncoding";
49 //===----------------------------------------------------------------------===//
50 // 64-bit transformation functions.
53 def SHL64 : SDNodeXForm<imm, [{
54 // Transformation function: 63 - imm
55 return getI32Imm(63 - N->getZExtValue());
58 def SRL64 : SDNodeXForm<imm, [{
59 // Transformation function: 64 - imm
60 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
63 def HI32_48 : SDNodeXForm<imm, [{
64 // Transformation function: shift the immediate value down into the low bits.
65 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
68 def HI48_64 : SDNodeXForm<imm, [{
69 // Transformation function: shift the immediate value down into the low bits.
70 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
74 //===----------------------------------------------------------------------===//
78 let Interpretation64Bit = 1 in {
79 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
81 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
82 Requires<[In64BitMode]>;
84 let isCodeGenOnly = 1 in
85 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
87 Requires<[In64BitMode]>;
92 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
95 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
96 let Defs = [CTR8], Uses = [CTR8] in {
97 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
99 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
103 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
104 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
106 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
113 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
114 // Convenient aliases for call instructions
116 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
117 "bl $func", BrB, []>; // See Pat patterns below.
119 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
120 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
122 let Uses = [RM], isCodeGenOnly = 1 in {
123 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
124 (outs), (ins calltarget:$func),
125 "bl $func\n\tnop", BrB, []>;
127 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
128 (outs), (ins tlscall:$func),
129 "bl $func\n\tnop", BrB, []>;
131 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
132 (outs), (ins abscalltarget:$func),
133 "bla $func\n\tnop", BrB,
134 [(PPCcall_nop (i64 imm:$func))]>;
136 let Uses = [CTR8, RM] in {
137 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
138 "bctrl", BrB, [(PPCbctrl)]>,
139 Requires<[In64BitMode]>;
141 let isCodeGenOnly = 1 in
142 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
143 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
144 Requires<[In64BitMode]>;
147 } // Interpretation64Bit
150 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
151 (BL8 tglobaladdr:$dst)>;
152 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
153 (BL8_NOP tglobaladdr:$dst)>;
155 def : Pat<(PPCcall (i64 texternalsym:$dst)),
156 (BL8 texternalsym:$dst)>;
157 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
158 (BL8_NOP texternalsym:$dst)>;
161 let usesCustomInserter = 1 in {
162 let Defs = [CR0] in {
163 def ATOMIC_LOAD_ADD_I64 : Pseudo<
164 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
165 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
166 def ATOMIC_LOAD_SUB_I64 : Pseudo<
167 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
168 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
169 def ATOMIC_LOAD_OR_I64 : Pseudo<
170 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
171 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
172 def ATOMIC_LOAD_XOR_I64 : Pseudo<
173 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
174 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
175 def ATOMIC_LOAD_AND_I64 : Pseudo<
176 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
177 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
178 def ATOMIC_LOAD_NAND_I64 : Pseudo<
179 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
180 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
182 def ATOMIC_CMP_SWAP_I64 : Pseudo<
183 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
184 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
186 def ATOMIC_SWAP_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
188 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
192 // Instructions to support atomic operations
193 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
194 "ldarx $rD, $ptr", LdStLDARX,
195 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
198 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
199 "stdcx. $rS, $dst", LdStSTDCX,
200 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
203 let Interpretation64Bit = 1 in {
204 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
205 def TCRETURNdi8 :Pseudo< (outs),
206 (ins calltarget:$dst, i32imm:$offset),
207 "#TC_RETURNd8 $dst $offset",
210 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
211 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
212 "#TC_RETURNa8 $func $offset",
213 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
215 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
216 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
217 "#TC_RETURNr8 $dst $offset",
220 let isCodeGenOnly = 1 in {
222 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
223 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
224 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
225 Requires<[In64BitMode]>;
228 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
229 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
230 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
235 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
236 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
237 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
242 } // Interpretation64Bit
244 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
245 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
247 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
248 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
250 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
251 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
254 // 64-bit CR instructions
255 let Interpretation64Bit = 1 in {
256 let neverHasSideEffects = 1 in {
257 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS),
258 "mtcrf $FXM, $rS", BrMCRX>,
259 PPC970_MicroCode, PPC970_Unit_CRU;
261 let isCodeGenOnly = 1 in
262 def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
263 "#MFCR8pseud", SprMFCR>,
264 PPC970_MicroCode, PPC970_Unit_CRU;
265 } // neverHasSideEffects = 1
267 let neverHasSideEffects = 1 in
268 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
269 "mfcr $rT", SprMFCR>,
270 PPC970_MicroCode, PPC970_Unit_CRU;
272 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
273 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
275 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
276 Requires<[In64BitMode]>;
277 let isTerminator = 1 in
278 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
279 "#EH_SJLJ_LONGJMP64",
280 [(PPCeh_sjlj_longjmp addr:$buf)]>,
281 Requires<[In64BitMode]>;
284 //===----------------------------------------------------------------------===//
285 // 64-bit SPR manipulation instrs.
287 let Uses = [CTR8] in {
288 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
289 "mfctr $rT", SprMFSPR>,
290 PPC970_DGroup_First, PPC970_Unit_FXU;
292 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
293 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
294 "mtctr $rS", SprMTSPR>,
295 PPC970_DGroup_First, PPC970_Unit_FXU;
297 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
298 let Pattern = [(int_ppc_mtctr i64:$rS)] in
299 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
300 "mtctr $rS", SprMTSPR>,
301 PPC970_DGroup_First, PPC970_Unit_FXU;
304 let Pattern = [(set i64:$rT, readcyclecounter)] in
305 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
306 "mfspr $rT, 268", SprMFTB>,
307 PPC970_DGroup_First, PPC970_Unit_FXU;
308 // Note that encoding mftb using mfspr is now the preferred form,
309 // and has been since at least ISA v2.03. The mftb instruction has
310 // now been phased out. Using mfspr, however, is known not to work on
313 let Defs = [X1], Uses = [X1] in
314 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
316 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
318 let Defs = [LR8] in {
319 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
320 "mtlr $rS", SprMTSPR>,
321 PPC970_DGroup_First, PPC970_Unit_FXU;
323 let Uses = [LR8] in {
324 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
325 "mflr $rT", SprMFSPR>,
326 PPC970_DGroup_First, PPC970_Unit_FXU;
328 } // Interpretation64Bit
330 //===----------------------------------------------------------------------===//
331 // Fixed point instructions.
334 let PPC970_Unit = 1 in { // FXU Operations.
335 let Interpretation64Bit = 1 in {
336 let neverHasSideEffects = 1 in {
338 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
339 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
340 "li $rD, $imm", IntSimple,
341 [(set i64:$rD, imm64SExt16:$imm)]>;
342 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
343 "lis $rD, $imm", IntSimple,
344 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
348 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
349 "nand", "$rA, $rS, $rB", IntSimple,
350 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
351 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
352 "and", "$rA, $rS, $rB", IntSimple,
353 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
354 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
355 "andc", "$rA, $rS, $rB", IntSimple,
356 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
357 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
358 "or", "$rA, $rS, $rB", IntSimple,
359 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
360 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
361 "nor", "$rA, $rS, $rB", IntSimple,
362 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
363 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
364 "orc", "$rA, $rS, $rB", IntSimple,
365 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
366 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
367 "eqv", "$rA, $rS, $rB", IntSimple,
368 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
369 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
370 "xor", "$rA, $rS, $rB", IntSimple,
371 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
373 // Logical ops with immediate.
374 let Defs = [CR0] in {
375 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
376 "andi. $dst, $src1, $src2", IntGeneral,
377 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
379 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
380 "andis. $dst, $src1, $src2", IntGeneral,
381 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
384 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
385 "ori $dst, $src1, $src2", IntSimple,
386 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
387 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
388 "oris $dst, $src1, $src2", IntSimple,
389 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
390 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
391 "xori $dst, $src1, $src2", IntSimple,
392 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
393 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
394 "xoris $dst, $src1, $src2", IntSimple,
395 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
397 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
398 "add", "$rT, $rA, $rB", IntSimple,
399 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
400 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
401 // initial-exec thread-local storage model.
402 let isCodeGenOnly = 1 in
403 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
404 "add $rT, $rA, $rB@tls", IntSimple,
405 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
407 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
408 "addc", "$rT, $rA, $rB", IntGeneral,
409 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
410 PPC970_DGroup_Cracked;
411 let Defs = [CARRY] in
412 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
413 "addic $rD, $rA, $imm", IntGeneral,
414 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
415 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
416 "addi $rD, $rA, $imm", IntSimple,
417 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
418 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
419 "addis $rD, $rA, $imm", IntSimple,
420 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
422 let Defs = [CARRY] in {
423 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
424 "subfic $rD, $rA, $imm", IntGeneral,
425 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
426 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
427 "subfc", "$rT, $rA, $rB", IntGeneral,
428 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
429 PPC970_DGroup_Cracked;
431 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
432 "subf", "$rT, $rA, $rB", IntGeneral,
433 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
434 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
435 "neg", "$rT, $rA", IntSimple,
436 [(set i64:$rT, (ineg i64:$rA))]>;
437 let Uses = [CARRY] in {
438 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
439 "adde", "$rT, $rA, $rB", IntGeneral,
440 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
441 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
442 "addme", "$rT, $rA", IntGeneral,
443 [(set i64:$rT, (adde i64:$rA, -1))]>;
444 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
445 "addze", "$rT, $rA", IntGeneral,
446 [(set i64:$rT, (adde i64:$rA, 0))]>;
447 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
448 "subfe", "$rT, $rA, $rB", IntGeneral,
449 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
450 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
451 "subfme", "$rT, $rA", IntGeneral,
452 [(set i64:$rT, (sube -1, i64:$rA))]>;
453 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
454 "subfze", "$rT, $rA", IntGeneral,
455 [(set i64:$rT, (sube 0, i64:$rA))]>;
459 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
460 "mulhd", "$rT, $rA, $rB", IntMulHW,
461 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
462 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
463 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
464 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
466 } // Interpretation64Bit
468 let isCompare = 1, neverHasSideEffects = 1 in {
469 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
470 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
471 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
472 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
473 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
474 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
475 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
476 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
479 let neverHasSideEffects = 1 in {
480 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
481 "sld", "$rA, $rS, $rB", IntRotateD,
482 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
483 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
484 "srd", "$rA, $rS, $rB", IntRotateD,
485 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
486 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
487 "srad", "$rA, $rS, $rB", IntRotateD,
488 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
490 let Interpretation64Bit = 1 in {
491 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
492 "extsb", "$rA, $rS", IntSimple,
493 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
494 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
495 "extsh", "$rA, $rS", IntSimple,
496 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
497 } // Interpretation64Bit
499 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
500 "extsw", "$rA, $rS", IntSimple,
501 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
502 let Interpretation64Bit = 1 in
503 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
504 "extsw", "$rA, $rS", IntSimple,
505 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
507 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
508 "sradi", "$rA, $rS, $SH", IntRotateDI,
509 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
510 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
511 "cntlzd", "$rA, $rS", IntGeneral,
512 [(set i64:$rA, (ctlz i64:$rS))]>;
513 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
514 "popcntd", "$rA, $rS", IntGeneral,
515 [(set i64:$rA, (ctpop i64:$rS))]>;
517 // popcntw also does a population count on the high 32 bits (storing the
518 // results in the high 32-bits of the output). We'll ignore that here (which is
519 // safe because we never separately use the high part of the 64-bit registers).
520 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
521 "popcntw", "$rA, $rS", IntGeneral,
522 [(set i32:$rA, (ctpop i32:$rS))]>;
524 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
525 "divd", "$rT, $rA, $rB", IntDivD,
526 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
527 PPC970_DGroup_First, PPC970_DGroup_Cracked;
528 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
529 "divdu", "$rT, $rA, $rB", IntDivD,
530 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
531 PPC970_DGroup_First, PPC970_DGroup_Cracked;
532 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
533 "mulld", "$rT, $rA, $rB", IntMulHD,
534 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
537 let neverHasSideEffects = 1 in {
538 let isCommutable = 1 in {
539 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
540 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
541 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
542 []>, isPPC64, RegConstraint<"$rSi = $rA">,
546 // Rotate instructions.
547 defm RLDCL : MDSForm_1r<30, 8,
548 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
549 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
551 defm RLDCR : MDSForm_1r<30, 9,
552 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
553 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
555 defm RLDICL : MDForm_1r<30, 0,
556 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
557 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
559 defm RLDICR : MDForm_1r<30, 1,
560 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
561 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
563 defm RLDIC : MDForm_1r<30, 2,
564 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
565 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
568 let Interpretation64Bit = 1 in {
569 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
570 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
571 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
575 def ISEL8 : AForm_4<31, 15,
576 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
577 "isel $rT, $rA, $rB, $cond", IntGeneral,
579 } // Interpretation64Bit
580 } // neverHasSideEffects = 1
581 } // End FXU Operations.
584 //===----------------------------------------------------------------------===//
585 // Load/Store instructions.
589 // Sign extending loads.
590 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
591 let Interpretation64Bit = 1 in
592 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
593 "lha $rD, $src", LdStLHA,
594 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
595 PPC970_DGroup_Cracked;
596 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
597 "lwa $rD, $src", LdStLWA,
599 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
600 PPC970_DGroup_Cracked;
601 let Interpretation64Bit = 1 in
602 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
603 "lhax $rD, $src", LdStLHA,
604 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
605 PPC970_DGroup_Cracked;
606 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
607 "lwax $rD, $src", LdStLHA,
608 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
609 PPC970_DGroup_Cracked;
612 let mayLoad = 1, neverHasSideEffects = 1 in {
613 let Interpretation64Bit = 1 in
614 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
616 "lhau $rD, $addr", LdStLHAU,
617 []>, RegConstraint<"$addr.reg = $ea_result">,
618 NoEncode<"$ea_result">;
621 let Interpretation64Bit = 1 in
622 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
624 "lhaux $rD, $addr", LdStLHAU,
625 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
626 NoEncode<"$ea_result">;
627 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
629 "lwaux $rD, $addr", LdStLHAU,
630 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
631 NoEncode<"$ea_result">, isPPC64;
635 let Interpretation64Bit = 1 in {
636 // Zero extending loads.
637 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
638 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
639 "lbz $rD, $src", LdStLoad,
640 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
641 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
642 "lhz $rD, $src", LdStLoad,
643 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
644 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
645 "lwz $rD, $src", LdStLoad,
646 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
648 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
649 "lbzx $rD, $src", LdStLoad,
650 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
651 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
652 "lhzx $rD, $src", LdStLoad,
653 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
654 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
655 "lwzx $rD, $src", LdStLoad,
656 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
660 let mayLoad = 1, neverHasSideEffects = 1 in {
661 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
662 "lbzu $rD, $addr", LdStLoadUpd,
663 []>, RegConstraint<"$addr.reg = $ea_result">,
664 NoEncode<"$ea_result">;
665 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
666 "lhzu $rD, $addr", LdStLoadUpd,
667 []>, RegConstraint<"$addr.reg = $ea_result">,
668 NoEncode<"$ea_result">;
669 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
670 "lwzu $rD, $addr", LdStLoadUpd,
671 []>, RegConstraint<"$addr.reg = $ea_result">,
672 NoEncode<"$ea_result">;
674 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
676 "lbzux $rD, $addr", LdStLoadUpd,
677 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
678 NoEncode<"$ea_result">;
679 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
681 "lhzux $rD, $addr", LdStLoadUpd,
682 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
683 NoEncode<"$ea_result">;
684 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
686 "lwzux $rD, $addr", LdStLoadUpd,
687 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
688 NoEncode<"$ea_result">;
691 } // Interpretation64Bit
694 // Full 8-byte loads.
695 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
696 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
697 "ld $rD, $src", LdStLD,
698 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
699 // The following three definitions are selected for small code model only.
700 // Otherwise, we need to create two instructions to form a 32-bit offset,
701 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
702 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
705 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
706 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
709 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
710 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
713 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
715 let hasSideEffects = 1, isCodeGenOnly = 1 in {
716 let RST = 2, DS = 2 in
717 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
718 "ld 2, 8($reg)", LdStLD,
719 [(PPCload_toc i64:$reg)]>, isPPC64;
721 let RST = 2, DS = 10, RA = 1 in
722 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
723 "ld 2, 40(1)", LdStLD,
724 [(PPCtoc_restore)]>, isPPC64;
726 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
727 "ldx $rD, $src", LdStLD,
728 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
729 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
730 "ldbrx $rD, $src", LdStLoad,
731 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
733 let mayLoad = 1, neverHasSideEffects = 1 in {
734 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
735 "ldu $rD, $addr", LdStLDU,
736 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
737 NoEncode<"$ea_result">;
739 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
741 "ldux $rD, $addr", LdStLDU,
742 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
743 NoEncode<"$ea_result">, isPPC64;
747 def : Pat<(PPCload ixaddr:$src),
749 def : Pat<(PPCload xaddr:$src),
752 // Support for medium and large code model.
753 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
756 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
758 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
761 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
762 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
765 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
767 // Support for thread-local storage.
768 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
771 (PPCaddisGotTprelHA i64:$reg,
772 tglobaltlsaddr:$disp))]>,
774 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
777 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
779 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
780 (ADD8TLS $in, tglobaltlsaddr:$g)>;
781 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
784 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
786 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
789 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
791 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
794 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
796 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
799 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
801 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
804 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
806 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
809 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
811 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
814 (PPCaddisDtprelHA i64:$reg,
815 tglobaltlsaddr:$disp))]>,
817 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
820 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
823 let PPC970_Unit = 2 in {
824 let Interpretation64Bit = 1 in {
825 // Truncating stores.
826 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
827 "stb $rS, $src", LdStStore,
828 [(truncstorei8 i64:$rS, iaddr:$src)]>;
829 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
830 "sth $rS, $src", LdStStore,
831 [(truncstorei16 i64:$rS, iaddr:$src)]>;
832 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
833 "stw $rS, $src", LdStStore,
834 [(truncstorei32 i64:$rS, iaddr:$src)]>;
835 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
836 "stbx $rS, $dst", LdStStore,
837 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
838 PPC970_DGroup_Cracked;
839 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
840 "sthx $rS, $dst", LdStStore,
841 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
842 PPC970_DGroup_Cracked;
843 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
844 "stwx $rS, $dst", LdStStore,
845 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
846 PPC970_DGroup_Cracked;
847 } // Interpretation64Bit
849 // Normal 8-byte stores.
850 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
851 "std $rS, $dst", LdStSTD,
852 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
853 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
854 "stdx $rS, $dst", LdStSTD,
855 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
856 PPC970_DGroup_Cracked;
857 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
858 "stdbrx $rS, $dst", LdStStore,
859 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
860 PPC970_DGroup_Cracked;
863 // Stores with Update (pre-inc).
864 let PPC970_Unit = 2, mayStore = 1 in {
865 let Interpretation64Bit = 1 in {
866 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
867 "stbu $rS, $dst", LdStStoreUpd, []>,
868 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
869 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
870 "sthu $rS, $dst", LdStStoreUpd, []>,
871 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
872 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
873 "stwu $rS, $dst", LdStStoreUpd, []>,
874 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
875 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
876 "stdu $rS, $dst", LdStSTDU, []>,
877 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
880 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
881 "stbux $rS, $dst", LdStStoreUpd, []>,
882 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
883 PPC970_DGroup_Cracked;
884 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
885 "sthux $rS, $dst", LdStStoreUpd, []>,
886 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
887 PPC970_DGroup_Cracked;
888 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
889 "stwux $rS, $dst", LdStStoreUpd, []>,
890 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
891 PPC970_DGroup_Cracked;
892 } // Interpretation64Bit
894 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
895 "stdux $rS, $dst", LdStSTDU, []>,
896 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
897 PPC970_DGroup_Cracked, isPPC64;
900 // Patterns to match the pre-inc stores. We can't put the patterns on
901 // the instruction definitions directly as ISel wants the address base
902 // and offset to be separate operands, not a single complex operand.
903 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
904 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
905 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
906 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
907 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
908 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
909 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
910 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
912 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
913 (STBUX8 $rS, $ptrreg, $ptroff)>;
914 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
915 (STHUX8 $rS, $ptrreg, $ptroff)>;
916 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
917 (STWUX8 $rS, $ptrreg, $ptroff)>;
918 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
919 (STDUX $rS, $ptrreg, $ptroff)>;
922 //===----------------------------------------------------------------------===//
923 // Floating point instructions.
927 let PPC970_Unit = 3, neverHasSideEffects = 1,
928 Uses = [RM] in { // FPU Operations.
929 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
930 "fcfid", "$frD, $frB", FPGeneral,
931 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
932 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
933 "fctidz", "$frD, $frB", FPGeneral,
934 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
936 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
937 "fcfidu", "$frD, $frB", FPGeneral,
938 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
939 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
940 "fcfids", "$frD, $frB", FPGeneral,
941 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
942 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
943 "fcfidus", "$frD, $frB", FPGeneral,
944 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
945 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
946 "fctiduz", "$frD, $frB", FPGeneral,
947 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
948 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
949 "fctiwuz", "$frD, $frB", FPGeneral,
950 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
954 //===----------------------------------------------------------------------===//
955 // Instruction Patterns
958 // Extensions and truncates to/from 32-bit regs.
959 def : Pat<(i64 (zext i32:$in)),
960 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
962 def : Pat<(i64 (anyext i32:$in)),
963 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
964 def : Pat<(i32 (trunc i64:$in)),
965 (EXTRACT_SUBREG $in, sub_32)>;
967 // Extending loads with i64 targets.
968 def : Pat<(zextloadi1 iaddr:$src),
970 def : Pat<(zextloadi1 xaddr:$src),
972 def : Pat<(extloadi1 iaddr:$src),
974 def : Pat<(extloadi1 xaddr:$src),
976 def : Pat<(extloadi8 iaddr:$src),
978 def : Pat<(extloadi8 xaddr:$src),
980 def : Pat<(extloadi16 iaddr:$src),
982 def : Pat<(extloadi16 xaddr:$src),
984 def : Pat<(extloadi32 iaddr:$src),
986 def : Pat<(extloadi32 xaddr:$src),
989 // Standard shifts. These are represented separately from the real shifts above
990 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
992 def : Pat<(sra i64:$rS, i32:$rB),
994 def : Pat<(srl i64:$rS, i32:$rB),
996 def : Pat<(shl i64:$rS, i32:$rB),
1000 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1001 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1002 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1003 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1006 def : Pat<(rotl i64:$in, i32:$sh),
1007 (RLDCL $in, $sh, 0)>;
1008 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1009 (RLDICL $in, imm:$imm, 0)>;
1011 // Hi and Lo for Darwin Global Addresses.
1012 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1013 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1014 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1015 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1016 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1017 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1018 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1019 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1020 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1021 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1022 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1023 (ADDI8 $in, tglobaltlsaddr:$g)>;
1024 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1025 (ADDIS8 $in, tglobaladdr:$g)>;
1026 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1027 (ADDIS8 $in, tconstpool:$g)>;
1028 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1029 (ADDIS8 $in, tjumptable:$g)>;
1030 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1031 (ADDIS8 $in, tblockaddress:$g)>;
1033 // Patterns to match r+r indexed loads and stores for
1034 // addresses without at least 4-byte alignment.
1035 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1036 (LWAX xoaddr:$src)>;
1037 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1039 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1040 (STDX $rS, xoaddr:$dst)>;