1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
61 [(set G8RC:$rD, (undef))]>;
64 //===----------------------------------------------------------------------===//
69 def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
72 let isCall = 1, noResults = 1, PPC970_Unit = 7,
73 // All calls clobber the PPC64 non-callee saved registers.
74 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
75 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
76 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
78 CR0,CR1,CR5,CR6,CR7] in {
79 // Convenient aliases for call instructions
80 def BL8 : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
81 "bl $func", BrB, []>; // See Pat patterns below.
83 def BLA8 : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
84 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
88 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
89 (BL8 tglobaladdr:$dst)>;
90 def : Pat<(PPCcall (i64 texternalsym:$dst)),
91 (BL8 texternalsym:$dst)>;
93 //===----------------------------------------------------------------------===//
94 // 64-bit SPR manipulation instrs.
96 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
97 PPC970_DGroup_First, PPC970_Unit_FXU;
98 let Pattern = [(PPCmtctr G8RC:$rS)] in {
99 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
100 PPC970_DGroup_First, PPC970_Unit_FXU;
103 def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
104 PPC970_DGroup_First, PPC970_Unit_FXU;
105 def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
106 PPC970_DGroup_First, PPC970_Unit_FXU;
109 //===----------------------------------------------------------------------===//
110 // Fixed point instructions.
113 let PPC970_Unit = 1 in { // FXU Operations.
115 // Copies, extends, truncates.
116 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
117 "or $rA, $rS, $rB", IntGeneral,
119 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
120 "or $rA, $rS, $rB", IntGeneral,
123 def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
124 "li $rD, $imm", IntGeneral,
125 [(set G8RC:$rD, immSExt16:$imm)]>;
126 def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
127 "lis $rD, $imm", IntGeneral,
128 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
131 def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
132 "nand $rA, $rS, $rB", IntGeneral,
133 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
134 def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
135 "and $rA, $rS, $rB", IntGeneral,
136 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
137 def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
138 "andc $rA, $rS, $rB", IntGeneral,
139 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
140 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
141 "or $rA, $rS, $rB", IntGeneral,
142 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
143 def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
144 "nor $rA, $rS, $rB", IntGeneral,
145 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
146 def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
147 "orc $rA, $rS, $rB", IntGeneral,
148 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
149 def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
150 "eqv $rA, $rS, $rB", IntGeneral,
151 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
152 def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
153 "xor $rA, $rS, $rB", IntGeneral,
154 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
156 // Logical ops with immediate.
157 def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
158 "andi. $dst, $src1, $src2", IntGeneral,
159 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
161 def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
162 "andis. $dst, $src1, $src2", IntGeneral,
163 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
165 def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
166 "ori $dst, $src1, $src2", IntGeneral,
167 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
168 def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
169 "oris $dst, $src1, $src2", IntGeneral,
170 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
171 def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
172 "xori $dst, $src1, $src2", IntGeneral,
173 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
174 def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
175 "xoris $dst, $src1, $src2", IntGeneral,
176 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
178 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
179 "add $rT, $rA, $rB", IntGeneral,
180 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
181 def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
182 "addi $rD, $rA, $imm", IntGeneral,
183 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
184 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
185 "addis $rD, $rA, $imm", IntGeneral,
186 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
188 def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
189 "subfic $rD, $rA, $imm", IntGeneral,
190 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
191 def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
192 "subf $rT, $rA, $rB", IntGeneral,
193 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
196 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
197 "mulhd $rT, $rA, $rB", IntMulHW,
198 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
199 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
200 "mulhdu $rT, $rA, $rB", IntMulHWU,
201 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
203 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
204 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
205 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
206 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
207 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
208 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
209 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
210 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
212 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
213 "sld $rA, $rS, $rB", IntRotateD,
214 [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
215 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
216 "srd $rA, $rS, $rB", IntRotateD,
217 [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
218 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
219 "srad $rA, $rS, $rB", IntRotateD,
220 [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
221 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
222 "extsw $rA, $rS", IntGeneral,
223 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
224 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
225 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
226 "extsw $rA, $rS", IntGeneral,
227 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
228 def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
229 "extsw $rA, $rS", IntGeneral,
230 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
232 def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH),
233 "sradi $rA, $rS, $SH", IntRotateD,
234 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
236 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
237 "divd $rT, $rA, $rB", IntDivD,
238 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
239 PPC970_DGroup_First, PPC970_DGroup_Cracked;
240 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
241 "divdu $rT, $rA, $rB", IntDivD,
242 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
243 PPC970_DGroup_First, PPC970_DGroup_Cracked;
244 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
245 "mulld $rT, $rA, $rB", IntMulHD,
246 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
249 let isTwoAddress = 1, isCommutable = 1 in {
250 def RLDIMI : MDForm_1<30, 3,
251 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
252 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
256 // Rotate instructions.
257 def RLDICL : MDForm_1<30, 0,
258 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
259 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
261 def RLDICR : MDForm_1<30, 1,
262 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
263 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
265 } // End FXU Operations.
268 //===----------------------------------------------------------------------===//
269 // Load/Store instructions.
273 // Sign extending loads.
274 let isLoad = 1, PPC970_Unit = 2 in {
275 def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
276 "lha $rD, $src", LdStLHA,
277 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
278 PPC970_DGroup_Cracked;
279 def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
280 "lwa $rD, $src", LdStLWA,
281 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
282 PPC970_DGroup_Cracked;
283 def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src),
284 "lhax $rD, $src", LdStLHA,
285 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
286 PPC970_DGroup_Cracked;
287 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
288 "lwax $rD, $src", LdStLHA,
289 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
290 PPC970_DGroup_Cracked;
293 def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
295 "lhau $rD, $disp($rA)", LdStGeneral,
296 []>, RegConstraint<"$rA = $rA_result">;
301 // Zero extending loads.
302 let isLoad = 1, PPC970_Unit = 2 in {
303 def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
304 "lbz $rD, $src", LdStGeneral,
305 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
306 def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src),
307 "lhz $rD, $src", LdStGeneral,
308 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
309 def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
310 "lwz $rD, $src", LdStGeneral,
311 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
313 def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src),
314 "lbzx $rD, $src", LdStGeneral,
315 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
316 def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src),
317 "lhzx $rD, $src", LdStGeneral,
318 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
319 def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
320 "lwzx $rD, $src", LdStGeneral,
321 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
325 def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
327 "lbzu $rD, $disp($rA)", LdStGeneral,
328 []>, RegConstraint<"$rA = $rA_result">;
329 def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
331 "lhzu $rD, $disp($rA)", LdStGeneral,
332 []>, RegConstraint<"$rA = $rA_result">;
333 def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
335 "lwzu $rD, $disp($rA)", LdStGeneral,
336 []>, RegConstraint<"$rA = $rA_result">;
341 // Full 8-byte loads.
342 let isLoad = 1, PPC970_Unit = 2 in {
343 def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
344 "ld $rD, $src", LdStLD,
345 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
346 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
347 "ldx $rD, $src", LdStLD,
348 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
350 def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
352 "ldu $rD, $disp($rA)", LdStLD,
353 []>, RegConstraint<"$rA = $rA_result">, isPPC64;
357 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
359 def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
360 "std $rS, $dst", LdStSTD,
361 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
362 def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
363 "stdx $rS, $dst", LdStSTD,
364 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
365 PPC970_DGroup_Cracked;
367 def STDU : DSForm_1<62, 1, (ops G8RC:$ea_res, G8RC:$rS, memrix:$dst),
368 "stdu $rS, $dst", LdStSTD,
370 def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
371 "stdux $rS, $dst", LdStSTD,
374 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
375 def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
376 "std $rT, $dst", LdStSTD,
377 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
378 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
379 "stdx $rT, $dst", LdStSTD,
380 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
381 PPC970_DGroup_Cracked;
384 // Truncating stores.
385 def STB8 : DForm_3<38, (ops G8RC:$rS, memri:$src),
386 "stb $rS, $src", LdStGeneral,
387 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
388 def STH8 : DForm_3<44, (ops G8RC:$rS, memri:$src),
389 "sth $rS, $src", LdStGeneral,
390 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
391 def STW8 : DForm_3<36, (ops G8RC:$rS, memri:$src),
392 "stw $rS, $src", LdStGeneral,
393 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
394 def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
395 "stbx $rS, $dst", LdStGeneral,
396 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
397 PPC970_DGroup_Cracked;
398 def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
399 "sthx $rS, $dst", LdStGeneral,
400 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
401 PPC970_DGroup_Cracked;
402 def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
403 "stwx $rS, $dst", LdStGeneral,
404 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
405 PPC970_DGroup_Cracked;
410 //===----------------------------------------------------------------------===//
411 // Floating point instructions.
415 let PPC970_Unit = 3 in { // FPU Operations.
416 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
417 "fcfid $frD, $frB", FPGeneral,
418 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
419 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
420 "fctidz $frD, $frB", FPGeneral,
421 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
425 //===----------------------------------------------------------------------===//
426 // Instruction Patterns
429 // Immediate support.
431 // sext(0x0000_0000_0000_FFFF, i8) -> li imm
432 // sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
434 // sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori
435 def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
436 return N->getValue() == (uint64_t)(int32_t)N->getValue();
438 def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
439 (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
441 // zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16
442 def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{
443 return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0;
445 def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm),
446 (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
448 // zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16
449 def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
450 return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
452 def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
453 (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>;
455 // FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff
456 // like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's!
458 // Fully general (and most expensive: 6 instructions!) immediate pattern.
459 def : Pat<(i64 imm:$imm),
464 (LIS8 (HI48_64 imm:$imm)),
471 // Extensions and truncates to/from 32-bit regs.
472 def : Pat<(i64 (zext GPRC:$in)),
473 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
474 def : Pat<(i64 (anyext GPRC:$in)),
475 (OR4To8 GPRC:$in, GPRC:$in)>;
476 def : Pat<(i32 (trunc G8RC:$in)),
477 (OR8To4 G8RC:$in, G8RC:$in)>;
479 // Extending loads with i64 targets.
480 def : Pat<(zextloadi1 iaddr:$src),
482 def : Pat<(zextloadi1 xaddr:$src),
484 def : Pat<(extloadi1 iaddr:$src),
486 def : Pat<(extloadi1 xaddr:$src),
488 def : Pat<(extloadi8 iaddr:$src),
490 def : Pat<(extloadi8 xaddr:$src),
492 def : Pat<(extloadi16 iaddr:$src),
494 def : Pat<(extloadi16 xaddr:$src),
496 def : Pat<(extloadi32 iaddr:$src),
498 def : Pat<(extloadi32 xaddr:$src),
502 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
503 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
504 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
505 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
507 // Hi and Lo for Darwin Global Addresses.
508 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
509 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
510 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
511 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
512 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
513 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
514 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
515 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
516 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
517 (ADDIS8 G8RC:$in, tconstpool:$g)>;
518 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
519 (ADDIS8 G8RC:$in, tjumptable:$g)>;