1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
65 let isCall = 1, PPC970_Unit = 7,
66 // All calls clobber the PPC64 non-callee saved registers.
67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
71 CR0,CR1,CR5,CR6,CR7] in {
72 // Convenient aliases for call instructions
73 def BL8_Macho : IForm<18, 0, 1,
74 (outs), (ins calltarget:$func, variable_ops),
75 "bl $func", BrB, []>; // See Pat patterns below.
76 def BLA8_Macho : IForm<18, 1, 1,
77 (outs), (ins aaddr:$func, variable_ops),
78 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
79 def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
80 (outs), (ins variable_ops),
82 [(PPCbctrl_Macho)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Macho ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7,
88 // All calls clobber the PPC64 non-callee saved registers.
89 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
90 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
91 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
93 CR0,CR1,CR5,CR6,CR7] in {
94 // Convenient aliases for call instructions
95 def BL8_ELF : IForm<18, 0, 1,
96 (outs), (ins calltarget:$func, variable_ops),
97 "bl $func", BrB, []>; // See Pat patterns below.
98 def BLA8_ELF : IForm<18, 1, 1,
99 (outs), (ins aaddr:$func, variable_ops),
100 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
101 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
102 (outs), (ins variable_ops),
104 [(PPCbctrl_ELF)]>, Requires<[In64BitMode]>;
109 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
110 (BL8_Macho tglobaladdr:$dst)>;
111 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
112 (BL8_Macho texternalsym:$dst)>;
114 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
115 (BL8_ELF tglobaladdr:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
117 (BL8_ELF texternalsym:$dst)>;
120 let usesCustomDAGSchedInserter = 1 in {
121 let Uses = [CR0] in {
122 def ATOMIC_LOAD_ADD_I64 : Pseudo<
123 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
124 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
125 [(set G8RC:$dst, (PPCatomic_load_add xoaddr:$ptr, G8RC:$incr))]>;
126 def ATOMIC_CMP_SWAP_I64 : Pseudo<
127 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
128 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
129 [(set G8RC:$dst, (PPCatomic_cmp_swap xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
130 def ATOMIC_SWAP_I64 : Pseudo<
131 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
132 "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
133 [(set G8RC:$dst, (PPCatomic_swap xoaddr:$ptr, G8RC:$new))]>;
137 // Instructions to support atomic operations
138 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
139 "ldarx $rD, $ptr", LdStLDARX,
140 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
143 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
144 "stdcx. $rS, $dst", LdStSTDCX,
145 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
148 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
149 def TCRETURNdi8 :Pseudo< (outs),
150 (ins calltarget:$dst, i32imm:$offset, variable_ops),
151 "#TC_RETURNd8 $dst $offset",
154 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
155 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
156 "#TC_RETURNa8 $func $offset",
157 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
159 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
160 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
161 "#TC_RETURNr8 $dst $offset",
165 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
166 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
167 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
168 Requires<[In64BitMode]>;
172 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
173 isBarrier = 1, isCall = 1, isReturn = 1 in
174 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
179 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
180 isBarrier = 1, isCall = 1, isReturn = 1 in
181 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
185 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
186 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
188 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
189 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
191 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
192 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
195 //===----------------------------------------------------------------------===//
196 // 64-bit SPR manipulation instrs.
198 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
199 "mfctr $rT", SprMFSPR>,
200 PPC970_DGroup_First, PPC970_Unit_FXU;
201 let Pattern = [(PPCmtctr G8RC:$rS)] in {
202 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
203 "mtctr $rS", SprMTSPR>,
204 PPC970_DGroup_First, PPC970_Unit_FXU;
207 let Defs = [X1], Uses = [X1] in
208 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
209 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
211 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
213 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
214 "mtlr $rS", SprMTSPR>,
215 PPC970_DGroup_First, PPC970_Unit_FXU;
216 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
217 "mflr $rT", SprMFSPR>,
218 PPC970_DGroup_First, PPC970_Unit_FXU;
221 //===----------------------------------------------------------------------===//
222 // Fixed point instructions.
225 let PPC970_Unit = 1 in { // FXU Operations.
227 // Copies, extends, truncates.
228 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
229 "or $rA, $rS, $rB", IntGeneral,
231 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
232 "or $rA, $rS, $rB", IntGeneral,
235 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
236 "li $rD, $imm", IntGeneral,
237 [(set G8RC:$rD, immSExt16:$imm)]>;
238 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
239 "lis $rD, $imm", IntGeneral,
240 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
243 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
244 "nand $rA, $rS, $rB", IntGeneral,
245 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
246 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
247 "and $rA, $rS, $rB", IntGeneral,
248 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
249 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
250 "andc $rA, $rS, $rB", IntGeneral,
251 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
252 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
253 "or $rA, $rS, $rB", IntGeneral,
254 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
255 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
256 "nor $rA, $rS, $rB", IntGeneral,
257 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
258 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
259 "orc $rA, $rS, $rB", IntGeneral,
260 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
261 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
262 "eqv $rA, $rS, $rB", IntGeneral,
263 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
264 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
265 "xor $rA, $rS, $rB", IntGeneral,
266 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
268 // Logical ops with immediate.
269 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
270 "andi. $dst, $src1, $src2", IntGeneral,
271 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
273 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
274 "andis. $dst, $src1, $src2", IntGeneral,
275 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
277 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
278 "ori $dst, $src1, $src2", IntGeneral,
279 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
280 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
281 "oris $dst, $src1, $src2", IntGeneral,
282 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
283 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
284 "xori $dst, $src1, $src2", IntGeneral,
285 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
286 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
287 "xoris $dst, $src1, $src2", IntGeneral,
288 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
290 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
291 "add $rT, $rA, $rB", IntGeneral,
292 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
294 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
295 "addc $rT, $rA, $rB", IntGeneral,
296 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
297 PPC970_DGroup_Cracked;
298 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
299 "adde $rT, $rA, $rB", IntGeneral,
300 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
302 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
303 "addi $rD, $rA, $imm", IntGeneral,
304 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
305 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
306 "addis $rD, $rA, $imm", IntGeneral,
307 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
309 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
310 "subfic $rD, $rA, $imm", IntGeneral,
311 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
312 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
313 "subf $rT, $rA, $rB", IntGeneral,
314 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
316 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
317 "subfc $rT, $rA, $rB", IntGeneral,
318 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
319 PPC970_DGroup_Cracked;
321 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
322 "subfe $rT, $rA, $rB", IntGeneral,
323 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
324 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
325 "addme $rT, $rA", IntGeneral,
326 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
327 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
328 "addze $rT, $rA", IntGeneral,
329 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
330 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
331 "neg $rT, $rA", IntGeneral,
332 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
333 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
334 "subfme $rT, $rA", IntGeneral,
335 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
336 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
337 "subfze $rT, $rA", IntGeneral,
338 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
342 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
343 "mulhd $rT, $rA, $rB", IntMulHW,
344 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
345 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
346 "mulhdu $rT, $rA, $rB", IntMulHWU,
347 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
349 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
350 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
351 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
352 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
353 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
354 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
355 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
356 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
358 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
359 "sld $rA, $rS, $rB", IntRotateD,
360 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
361 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
362 "srd $rA, $rS, $rB", IntRotateD,
363 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
364 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
365 "srad $rA, $rS, $rB", IntRotateD,
366 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
368 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
369 "extsb $rA, $rS", IntGeneral,
370 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
371 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
372 "extsh $rA, $rS", IntGeneral,
373 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
375 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
376 "extsw $rA, $rS", IntGeneral,
377 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
378 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
379 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
380 "extsw $rA, $rS", IntGeneral,
381 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
382 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
383 "extsw $rA, $rS", IntGeneral,
384 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
386 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
387 "sradi $rA, $rS, $SH", IntRotateD,
388 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
389 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
390 "cntlzd $rA, $rS", IntGeneral,
391 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
393 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
394 "divd $rT, $rA, $rB", IntDivD,
395 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
396 PPC970_DGroup_First, PPC970_DGroup_Cracked;
397 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
398 "divdu $rT, $rA, $rB", IntDivD,
399 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
400 PPC970_DGroup_First, PPC970_DGroup_Cracked;
401 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
402 "mulld $rT, $rA, $rB", IntMulHD,
403 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
406 let isCommutable = 1 in {
407 def RLDIMI : MDForm_1<30, 3,
408 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
409 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
410 []>, isPPC64, RegConstraint<"$rSi = $rA">,
414 // Rotate instructions.
415 def RLDCL : MDForm_1<30, 0,
416 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
417 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
419 def RLDICL : MDForm_1<30, 0,
420 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
421 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
423 def RLDICR : MDForm_1<30, 1,
424 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
425 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
427 } // End FXU Operations.
430 //===----------------------------------------------------------------------===//
431 // Load/Store instructions.
435 // Sign extending loads.
436 let isSimpleLoad = 1, PPC970_Unit = 2 in {
437 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
438 "lha $rD, $src", LdStLHA,
439 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
440 PPC970_DGroup_Cracked;
441 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
442 "lwa $rD, $src", LdStLWA,
443 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
444 PPC970_DGroup_Cracked;
445 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
446 "lhax $rD, $src", LdStLHA,
447 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
448 PPC970_DGroup_Cracked;
449 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
450 "lwax $rD, $src", LdStLHA,
451 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
452 PPC970_DGroup_Cracked;
455 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
457 "lhau $rD, $disp($rA)", LdStGeneral,
458 []>, RegConstraint<"$rA = $ea_result">,
459 NoEncode<"$ea_result">;
464 // Zero extending loads.
465 let isSimpleLoad = 1, PPC970_Unit = 2 in {
466 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
467 "lbz $rD, $src", LdStGeneral,
468 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
469 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
470 "lhz $rD, $src", LdStGeneral,
471 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
472 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
473 "lwz $rD, $src", LdStGeneral,
474 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
476 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
477 "lbzx $rD, $src", LdStGeneral,
478 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
479 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
480 "lhzx $rD, $src", LdStGeneral,
481 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
482 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
483 "lwzx $rD, $src", LdStGeneral,
484 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
488 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
489 "lbzu $rD, $addr", LdStGeneral,
490 []>, RegConstraint<"$addr.reg = $ea_result">,
491 NoEncode<"$ea_result">;
492 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
493 "lhzu $rD, $addr", LdStGeneral,
494 []>, RegConstraint<"$addr.reg = $ea_result">,
495 NoEncode<"$ea_result">;
496 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
497 "lwzu $rD, $addr", LdStGeneral,
498 []>, RegConstraint<"$addr.reg = $ea_result">,
499 NoEncode<"$ea_result">;
503 // Full 8-byte loads.
504 let isSimpleLoad = 1, PPC970_Unit = 2 in {
505 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
506 "ld $rD, $src", LdStLD,
507 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
508 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
509 "ldx $rD, $src", LdStLD,
510 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
512 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
513 "ldu $rD, $addr", LdStLD,
514 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
515 NoEncode<"$ea_result">;
519 let PPC970_Unit = 2 in {
520 // Truncating stores.
521 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
522 "stb $rS, $src", LdStGeneral,
523 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
524 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
525 "sth $rS, $src", LdStGeneral,
526 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
527 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
528 "stw $rS, $src", LdStGeneral,
529 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
530 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
531 "stbx $rS, $dst", LdStGeneral,
532 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
533 PPC970_DGroup_Cracked;
534 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
535 "sthx $rS, $dst", LdStGeneral,
536 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
537 PPC970_DGroup_Cracked;
538 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
539 "stwx $rS, $dst", LdStGeneral,
540 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
541 PPC970_DGroup_Cracked;
542 // Normal 8-byte stores.
543 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
544 "std $rS, $dst", LdStSTD,
545 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
546 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
547 "stdx $rS, $dst", LdStSTD,
548 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
549 PPC970_DGroup_Cracked;
552 let PPC970_Unit = 2 in {
554 def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
555 symbolLo:$ptroff, ptr_rc:$ptrreg),
556 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
557 [(set ptr_rc:$ea_res,
558 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
559 iaddroff:$ptroff))]>,
560 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
561 def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
562 symbolLo:$ptroff, ptr_rc:$ptrreg),
563 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
564 [(set ptr_rc:$ea_res,
565 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
566 iaddroff:$ptroff))]>,
567 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
568 def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
569 symbolLo:$ptroff, ptr_rc:$ptrreg),
570 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
571 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
572 iaddroff:$ptroff))]>,
573 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
576 def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
577 s16immX4:$ptroff, ptr_rc:$ptrreg),
578 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
579 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
580 iaddroff:$ptroff))]>,
581 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
585 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
586 "stdux $rS, $dst", LdStSTD,
589 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
590 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
591 "std $rT, $dst", LdStSTD,
592 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
593 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
594 "stdx $rT, $dst", LdStSTD,
595 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
596 PPC970_DGroup_Cracked;
601 //===----------------------------------------------------------------------===//
602 // Floating point instructions.
606 let PPC970_Unit = 3 in { // FPU Operations.
607 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
608 "fcfid $frD, $frB", FPGeneral,
609 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
610 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
611 "fctidz $frD, $frB", FPGeneral,
612 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
616 //===----------------------------------------------------------------------===//
617 // Instruction Patterns
620 // Extensions and truncates to/from 32-bit regs.
621 def : Pat<(i64 (zext GPRC:$in)),
622 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
623 def : Pat<(i64 (anyext GPRC:$in)),
624 (OR4To8 GPRC:$in, GPRC:$in)>;
625 def : Pat<(i32 (trunc G8RC:$in)),
626 (OR8To4 G8RC:$in, G8RC:$in)>;
628 // Extending loads with i64 targets.
629 def : Pat<(zextloadi1 iaddr:$src),
631 def : Pat<(zextloadi1 xaddr:$src),
633 def : Pat<(extloadi1 iaddr:$src),
635 def : Pat<(extloadi1 xaddr:$src),
637 def : Pat<(extloadi8 iaddr:$src),
639 def : Pat<(extloadi8 xaddr:$src),
641 def : Pat<(extloadi16 iaddr:$src),
643 def : Pat<(extloadi16 xaddr:$src),
645 def : Pat<(extloadi32 iaddr:$src),
647 def : Pat<(extloadi32 xaddr:$src),
650 // Standard shifts. These are represented separately from the real shifts above
651 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
653 def : Pat<(sra G8RC:$rS, GPRC:$rB),
654 (SRAD G8RC:$rS, GPRC:$rB)>;
655 def : Pat<(srl G8RC:$rS, GPRC:$rB),
656 (SRD G8RC:$rS, GPRC:$rB)>;
657 def : Pat<(shl G8RC:$rS, GPRC:$rB),
658 (SLD G8RC:$rS, GPRC:$rB)>;
661 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
662 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
663 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
664 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
667 def : Pat<(rotl G8RC:$in, GPRC:$sh),
668 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
669 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
670 (RLDICL G8RC:$in, imm:$imm, 0)>;
672 // Hi and Lo for Darwin Global Addresses.
673 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
674 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
675 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
676 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
677 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
678 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
679 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
680 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
681 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
682 (ADDIS8 G8RC:$in, tconstpool:$g)>;
683 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
684 (ADDIS8 G8RC:$in, tjumptable:$g)>;