1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
65 let isCall = 1, PPC970_Unit = 7,
66 // All calls clobber the PPC64 non-callee saved registers.
67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
71 CR0,CR1,CR5,CR6,CR7] in {
72 // Convenient aliases for call instructions
73 def BL8_Macho : IForm<18, 0, 1,
74 (outs), (ins calltarget:$func, variable_ops),
75 "bl $func", BrB, []>; // See Pat patterns below.
76 def BLA8_Macho : IForm<18, 1, 1,
77 (outs), (ins aaddr:$func, variable_ops),
78 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
79 def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
80 (outs), (ins variable_ops),
82 [(PPCbctrl_Macho)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Macho ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7,
88 // All calls clobber the PPC64 non-callee saved registers.
89 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
90 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
91 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
93 CR0,CR1,CR5,CR6,CR7] in {
94 // Convenient aliases for call instructions
95 def BL8_ELF : IForm<18, 0, 1,
96 (outs), (ins calltarget:$func, variable_ops),
97 "bl $func", BrB, []>; // See Pat patterns below.
98 def BLA8_ELF : IForm<18, 1, 1,
99 (outs), (ins aaddr:$func, variable_ops),
100 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
101 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
102 (outs), (ins variable_ops),
104 [(PPCbctrl_ELF)]>, Requires<[In64BitMode]>;
109 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
110 (BL8_Macho tglobaladdr:$dst)>;
111 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
112 (BL8_Macho texternalsym:$dst)>;
114 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
115 (BL8_ELF tglobaladdr:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
117 (BL8_ELF texternalsym:$dst)>;
120 let usesCustomDAGSchedInserter = 1 in {
121 let Uses = [CR0] in {
122 def ATOMIC_LOAD_ADD_I64 : Pseudo<
123 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr),
124 "${:comment} ATOMIC_LOAD_ADD_I64 PSEUDO!",
125 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
126 def ATOMIC_CMP_SWAP_I64 : Pseudo<
127 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new),
128 "${:comment} ATOMIC_CMP_SWAP_I64 PSEUDO!",
130 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
131 def ATOMIC_SWAP_I64 : Pseudo<
132 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new),
133 "${:comment} ATOMIC_SWAP_I64 PSEUDO!",
134 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
138 // Instructions to support atomic operations
139 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
140 "ldarx $rD, $ptr", LdStLDARX,
141 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
144 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
145 "stdcx. $rS, $dst", LdStSTDCX,
146 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
149 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
150 def TCRETURNdi8 :Pseudo< (outs),
151 (ins calltarget:$dst, i32imm:$offset, variable_ops),
152 "#TC_RETURNd8 $dst $offset",
155 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
156 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
157 "#TC_RETURNa8 $func $offset",
158 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
160 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
161 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
162 "#TC_RETURNr8 $dst $offset",
166 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
167 isIndirectBranch = 1, isCall = 1, isReturn = 1 in
168 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
169 Requires<[In64BitMode]>;
173 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
174 isBarrier = 1, isCall = 1, isReturn = 1 in
175 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
180 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
181 isBarrier = 1, isCall = 1, isReturn = 1 in
182 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
186 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
187 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
189 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
190 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
192 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
193 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
196 //===----------------------------------------------------------------------===//
197 // 64-bit SPR manipulation instrs.
199 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
200 "mfctr $rT", SprMFSPR>,
201 PPC970_DGroup_First, PPC970_Unit_FXU;
202 let Pattern = [(PPCmtctr G8RC:$rS)] in {
203 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
204 "mtctr $rS", SprMTSPR>,
205 PPC970_DGroup_First, PPC970_Unit_FXU;
208 let Defs = [X1], Uses = [X1] in
209 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
210 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
212 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
214 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
215 "mtlr $rS", SprMTSPR>,
216 PPC970_DGroup_First, PPC970_Unit_FXU;
217 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
218 "mflr $rT", SprMFSPR>,
219 PPC970_DGroup_First, PPC970_Unit_FXU;
222 //===----------------------------------------------------------------------===//
223 // Fixed point instructions.
226 let PPC970_Unit = 1 in { // FXU Operations.
228 // Copies, extends, truncates.
229 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
230 "or $rA, $rS, $rB", IntGeneral,
232 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
233 "or $rA, $rS, $rB", IntGeneral,
236 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
237 "li $rD, $imm", IntGeneral,
238 [(set G8RC:$rD, immSExt16:$imm)]>;
239 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
240 "lis $rD, $imm", IntGeneral,
241 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
244 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
245 "nand $rA, $rS, $rB", IntGeneral,
246 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
247 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
248 "and $rA, $rS, $rB", IntGeneral,
249 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
250 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
251 "andc $rA, $rS, $rB", IntGeneral,
252 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
253 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
254 "or $rA, $rS, $rB", IntGeneral,
255 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
256 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
257 "nor $rA, $rS, $rB", IntGeneral,
258 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
259 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
260 "orc $rA, $rS, $rB", IntGeneral,
261 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
262 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
263 "eqv $rA, $rS, $rB", IntGeneral,
264 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
265 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
266 "xor $rA, $rS, $rB", IntGeneral,
267 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
269 // Logical ops with immediate.
270 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
271 "andi. $dst, $src1, $src2", IntGeneral,
272 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
274 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
275 "andis. $dst, $src1, $src2", IntGeneral,
276 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
278 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
279 "ori $dst, $src1, $src2", IntGeneral,
280 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
281 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
282 "oris $dst, $src1, $src2", IntGeneral,
283 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
284 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
285 "xori $dst, $src1, $src2", IntGeneral,
286 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
287 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
288 "xoris $dst, $src1, $src2", IntGeneral,
289 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
291 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
292 "add $rT, $rA, $rB", IntGeneral,
293 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
295 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
296 "addc $rT, $rA, $rB", IntGeneral,
297 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
298 PPC970_DGroup_Cracked;
299 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
300 "adde $rT, $rA, $rB", IntGeneral,
301 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
303 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
304 "addi $rD, $rA, $imm", IntGeneral,
305 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
306 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
307 "addis $rD, $rA, $imm", IntGeneral,
308 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
310 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
311 "subfic $rD, $rA, $imm", IntGeneral,
312 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
313 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
314 "subf $rT, $rA, $rB", IntGeneral,
315 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
317 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
318 "subfc $rT, $rA, $rB", IntGeneral,
319 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
320 PPC970_DGroup_Cracked;
322 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
323 "subfe $rT, $rA, $rB", IntGeneral,
324 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
325 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
326 "addme $rT, $rA", IntGeneral,
327 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
328 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
329 "addze $rT, $rA", IntGeneral,
330 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
331 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
332 "neg $rT, $rA", IntGeneral,
333 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
334 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
335 "subfme $rT, $rA", IntGeneral,
336 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
337 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
338 "subfze $rT, $rA", IntGeneral,
339 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
343 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
344 "mulhd $rT, $rA, $rB", IntMulHW,
345 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
346 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
347 "mulhdu $rT, $rA, $rB", IntMulHWU,
348 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
350 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
351 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
352 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
353 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
354 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
355 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
356 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
357 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
359 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
360 "sld $rA, $rS, $rB", IntRotateD,
361 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
362 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
363 "srd $rA, $rS, $rB", IntRotateD,
364 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
365 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
366 "srad $rA, $rS, $rB", IntRotateD,
367 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
369 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
370 "extsb $rA, $rS", IntGeneral,
371 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
372 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
373 "extsh $rA, $rS", IntGeneral,
374 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
376 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
377 "extsw $rA, $rS", IntGeneral,
378 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
379 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
380 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
381 "extsw $rA, $rS", IntGeneral,
382 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
383 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
384 "extsw $rA, $rS", IntGeneral,
385 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
387 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
388 "sradi $rA, $rS, $SH", IntRotateD,
389 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
390 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
391 "cntlzd $rA, $rS", IntGeneral,
392 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
394 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
395 "divd $rT, $rA, $rB", IntDivD,
396 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
397 PPC970_DGroup_First, PPC970_DGroup_Cracked;
398 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
399 "divdu $rT, $rA, $rB", IntDivD,
400 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
401 PPC970_DGroup_First, PPC970_DGroup_Cracked;
402 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
403 "mulld $rT, $rA, $rB", IntMulHD,
404 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
407 let isCommutable = 1 in {
408 def RLDIMI : MDForm_1<30, 3,
409 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
410 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
411 []>, isPPC64, RegConstraint<"$rSi = $rA">,
415 // Rotate instructions.
416 def RLDCL : MDForm_1<30, 0,
417 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
418 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
420 def RLDICL : MDForm_1<30, 0,
421 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
422 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
424 def RLDICR : MDForm_1<30, 1,
425 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
426 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
428 } // End FXU Operations.
431 //===----------------------------------------------------------------------===//
432 // Load/Store instructions.
436 // Sign extending loads.
437 let isSimpleLoad = 1, PPC970_Unit = 2 in {
438 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
439 "lha $rD, $src", LdStLHA,
440 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
441 PPC970_DGroup_Cracked;
442 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
443 "lwa $rD, $src", LdStLWA,
444 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
445 PPC970_DGroup_Cracked;
446 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
447 "lhax $rD, $src", LdStLHA,
448 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
449 PPC970_DGroup_Cracked;
450 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
451 "lwax $rD, $src", LdStLHA,
452 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
453 PPC970_DGroup_Cracked;
456 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
458 "lhau $rD, $disp($rA)", LdStGeneral,
459 []>, RegConstraint<"$rA = $ea_result">,
460 NoEncode<"$ea_result">;
465 // Zero extending loads.
466 let isSimpleLoad = 1, PPC970_Unit = 2 in {
467 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
468 "lbz $rD, $src", LdStGeneral,
469 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
470 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
471 "lhz $rD, $src", LdStGeneral,
472 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
473 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
474 "lwz $rD, $src", LdStGeneral,
475 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
477 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
478 "lbzx $rD, $src", LdStGeneral,
479 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
480 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
481 "lhzx $rD, $src", LdStGeneral,
482 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
483 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
484 "lwzx $rD, $src", LdStGeneral,
485 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
489 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
490 "lbzu $rD, $addr", LdStGeneral,
491 []>, RegConstraint<"$addr.reg = $ea_result">,
492 NoEncode<"$ea_result">;
493 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
494 "lhzu $rD, $addr", LdStGeneral,
495 []>, RegConstraint<"$addr.reg = $ea_result">,
496 NoEncode<"$ea_result">;
497 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
498 "lwzu $rD, $addr", LdStGeneral,
499 []>, RegConstraint<"$addr.reg = $ea_result">,
500 NoEncode<"$ea_result">;
504 // Full 8-byte loads.
505 let isSimpleLoad = 1, PPC970_Unit = 2 in {
506 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
507 "ld $rD, $src", LdStLD,
508 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
509 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
510 "ldx $rD, $src", LdStLD,
511 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
513 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
514 "ldu $rD, $addr", LdStLD,
515 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
516 NoEncode<"$ea_result">;
520 let PPC970_Unit = 2 in {
521 // Truncating stores.
522 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
523 "stb $rS, $src", LdStGeneral,
524 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
525 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
526 "sth $rS, $src", LdStGeneral,
527 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
528 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
529 "stw $rS, $src", LdStGeneral,
530 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
531 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
532 "stbx $rS, $dst", LdStGeneral,
533 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
534 PPC970_DGroup_Cracked;
535 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
536 "sthx $rS, $dst", LdStGeneral,
537 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
538 PPC970_DGroup_Cracked;
539 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
540 "stwx $rS, $dst", LdStGeneral,
541 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
542 PPC970_DGroup_Cracked;
543 // Normal 8-byte stores.
544 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
545 "std $rS, $dst", LdStSTD,
546 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
547 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
548 "stdx $rS, $dst", LdStSTD,
549 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
550 PPC970_DGroup_Cracked;
553 let PPC970_Unit = 2 in {
555 def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
556 symbolLo:$ptroff, ptr_rc:$ptrreg),
557 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
558 [(set ptr_rc:$ea_res,
559 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
560 iaddroff:$ptroff))]>,
561 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
562 def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
563 symbolLo:$ptroff, ptr_rc:$ptrreg),
564 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
565 [(set ptr_rc:$ea_res,
566 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
567 iaddroff:$ptroff))]>,
568 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
569 def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
570 symbolLo:$ptroff, ptr_rc:$ptrreg),
571 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
572 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
573 iaddroff:$ptroff))]>,
574 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
577 def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
578 s16immX4:$ptroff, ptr_rc:$ptrreg),
579 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
580 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
581 iaddroff:$ptroff))]>,
582 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
586 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
587 "stdux $rS, $dst", LdStSTD,
590 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
591 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
592 "std $rT, $dst", LdStSTD,
593 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
594 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
595 "stdx $rT, $dst", LdStSTD,
596 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
597 PPC970_DGroup_Cracked;
602 //===----------------------------------------------------------------------===//
603 // Floating point instructions.
607 let PPC970_Unit = 3 in { // FPU Operations.
608 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
609 "fcfid $frD, $frB", FPGeneral,
610 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
611 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
612 "fctidz $frD, $frB", FPGeneral,
613 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
617 //===----------------------------------------------------------------------===//
618 // Instruction Patterns
621 // Extensions and truncates to/from 32-bit regs.
622 def : Pat<(i64 (zext GPRC:$in)),
623 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
624 def : Pat<(i64 (anyext GPRC:$in)),
625 (OR4To8 GPRC:$in, GPRC:$in)>;
626 def : Pat<(i32 (trunc G8RC:$in)),
627 (OR8To4 G8RC:$in, G8RC:$in)>;
629 // Extending loads with i64 targets.
630 def : Pat<(zextloadi1 iaddr:$src),
632 def : Pat<(zextloadi1 xaddr:$src),
634 def : Pat<(extloadi1 iaddr:$src),
636 def : Pat<(extloadi1 xaddr:$src),
638 def : Pat<(extloadi8 iaddr:$src),
640 def : Pat<(extloadi8 xaddr:$src),
642 def : Pat<(extloadi16 iaddr:$src),
644 def : Pat<(extloadi16 xaddr:$src),
646 def : Pat<(extloadi32 iaddr:$src),
648 def : Pat<(extloadi32 xaddr:$src),
651 // Standard shifts. These are represented separately from the real shifts above
652 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
654 def : Pat<(sra G8RC:$rS, GPRC:$rB),
655 (SRAD G8RC:$rS, GPRC:$rB)>;
656 def : Pat<(srl G8RC:$rS, GPRC:$rB),
657 (SRD G8RC:$rS, GPRC:$rB)>;
658 def : Pat<(shl G8RC:$rS, GPRC:$rB),
659 (SLD G8RC:$rS, GPRC:$rB)>;
662 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
663 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
664 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
665 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
668 def : Pat<(rotl G8RC:$in, GPRC:$sh),
669 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
670 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
671 (RLDICL G8RC:$in, imm:$imm, 0)>;
673 // Hi and Lo for Darwin Global Addresses.
674 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
675 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
676 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
677 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
678 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
679 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
680 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
681 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
682 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
683 (ADDIS8 G8RC:$in, tconstpool:$g)>;
684 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
685 (ADDIS8 G8RC:$in, tjumptable:$g)>;