1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(outs G8RC:$rD), (ins),"; IMPLICIT_DEF_G8RC $rD",
61 [(set G8RC:$rD, (undef))]>;
64 //===----------------------------------------------------------------------===//
69 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
73 let isCall = 1, PPC970_Unit = 7,
74 // All calls clobber the PPC64 non-callee saved registers.
75 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
76 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
77 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
79 CR0,CR1,CR5,CR6,CR7] in {
80 // Convenient aliases for call instructions
81 def BL8_Macho : IForm<18, 0, 1,
82 (outs), (ins calltarget:$func, variable_ops),
83 "bl $func", BrB, []>; // See Pat patterns below.
85 def BLA8_Macho : IForm<18, 1, 1,
86 (outs), (ins aaddr:$func, variable_ops),
87 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
90 // ELF 64 ABI Calls = Macho ABI Calls
91 // Used to define BL8_ELF and BLA8_ELF
92 let isCall = 1, PPC970_Unit = 7,
93 // All calls clobber the PPC64 non-callee saved registers.
94 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
95 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
96 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
98 CR0,CR1,CR5,CR6,CR7] in {
99 // Convenient aliases for call instructions
100 def BL8_ELF : IForm<18, 0, 1,
101 (outs), (ins calltarget:$func, variable_ops),
102 "bl $func", BrB, []>; // See Pat patterns below.
104 def BLA8_ELF : IForm<18, 1, 1,
105 (outs), (ins aaddr:$func, variable_ops),
106 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
111 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
112 (BL8_Macho tglobaladdr:$dst)>;
113 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
114 (BL8_Macho texternalsym:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
117 (BL8_ELF tglobaladdr:$dst)>;
118 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
119 (BL8_ELF texternalsym:$dst)>;
121 //===----------------------------------------------------------------------===//
122 // 64-bit SPR manipulation instrs.
124 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
125 "mfctr $rT", SprMFSPR>,
126 PPC970_DGroup_First, PPC970_Unit_FXU;
127 let Pattern = [(PPCmtctr G8RC:$rS)] in {
128 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
129 "mtctr $rS", SprMTSPR>,
130 PPC970_DGroup_First, PPC970_Unit_FXU;
133 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
134 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
136 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
139 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
140 "mtlr $rS", SprMTSPR>,
141 PPC970_DGroup_First, PPC970_Unit_FXU;
142 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
143 "mflr $rT", SprMFSPR>,
144 PPC970_DGroup_First, PPC970_Unit_FXU;
147 //===----------------------------------------------------------------------===//
148 // Fixed point instructions.
151 let PPC970_Unit = 1 in { // FXU Operations.
153 // Copies, extends, truncates.
154 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
155 "or $rA, $rS, $rB", IntGeneral,
157 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
158 "or $rA, $rS, $rB", IntGeneral,
161 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
162 "li $rD, $imm", IntGeneral,
163 [(set G8RC:$rD, immSExt16:$imm)]>;
164 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
165 "lis $rD, $imm", IntGeneral,
166 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
169 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
170 "nand $rA, $rS, $rB", IntGeneral,
171 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
172 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
173 "and $rA, $rS, $rB", IntGeneral,
174 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
175 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
176 "andc $rA, $rS, $rB", IntGeneral,
177 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
178 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
179 "or $rA, $rS, $rB", IntGeneral,
180 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
181 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
182 "nor $rA, $rS, $rB", IntGeneral,
183 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
184 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
185 "orc $rA, $rS, $rB", IntGeneral,
186 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
187 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
188 "eqv $rA, $rS, $rB", IntGeneral,
189 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
190 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
191 "xor $rA, $rS, $rB", IntGeneral,
192 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
194 // Logical ops with immediate.
195 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
196 "andi. $dst, $src1, $src2", IntGeneral,
197 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
199 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
200 "andis. $dst, $src1, $src2", IntGeneral,
201 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
203 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
204 "ori $dst, $src1, $src2", IntGeneral,
205 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
206 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
207 "oris $dst, $src1, $src2", IntGeneral,
208 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
209 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
210 "xori $dst, $src1, $src2", IntGeneral,
211 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
212 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
213 "xoris $dst, $src1, $src2", IntGeneral,
214 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
216 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
217 "add $rT, $rA, $rB", IntGeneral,
218 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
220 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
221 "addc $rT, $rA, $rB", IntGeneral,
222 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
223 PPC970_DGroup_Cracked;
224 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
225 "adde $rT, $rA, $rB", IntGeneral,
226 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
228 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
229 "addi $rD, $rA, $imm", IntGeneral,
230 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
231 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
232 "addis $rD, $rA, $imm", IntGeneral,
233 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
235 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
236 "subfic $rD, $rA, $imm", IntGeneral,
237 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
238 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
239 "subf $rT, $rA, $rB", IntGeneral,
240 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
242 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
243 "subfc $rT, $rA, $rB", IntGeneral,
244 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
245 PPC970_DGroup_Cracked;
247 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
248 "subfe $rT, $rA, $rB", IntGeneral,
249 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
250 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
251 "addme $rT, $rA", IntGeneral,
252 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
253 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
254 "addze $rT, $rA", IntGeneral,
255 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
256 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
257 "neg $rT, $rA", IntGeneral,
258 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
259 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
260 "subfme $rT, $rA", IntGeneral,
261 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
262 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
263 "subfze $rT, $rA", IntGeneral,
264 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
268 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
269 "mulhd $rT, $rA, $rB", IntMulHW,
270 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
271 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
272 "mulhdu $rT, $rA, $rB", IntMulHWU,
273 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
275 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
276 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
277 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
278 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
279 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
280 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
281 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
282 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
284 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
285 "sld $rA, $rS, $rB", IntRotateD,
286 [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
287 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
288 "srd $rA, $rS, $rB", IntRotateD,
289 [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
290 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
291 "srad $rA, $rS, $rB", IntRotateD,
292 [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
294 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
295 "extsb $rA, $rS", IntGeneral,
296 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
297 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
298 "extsh $rA, $rS", IntGeneral,
299 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
301 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
302 "extsw $rA, $rS", IntGeneral,
303 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
304 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
305 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
306 "extsw $rA, $rS", IntGeneral,
307 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
308 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
309 "extsw $rA, $rS", IntGeneral,
310 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
312 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
313 "sradi $rA, $rS, $SH", IntRotateD,
314 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
315 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
316 "cntlzd $rA, $rS", IntGeneral,
317 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
319 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
320 "divd $rT, $rA, $rB", IntDivD,
321 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
322 PPC970_DGroup_First, PPC970_DGroup_Cracked;
323 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
324 "divdu $rT, $rA, $rB", IntDivD,
325 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
326 PPC970_DGroup_First, PPC970_DGroup_Cracked;
327 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
328 "mulld $rT, $rA, $rB", IntMulHD,
329 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
332 let isCommutable = 1 in {
333 def RLDIMI : MDForm_1<30, 3,
334 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
335 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
336 []>, isPPC64, RegConstraint<"$rSi = $rA">,
340 // Rotate instructions.
341 def RLDCL : MDForm_1<30, 0,
342 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
343 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
345 def RLDICL : MDForm_1<30, 0,
346 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
347 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
349 def RLDICR : MDForm_1<30, 1,
350 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
351 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
353 } // End FXU Operations.
356 //===----------------------------------------------------------------------===//
357 // Load/Store instructions.
361 // Sign extending loads.
362 let isLoad = 1, PPC970_Unit = 2 in {
363 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
364 "lha $rD, $src", LdStLHA,
365 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
366 PPC970_DGroup_Cracked;
367 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
368 "lwa $rD, $src", LdStLWA,
369 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
370 PPC970_DGroup_Cracked;
371 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
372 "lhax $rD, $src", LdStLHA,
373 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
374 PPC970_DGroup_Cracked;
375 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
376 "lwax $rD, $src", LdStLHA,
377 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
378 PPC970_DGroup_Cracked;
381 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
383 "lhau $rD, $disp($rA)", LdStGeneral,
384 []>, RegConstraint<"$rA = $ea_result">,
385 NoEncode<"$ea_result">;
390 // Zero extending loads.
391 let isLoad = 1, PPC970_Unit = 2 in {
392 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
393 "lbz $rD, $src", LdStGeneral,
394 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
395 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
396 "lhz $rD, $src", LdStGeneral,
397 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
398 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
399 "lwz $rD, $src", LdStGeneral,
400 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
402 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
403 "lbzx $rD, $src", LdStGeneral,
404 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
405 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
406 "lhzx $rD, $src", LdStGeneral,
407 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
408 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
409 "lwzx $rD, $src", LdStGeneral,
410 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
414 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
415 "lbzu $rD, $addr", LdStGeneral,
416 []>, RegConstraint<"$addr.reg = $ea_result">,
417 NoEncode<"$ea_result">;
418 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
419 "lhzu $rD, $addr", LdStGeneral,
420 []>, RegConstraint<"$addr.reg = $ea_result">,
421 NoEncode<"$ea_result">;
422 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
423 "lwzu $rD, $addr", LdStGeneral,
424 []>, RegConstraint<"$addr.reg = $ea_result">,
425 NoEncode<"$ea_result">;
429 // Full 8-byte loads.
430 let isLoad = 1, PPC970_Unit = 2 in {
431 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
432 "ld $rD, $src", LdStLD,
433 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
434 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
435 "ldx $rD, $src", LdStLD,
436 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
438 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
439 "ldu $rD, $addr", LdStLD,
440 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
441 NoEncode<"$ea_result">;
445 let isStore = 1, PPC970_Unit = 2 in {
446 // Truncating stores.
447 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
448 "stb $rS, $src", LdStGeneral,
449 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
450 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
451 "sth $rS, $src", LdStGeneral,
452 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
453 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
454 "stw $rS, $src", LdStGeneral,
455 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
456 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
457 "stbx $rS, $dst", LdStGeneral,
458 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
459 PPC970_DGroup_Cracked;
460 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
461 "sthx $rS, $dst", LdStGeneral,
462 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
463 PPC970_DGroup_Cracked;
464 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
465 "stwx $rS, $dst", LdStGeneral,
466 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
467 PPC970_DGroup_Cracked;
468 // Normal 8-byte stores.
469 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
470 "std $rS, $dst", LdStSTD,
471 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
472 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
473 "stdx $rS, $dst", LdStSTD,
474 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
475 PPC970_DGroup_Cracked;
478 let isStore = 1, PPC970_Unit = 2 in {
480 def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
481 symbolLo:$ptroff, ptr_rc:$ptrreg),
482 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
483 [(set ptr_rc:$ea_res,
484 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
485 iaddroff:$ptroff))]>,
486 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
487 def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
488 symbolLo:$ptroff, ptr_rc:$ptrreg),
489 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
490 [(set ptr_rc:$ea_res,
491 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
492 iaddroff:$ptroff))]>,
493 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
494 def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
495 symbolLo:$ptroff, ptr_rc:$ptrreg),
496 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
497 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
498 iaddroff:$ptroff))]>,
499 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
502 def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
503 s16immX4:$ptroff, ptr_rc:$ptrreg),
504 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
505 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
506 iaddroff:$ptroff))]>,
507 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
512 let isStore = 1, PPC970_Unit = 2 in {
514 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
515 "stdux $rS, $dst", LdStSTD,
519 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
520 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
521 "std $rT, $dst", LdStSTD,
522 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
523 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
524 "stdx $rT, $dst", LdStSTD,
525 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
526 PPC970_DGroup_Cracked;
531 //===----------------------------------------------------------------------===//
532 // Floating point instructions.
536 let PPC970_Unit = 3 in { // FPU Operations.
537 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
538 "fcfid $frD, $frB", FPGeneral,
539 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
540 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
541 "fctidz $frD, $frB", FPGeneral,
542 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
546 //===----------------------------------------------------------------------===//
547 // Instruction Patterns
550 // Extensions and truncates to/from 32-bit regs.
551 def : Pat<(i64 (zext GPRC:$in)),
552 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
553 def : Pat<(i64 (anyext GPRC:$in)),
554 (OR4To8 GPRC:$in, GPRC:$in)>;
555 def : Pat<(i32 (trunc G8RC:$in)),
556 (OR8To4 G8RC:$in, G8RC:$in)>;
558 // Extending loads with i64 targets.
559 def : Pat<(zextloadi1 iaddr:$src),
561 def : Pat<(zextloadi1 xaddr:$src),
563 def : Pat<(extloadi1 iaddr:$src),
565 def : Pat<(extloadi1 xaddr:$src),
567 def : Pat<(extloadi8 iaddr:$src),
569 def : Pat<(extloadi8 xaddr:$src),
571 def : Pat<(extloadi16 iaddr:$src),
573 def : Pat<(extloadi16 xaddr:$src),
575 def : Pat<(extloadi32 iaddr:$src),
577 def : Pat<(extloadi32 xaddr:$src),
581 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
582 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
583 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
584 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
587 def : Pat<(rotl G8RC:$in, GPRC:$sh),
588 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
589 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
590 (RLDICL G8RC:$in, imm:$imm, 0)>;
592 // Hi and Lo for Darwin Global Addresses.
593 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
594 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
595 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
596 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
597 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
598 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
599 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
600 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
601 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
602 (ADDIS8 G8RC:$in, tconstpool:$g)>;
603 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
604 (ADDIS8 G8RC:$in, tjumptable:$g)>;