1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
23 def u16imm64 : Operand<i64> {
24 let PrintMethod = "printU16ImmOperand";
25 let EncoderMethod = "getImm16Encoding";
26 let ParserMatchClass = PPCU16ImmAsmOperand;
28 def s17imm64 : Operand<i64> {
29 // This operand type is used for addis/lis to allow the assembler parser
30 // to accept immediates in the range -65536..65535 for compatibility with
31 // the GNU assembler. The operand is treated as 16-bit otherwise.
32 let PrintMethod = "printS16ImmOperand";
33 let EncoderMethod = "getImm16Encoding";
34 let ParserMatchClass = PPCS17ImmAsmOperand;
36 def tocentry : Operand<iPTR> {
37 let MIOperandInfo = (ops i64imm:$imm);
39 def PPCTLSRegOperand : AsmOperandClass {
40 let Name = "TLSReg"; let PredicateMethod = "isTLSReg";
41 let RenderMethod = "addTLSRegOperands";
43 def tlsreg : Operand<i64> {
44 let EncoderMethod = "getTLSRegEncoding";
45 let ParserMatchClass = PPCTLSRegOperand;
47 def tlsgd : Operand<i64> {}
48 def tlscall : Operand<i64> {
49 let PrintMethod = "printTLSCall";
50 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
51 let EncoderMethod = "getTLSCallEncoding";
54 //===----------------------------------------------------------------------===//
55 // 64-bit transformation functions.
58 def SHL64 : SDNodeXForm<imm, [{
59 // Transformation function: 63 - imm
60 return getI32Imm(63 - N->getZExtValue());
63 def SRL64 : SDNodeXForm<imm, [{
64 // Transformation function: 64 - imm
65 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
68 def HI32_48 : SDNodeXForm<imm, [{
69 // Transformation function: shift the immediate value down into the low bits.
70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
73 def HI48_64 : SDNodeXForm<imm, [{
74 // Transformation function: shift the immediate value down into the low bits.
75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
79 //===----------------------------------------------------------------------===//
83 let Interpretation64Bit = 1 in {
84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
85 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
87 Requires<[In64BitMode]>;
89 let isCodeGenOnly = 1 in
90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
91 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
92 Requires<[In64BitMode]>;
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
101 let Defs = [CTR8], Uses = [CTR8] in {
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
119 // Convenient aliases for call instructions
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
122 "bl $func", BrB, []>; // See Pat patterns below.
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
125 "bl $func", BrB, []>;
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
130 let Uses = [RM], isCodeGenOnly = 1 in {
131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
132 (outs), (ins calltarget:$func),
133 "bl $func\n\tnop", BrB, []>;
135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
136 (outs), (ins tlscall:$func),
137 "bl $func\n\tnop", BrB, []>;
139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
140 (outs), (ins abscalltarget:$func),
141 "bla $func\n\tnop", BrB,
142 [(PPCcall_nop (i64 imm:$func))]>;
144 let Uses = [CTR8, RM] in {
145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
146 "bctrl", BrB, [(PPCbctrl)]>,
147 Requires<[In64BitMode]>;
149 let isCodeGenOnly = 1 in
150 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
152 Requires<[In64BitMode]>;
155 } // Interpretation64Bit
158 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
159 (BL8 tglobaladdr:$dst)>;
160 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
161 (BL8_NOP tglobaladdr:$dst)>;
163 def : Pat<(PPCcall (i64 texternalsym:$dst)),
164 (BL8 texternalsym:$dst)>;
165 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
166 (BL8_NOP texternalsym:$dst)>;
169 let usesCustomInserter = 1 in {
170 let Defs = [CR0] in {
171 def ATOMIC_LOAD_ADD_I64 : Pseudo<
172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
173 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
174 def ATOMIC_LOAD_SUB_I64 : Pseudo<
175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
176 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
177 def ATOMIC_LOAD_OR_I64 : Pseudo<
178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
179 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
180 def ATOMIC_LOAD_XOR_I64 : Pseudo<
181 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
182 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
183 def ATOMIC_LOAD_AND_I64 : Pseudo<
184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
185 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
186 def ATOMIC_LOAD_NAND_I64 : Pseudo<
187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
188 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
190 def ATOMIC_CMP_SWAP_I64 : Pseudo<
191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
192 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
194 def ATOMIC_SWAP_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
196 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
200 // Instructions to support atomic operations
201 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
202 "ldarx $rD, $ptr", LdStLDARX,
203 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
206 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
207 "stdcx. $rS, $dst", LdStSTDCX,
208 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
211 let Interpretation64Bit = 1 in {
212 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
213 def TCRETURNdi8 :Pseudo< (outs),
214 (ins calltarget:$dst, i32imm:$offset),
215 "#TC_RETURNd8 $dst $offset",
218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
219 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
220 "#TC_RETURNa8 $func $offset",
221 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
224 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
225 "#TC_RETURNr8 $dst $offset",
228 let isCodeGenOnly = 1 in {
230 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
231 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
232 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
233 Requires<[In64BitMode]>;
236 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
237 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
238 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
243 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
244 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
245 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
250 } // Interpretation64Bit
252 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
253 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
255 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
256 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
258 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
259 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
262 // 64-bit CR instructions
263 let Interpretation64Bit = 1 in {
264 let neverHasSideEffects = 1 in {
265 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
266 "mtocrf $FXM, $ST", BrMCRX>,
267 PPC970_DGroup_First, PPC970_Unit_CRU;
269 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
270 "mtcrf $FXM, $rS", BrMCRX>,
271 PPC970_MicroCode, PPC970_Unit_CRU;
273 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
274 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
275 "mfocrf $rT, $FXM", SprMFCR>,
276 PPC970_DGroup_First, PPC970_Unit_CRU;
278 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
279 "mfcr $rT", SprMFCR>,
280 PPC970_MicroCode, PPC970_Unit_CRU;
281 } // neverHasSideEffects = 1
283 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
285 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
287 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
288 Requires<[In64BitMode]>;
289 let isTerminator = 1 in
290 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
291 "#EH_SJLJ_LONGJMP64",
292 [(PPCeh_sjlj_longjmp addr:$buf)]>,
293 Requires<[In64BitMode]>;
296 //===----------------------------------------------------------------------===//
297 // 64-bit SPR manipulation instrs.
299 let Uses = [CTR8] in {
300 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
301 "mfctr $rT", SprMFSPR>,
302 PPC970_DGroup_First, PPC970_Unit_FXU;
304 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
305 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
306 "mtctr $rS", SprMTSPR>,
307 PPC970_DGroup_First, PPC970_Unit_FXU;
309 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
310 let Pattern = [(int_ppc_mtctr i64:$rS)] in
311 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
312 "mtctr $rS", SprMTSPR>,
313 PPC970_DGroup_First, PPC970_Unit_FXU;
316 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
317 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
318 "mfspr $rT, 268", SprMFTB>,
319 PPC970_DGroup_First, PPC970_Unit_FXU;
320 // Note that encoding mftb using mfspr is now the preferred form,
321 // and has been since at least ISA v2.03. The mftb instruction has
322 // now been phased out. Using mfspr, however, is known not to work on
325 let Defs = [X1], Uses = [X1] in
326 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
328 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
330 let Defs = [LR8] in {
331 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
332 "mtlr $rS", SprMTSPR>,
333 PPC970_DGroup_First, PPC970_Unit_FXU;
335 let Uses = [LR8] in {
336 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
337 "mflr $rT", SprMFSPR>,
338 PPC970_DGroup_First, PPC970_Unit_FXU;
340 } // Interpretation64Bit
342 //===----------------------------------------------------------------------===//
343 // Fixed point instructions.
346 let PPC970_Unit = 1 in { // FXU Operations.
347 let Interpretation64Bit = 1 in {
348 let neverHasSideEffects = 1 in {
350 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
351 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
352 "li $rD, $imm", IntSimple,
353 [(set i64:$rD, imm64SExt16:$imm)]>;
354 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
355 "lis $rD, $imm", IntSimple,
356 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
360 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
361 "nand", "$rA, $rS, $rB", IntSimple,
362 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
363 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
364 "and", "$rA, $rS, $rB", IntSimple,
365 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
366 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
367 "andc", "$rA, $rS, $rB", IntSimple,
368 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
369 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
370 "or", "$rA, $rS, $rB", IntSimple,
371 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
372 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
373 "nor", "$rA, $rS, $rB", IntSimple,
374 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
375 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
376 "orc", "$rA, $rS, $rB", IntSimple,
377 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
378 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
379 "eqv", "$rA, $rS, $rB", IntSimple,
380 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
381 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
382 "xor", "$rA, $rS, $rB", IntSimple,
383 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
385 // Logical ops with immediate.
386 let Defs = [CR0] in {
387 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
388 "andi. $dst, $src1, $src2", IntGeneral,
389 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
391 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
392 "andis. $dst, $src1, $src2", IntGeneral,
393 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
396 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
397 "ori $dst, $src1, $src2", IntSimple,
398 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
399 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
400 "oris $dst, $src1, $src2", IntSimple,
401 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
402 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
403 "xori $dst, $src1, $src2", IntSimple,
404 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
405 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
406 "xoris $dst, $src1, $src2", IntSimple,
407 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
409 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
410 "add", "$rT, $rA, $rB", IntSimple,
411 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
412 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
413 // initial-exec thread-local storage model.
414 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
415 "add $rT, $rA, $rB", IntSimple,
416 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
418 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
419 "addc", "$rT, $rA, $rB", IntGeneral,
420 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
421 PPC970_DGroup_Cracked;
422 let Defs = [CARRY] in
423 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
424 "addic $rD, $rA, $imm", IntGeneral,
425 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
426 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
427 "addi $rD, $rA, $imm", IntSimple,
428 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
429 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
430 "addis $rD, $rA, $imm", IntSimple,
431 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
433 let Defs = [CARRY] in {
434 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
435 "subfic $rD, $rA, $imm", IntGeneral,
436 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
437 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
438 "subfc", "$rT, $rA, $rB", IntGeneral,
439 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
440 PPC970_DGroup_Cracked;
442 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
443 "subf", "$rT, $rA, $rB", IntGeneral,
444 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
445 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
446 "neg", "$rT, $rA", IntSimple,
447 [(set i64:$rT, (ineg i64:$rA))]>;
448 let Uses = [CARRY] in {
449 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
450 "adde", "$rT, $rA, $rB", IntGeneral,
451 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
452 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
453 "addme", "$rT, $rA", IntGeneral,
454 [(set i64:$rT, (adde i64:$rA, -1))]>;
455 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
456 "addze", "$rT, $rA", IntGeneral,
457 [(set i64:$rT, (adde i64:$rA, 0))]>;
458 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
459 "subfe", "$rT, $rA, $rB", IntGeneral,
460 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
461 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
462 "subfme", "$rT, $rA", IntGeneral,
463 [(set i64:$rT, (sube -1, i64:$rA))]>;
464 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
465 "subfze", "$rT, $rA", IntGeneral,
466 [(set i64:$rT, (sube 0, i64:$rA))]>;
470 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
471 "mulhd", "$rT, $rA, $rB", IntMulHW,
472 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
473 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
474 "mulhdu", "$rT, $rA, $rB", IntMulHWU,
475 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
477 } // Interpretation64Bit
479 let isCompare = 1, neverHasSideEffects = 1 in {
480 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
481 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
482 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
483 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
484 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
485 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
486 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
487 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
490 let neverHasSideEffects = 1 in {
491 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
492 "sld", "$rA, $rS, $rB", IntRotateD,
493 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
494 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
495 "srd", "$rA, $rS, $rB", IntRotateD,
496 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
497 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
498 "srad", "$rA, $rS, $rB", IntRotateD,
499 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
501 let Interpretation64Bit = 1 in {
502 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
503 "extsb", "$rA, $rS", IntSimple,
504 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
505 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
506 "extsh", "$rA, $rS", IntSimple,
507 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
508 } // Interpretation64Bit
511 let isCodeGenOnly = 1 in {
512 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
513 "extsb $rA, $rS", IntSimple, []>, isPPC64;
514 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
515 "extsh $rA, $rS", IntSimple, []>, isPPC64;
516 } // isCodeGenOnly for fast-isel
518 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
519 "extsw", "$rA, $rS", IntSimple,
520 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
521 let Interpretation64Bit = 1 in
522 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
523 "extsw", "$rA, $rS", IntSimple,
524 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
526 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
527 "sradi", "$rA, $rS, $SH", IntRotateDI,
528 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
529 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
530 "cntlzd", "$rA, $rS", IntGeneral,
531 [(set i64:$rA, (ctlz i64:$rS))]>;
532 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
533 "popcntd", "$rA, $rS", IntGeneral,
534 [(set i64:$rA, (ctpop i64:$rS))]>;
536 // popcntw also does a population count on the high 32 bits (storing the
537 // results in the high 32-bits of the output). We'll ignore that here (which is
538 // safe because we never separately use the high part of the 64-bit registers).
539 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
540 "popcntw", "$rA, $rS", IntGeneral,
541 [(set i32:$rA, (ctpop i32:$rS))]>;
543 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
544 "divd", "$rT, $rA, $rB", IntDivD,
545 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
546 PPC970_DGroup_First, PPC970_DGroup_Cracked;
547 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
548 "divdu", "$rT, $rA, $rB", IntDivD,
549 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
550 PPC970_DGroup_First, PPC970_DGroup_Cracked;
551 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
552 "mulld", "$rT, $rA, $rB", IntMulHD,
553 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
554 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
555 "mulli $rD, $rA, $imm", IntMulLI,
556 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
559 let neverHasSideEffects = 1 in {
560 let isCommutable = 1 in {
561 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
562 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
563 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
564 []>, isPPC64, RegConstraint<"$rSi = $rA">,
568 // Rotate instructions.
569 defm RLDCL : MDSForm_1r<30, 8,
570 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
571 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
573 defm RLDCR : MDSForm_1r<30, 9,
574 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
575 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
577 defm RLDICL : MDForm_1r<30, 0,
578 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
579 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
582 let isCodeGenOnly = 1 in
583 def RLDICL_32_64 : MDForm_1<30, 0,
585 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
586 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
589 defm RLDICR : MDForm_1r<30, 1,
590 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
591 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
593 defm RLDIC : MDForm_1r<30, 2,
594 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
595 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
598 let Interpretation64Bit = 1 in {
599 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
600 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
601 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
605 def ISEL8 : AForm_4<31, 15,
606 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
607 "isel $rT, $rA, $rB, $cond", IntGeneral,
609 } // Interpretation64Bit
610 } // neverHasSideEffects = 1
611 } // End FXU Operations.
614 //===----------------------------------------------------------------------===//
615 // Load/Store instructions.
619 // Sign extending loads.
620 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
621 let Interpretation64Bit = 1 in
622 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
623 "lha $rD, $src", LdStLHA,
624 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
625 PPC970_DGroup_Cracked;
626 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
627 "lwa $rD, $src", LdStLWA,
629 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
630 PPC970_DGroup_Cracked;
631 let Interpretation64Bit = 1 in
632 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
633 "lhax $rD, $src", LdStLHA,
634 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
635 PPC970_DGroup_Cracked;
636 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
637 "lwax $rD, $src", LdStLHA,
638 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
639 PPC970_DGroup_Cracked;
641 let isCodeGenOnly = 1, mayLoad = 1 in {
642 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
643 "lwa $rD, $src", LdStLWA, []>, isPPC64,
644 PPC970_DGroup_Cracked;
645 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
646 "lwax $rD, $src", LdStLHA, []>, isPPC64,
647 PPC970_DGroup_Cracked;
648 } // end fast-isel isCodeGenOnly
651 let mayLoad = 1, neverHasSideEffects = 1 in {
652 let Interpretation64Bit = 1 in
653 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
655 "lhau $rD, $addr", LdStLHAU,
656 []>, RegConstraint<"$addr.reg = $ea_result">,
657 NoEncode<"$ea_result">;
660 let Interpretation64Bit = 1 in
661 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
663 "lhaux $rD, $addr", LdStLHAU,
664 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
665 NoEncode<"$ea_result">;
666 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
668 "lwaux $rD, $addr", LdStLHAU,
669 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
670 NoEncode<"$ea_result">, isPPC64;
674 let Interpretation64Bit = 1 in {
675 // Zero extending loads.
676 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
677 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
678 "lbz $rD, $src", LdStLoad,
679 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
680 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
681 "lhz $rD, $src", LdStLoad,
682 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
683 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
684 "lwz $rD, $src", LdStLoad,
685 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
687 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
688 "lbzx $rD, $src", LdStLoad,
689 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
690 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
691 "lhzx $rD, $src", LdStLoad,
692 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
693 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
694 "lwzx $rD, $src", LdStLoad,
695 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
699 let mayLoad = 1, neverHasSideEffects = 1 in {
700 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
701 "lbzu $rD, $addr", LdStLoadUpd,
702 []>, RegConstraint<"$addr.reg = $ea_result">,
703 NoEncode<"$ea_result">;
704 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
705 "lhzu $rD, $addr", LdStLoadUpd,
706 []>, RegConstraint<"$addr.reg = $ea_result">,
707 NoEncode<"$ea_result">;
708 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
709 "lwzu $rD, $addr", LdStLoadUpd,
710 []>, RegConstraint<"$addr.reg = $ea_result">,
711 NoEncode<"$ea_result">;
713 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
715 "lbzux $rD, $addr", LdStLoadUpd,
716 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
717 NoEncode<"$ea_result">;
718 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
720 "lhzux $rD, $addr", LdStLoadUpd,
721 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
722 NoEncode<"$ea_result">;
723 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
725 "lwzux $rD, $addr", LdStLoadUpd,
726 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
727 NoEncode<"$ea_result">;
730 } // Interpretation64Bit
733 // Full 8-byte loads.
734 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
735 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
736 "ld $rD, $src", LdStLD,
737 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
738 // The following three definitions are selected for small code model only.
739 // Otherwise, we need to create two instructions to form a 32-bit offset,
740 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
741 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
744 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
745 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
748 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
749 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
752 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
754 let hasSideEffects = 1, isCodeGenOnly = 1 in {
755 let RST = 2, DS = 2 in
756 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
757 "ld 2, 8($reg)", LdStLD,
758 [(PPCload_toc i64:$reg)]>, isPPC64;
760 let RST = 2, DS = 10, RA = 1 in
761 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
762 "ld 2, 40(1)", LdStLD,
763 [(PPCtoc_restore)]>, isPPC64;
765 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
766 "ldx $rD, $src", LdStLD,
767 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
768 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
769 "ldbrx $rD, $src", LdStLoad,
770 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
772 let mayLoad = 1, neverHasSideEffects = 1 in {
773 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
774 "ldu $rD, $addr", LdStLDU,
775 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
776 NoEncode<"$ea_result">;
778 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
780 "ldux $rD, $addr", LdStLDU,
781 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
782 NoEncode<"$ea_result">, isPPC64;
786 def : Pat<(PPCload ixaddr:$src),
788 def : Pat<(PPCload xaddr:$src),
791 // Support for medium and large code model.
792 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
795 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
797 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
800 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
801 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
804 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
806 // Support for thread-local storage.
807 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
810 (PPCaddisGotTprelHA i64:$reg,
811 tglobaltlsaddr:$disp))]>,
813 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
816 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
818 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
819 (ADD8TLS $in, tglobaltlsaddr:$g)>;
820 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
823 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
825 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
828 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
830 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
833 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
835 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
838 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
840 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
843 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
845 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
848 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
850 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
853 (PPCaddisDtprelHA i64:$reg,
854 tglobaltlsaddr:$disp))]>,
856 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
859 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
862 let PPC970_Unit = 2 in {
863 let Interpretation64Bit = 1 in {
864 // Truncating stores.
865 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
866 "stb $rS, $src", LdStStore,
867 [(truncstorei8 i64:$rS, iaddr:$src)]>;
868 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
869 "sth $rS, $src", LdStStore,
870 [(truncstorei16 i64:$rS, iaddr:$src)]>;
871 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
872 "stw $rS, $src", LdStStore,
873 [(truncstorei32 i64:$rS, iaddr:$src)]>;
874 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
875 "stbx $rS, $dst", LdStStore,
876 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
877 PPC970_DGroup_Cracked;
878 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
879 "sthx $rS, $dst", LdStStore,
880 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
881 PPC970_DGroup_Cracked;
882 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
883 "stwx $rS, $dst", LdStStore,
884 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
885 PPC970_DGroup_Cracked;
886 } // Interpretation64Bit
888 // Normal 8-byte stores.
889 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
890 "std $rS, $dst", LdStSTD,
891 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
892 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
893 "stdx $rS, $dst", LdStSTD,
894 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
895 PPC970_DGroup_Cracked;
896 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
897 "stdbrx $rS, $dst", LdStStore,
898 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
899 PPC970_DGroup_Cracked;
902 // Stores with Update (pre-inc).
903 let PPC970_Unit = 2, mayStore = 1 in {
904 let Interpretation64Bit = 1 in {
905 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
906 "stbu $rS, $dst", LdStStoreUpd, []>,
907 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
908 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
909 "sthu $rS, $dst", LdStStoreUpd, []>,
910 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
911 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
912 "stwu $rS, $dst", LdStStoreUpd, []>,
913 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
914 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
915 "stdu $rS, $dst", LdStSTDU, []>,
916 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
919 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
920 "stbux $rS, $dst", LdStStoreUpd, []>,
921 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
922 PPC970_DGroup_Cracked;
923 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
924 "sthux $rS, $dst", LdStStoreUpd, []>,
925 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
926 PPC970_DGroup_Cracked;
927 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
928 "stwux $rS, $dst", LdStStoreUpd, []>,
929 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
930 PPC970_DGroup_Cracked;
931 } // Interpretation64Bit
933 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
934 "stdux $rS, $dst", LdStSTDU, []>,
935 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
936 PPC970_DGroup_Cracked, isPPC64;
939 // Patterns to match the pre-inc stores. We can't put the patterns on
940 // the instruction definitions directly as ISel wants the address base
941 // and offset to be separate operands, not a single complex operand.
942 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
943 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
944 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
945 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
946 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
947 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
948 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
949 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
951 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
952 (STBUX8 $rS, $ptrreg, $ptroff)>;
953 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
954 (STHUX8 $rS, $ptrreg, $ptroff)>;
955 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
956 (STWUX8 $rS, $ptrreg, $ptroff)>;
957 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
958 (STDUX $rS, $ptrreg, $ptroff)>;
961 //===----------------------------------------------------------------------===//
962 // Floating point instructions.
966 let PPC970_Unit = 3, neverHasSideEffects = 1,
967 Uses = [RM] in { // FPU Operations.
968 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
969 "fcfid", "$frD, $frB", FPGeneral,
970 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
971 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
972 "fctidz", "$frD, $frB", FPGeneral,
973 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
975 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
976 "fcfidu", "$frD, $frB", FPGeneral,
977 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
978 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
979 "fcfids", "$frD, $frB", FPGeneral,
980 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
981 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
982 "fcfidus", "$frD, $frB", FPGeneral,
983 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
984 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
985 "fctiduz", "$frD, $frB", FPGeneral,
986 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
987 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
988 "fctiwuz", "$frD, $frB", FPGeneral,
989 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
993 //===----------------------------------------------------------------------===//
994 // Instruction Patterns
997 // Extensions and truncates to/from 32-bit regs.
998 def : Pat<(i64 (zext i32:$in)),
999 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1001 def : Pat<(i64 (anyext i32:$in)),
1002 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1003 def : Pat<(i32 (trunc i64:$in)),
1004 (EXTRACT_SUBREG $in, sub_32)>;
1006 // Extending loads with i64 targets.
1007 def : Pat<(zextloadi1 iaddr:$src),
1009 def : Pat<(zextloadi1 xaddr:$src),
1010 (LBZX8 xaddr:$src)>;
1011 def : Pat<(extloadi1 iaddr:$src),
1013 def : Pat<(extloadi1 xaddr:$src),
1014 (LBZX8 xaddr:$src)>;
1015 def : Pat<(extloadi8 iaddr:$src),
1017 def : Pat<(extloadi8 xaddr:$src),
1018 (LBZX8 xaddr:$src)>;
1019 def : Pat<(extloadi16 iaddr:$src),
1021 def : Pat<(extloadi16 xaddr:$src),
1022 (LHZX8 xaddr:$src)>;
1023 def : Pat<(extloadi32 iaddr:$src),
1025 def : Pat<(extloadi32 xaddr:$src),
1026 (LWZX8 xaddr:$src)>;
1028 // Standard shifts. These are represented separately from the real shifts above
1029 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1031 def : Pat<(sra i64:$rS, i32:$rB),
1033 def : Pat<(srl i64:$rS, i32:$rB),
1035 def : Pat<(shl i64:$rS, i32:$rB),
1039 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1040 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1041 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1042 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1045 def : Pat<(rotl i64:$in, i32:$sh),
1046 (RLDCL $in, $sh, 0)>;
1047 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1048 (RLDICL $in, imm:$imm, 0)>;
1050 // Hi and Lo for Darwin Global Addresses.
1051 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1052 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1053 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1054 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1055 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1056 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1057 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1058 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1059 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1060 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1061 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1062 (ADDI8 $in, tglobaltlsaddr:$g)>;
1063 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1064 (ADDIS8 $in, tglobaladdr:$g)>;
1065 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1066 (ADDIS8 $in, tconstpool:$g)>;
1067 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1068 (ADDIS8 $in, tjumptable:$g)>;
1069 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1070 (ADDIS8 $in, tblockaddress:$g)>;
1072 // Patterns to match r+r indexed loads and stores for
1073 // addresses without at least 4-byte alignment.
1074 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1075 (LWAX xoaddr:$src)>;
1076 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1078 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1079 (STDX $rS, xoaddr:$dst)>;