1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
87 Requires<[In64BitMode]>;
88 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
91 Requires<[In64BitMode]>;
93 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
94 "bcctr 12, $bi, 0", IIC_BrB, []>,
95 Requires<[In64BitMode]>;
96 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 4, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
106 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
107 let Defs = [CTR8], Uses = [CTR8] in {
108 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
110 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
114 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
115 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
116 "bdzlr", IIC_BrB, []>;
117 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 "bdnzlr", IIC_BrB, []>;
124 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
125 // Convenient aliases for call instructions
127 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
128 "bl $func", IIC_BrB, []>; // See Pat patterns below.
130 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
131 "bl $func", IIC_BrB, []>;
133 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
134 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
136 let Uses = [RM], isCodeGenOnly = 1 in {
137 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
138 (outs), (ins calltarget:$func),
139 "bl $func\n\tnop", IIC_BrB, []>;
141 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
142 (outs), (ins tlscall:$func),
143 "bl $func\n\tnop", IIC_BrB, []>;
145 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
146 (outs), (ins abscalltarget:$func),
147 "bla $func\n\tnop", IIC_BrB,
148 [(PPCcall_nop (i64 imm:$func))]>;
150 let Uses = [CTR8, RM] in {
151 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
152 "bctrl", IIC_BrB, [(PPCbctrl)]>,
153 Requires<[In64BitMode]>;
155 let isCodeGenOnly = 1 in {
156 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
157 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
159 Requires<[In64BitMode]>;
161 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
162 "bcctrl 12, $bi, 0", IIC_BrB, []>,
163 Requires<[In64BitMode]>;
164 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 4, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
170 } // Interpretation64Bit
172 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
173 // previous definition must be marked as CodeGen only to prevent decoding
175 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
176 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
177 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
178 "bl $func", IIC_BrB, []>;
181 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
182 (BL8 tglobaladdr:$dst)>;
183 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
184 (BL8_NOP tglobaladdr:$dst)>;
186 def : Pat<(PPCcall (i64 texternalsym:$dst)),
187 (BL8 texternalsym:$dst)>;
188 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
189 (BL8_NOP texternalsym:$dst)>;
192 let usesCustomInserter = 1 in {
193 let Defs = [CR0] in {
194 def ATOMIC_LOAD_ADD_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
196 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
197 def ATOMIC_LOAD_SUB_I64 : Pseudo<
198 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
199 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
200 def ATOMIC_LOAD_OR_I64 : Pseudo<
201 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
202 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
203 def ATOMIC_LOAD_XOR_I64 : Pseudo<
204 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
205 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
206 def ATOMIC_LOAD_AND_I64 : Pseudo<
207 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
208 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
209 def ATOMIC_LOAD_NAND_I64 : Pseudo<
210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
211 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
213 def ATOMIC_CMP_SWAP_I64 : Pseudo<
214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
215 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
217 def ATOMIC_SWAP_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
219 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
223 // Instructions to support atomic operations
224 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
225 "ldarx $rD, $ptr", IIC_LdStLDARX,
226 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
229 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
230 "stdcx. $rS, $dst", IIC_LdStSTDCX,
231 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
234 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
235 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
236 def TCRETURNdi8 :Pseudo< (outs),
237 (ins calltarget:$dst, i32imm:$offset),
238 "#TC_RETURNd8 $dst $offset",
241 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
242 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
243 "#TC_RETURNa8 $func $offset",
244 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
246 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
247 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
248 "#TC_RETURNr8 $dst $offset",
251 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
252 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
253 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
255 Requires<[In64BitMode]>;
257 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
258 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
259 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
263 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
264 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
265 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
268 } // Interpretation64Bit
270 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
271 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
273 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
274 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
276 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
277 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
280 // 64-bit CR instructions
281 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
282 let neverHasSideEffects = 1 in {
283 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
284 "mtocrf $FXM, $ST", IIC_BrMCRX>,
285 PPC970_DGroup_First, PPC970_Unit_CRU;
287 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
288 "mtcrf $FXM, $rS", IIC_BrMCRX>,
289 PPC970_MicroCode, PPC970_Unit_CRU;
291 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
292 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
293 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
294 PPC970_DGroup_First, PPC970_Unit_CRU;
296 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
297 "mfcr $rT", IIC_SprMFCR>,
298 PPC970_MicroCode, PPC970_Unit_CRU;
299 } // neverHasSideEffects = 1
301 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
303 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
305 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
306 Requires<[In64BitMode]>;
307 let isTerminator = 1 in
308 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
309 "#EH_SJLJ_LONGJMP64",
310 [(PPCeh_sjlj_longjmp addr:$buf)]>,
311 Requires<[In64BitMode]>;
314 //===----------------------------------------------------------------------===//
315 // 64-bit SPR manipulation instrs.
317 let Uses = [CTR8] in {
318 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
319 "mfctr $rT", IIC_SprMFSPR>,
320 PPC970_DGroup_First, PPC970_Unit_FXU;
322 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
323 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
324 "mtctr $rS", IIC_SprMTSPR>,
325 PPC970_DGroup_First, PPC970_Unit_FXU;
327 let hasSideEffects = 1, Defs = [CTR8] in {
328 let Pattern = [(int_ppc_mtctr i64:$rS)] in
329 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
330 "mtctr $rS", IIC_SprMTSPR>,
331 PPC970_DGroup_First, PPC970_Unit_FXU;
334 let Pattern = [(set i64:$rT, readcyclecounter)] in
335 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
336 "mfspr $rT, 268", IIC_SprMFTB>,
337 PPC970_DGroup_First, PPC970_Unit_FXU;
338 // Note that encoding mftb using mfspr is now the preferred form,
339 // and has been since at least ISA v2.03. The mftb instruction has
340 // now been phased out. Using mfspr, however, is known not to work on
343 let Defs = [X1], Uses = [X1] in
344 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
346 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
348 let Defs = [LR8] in {
349 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
350 "mtlr $rS", IIC_SprMTSPR>,
351 PPC970_DGroup_First, PPC970_Unit_FXU;
353 let Uses = [LR8] in {
354 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
355 "mflr $rT", IIC_SprMFSPR>,
356 PPC970_DGroup_First, PPC970_Unit_FXU;
358 } // Interpretation64Bit
360 //===----------------------------------------------------------------------===//
361 // Fixed point instructions.
364 let PPC970_Unit = 1 in { // FXU Operations.
365 let Interpretation64Bit = 1 in {
366 let neverHasSideEffects = 1 in {
367 let isCodeGenOnly = 1 in {
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
370 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
371 "li $rD, $imm", IIC_IntSimple,
372 [(set i64:$rD, imm64SExt16:$imm)]>;
373 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
374 "lis $rD, $imm", IIC_IntSimple,
375 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
379 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
380 "nand", "$rA, $rS, $rB", IIC_IntSimple,
381 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
382 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
383 "and", "$rA, $rS, $rB", IIC_IntSimple,
384 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
385 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
386 "andc", "$rA, $rS, $rB", IIC_IntSimple,
387 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
388 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
389 "or", "$rA, $rS, $rB", IIC_IntSimple,
390 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
391 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
392 "nor", "$rA, $rS, $rB", IIC_IntSimple,
393 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
394 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
395 "orc", "$rA, $rS, $rB", IIC_IntSimple,
396 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
397 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
398 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
399 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
400 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
401 "xor", "$rA, $rS, $rB", IIC_IntSimple,
402 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
404 // Logical ops with immediate.
405 let Defs = [CR0] in {
406 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
407 "andi. $dst, $src1, $src2", IIC_IntGeneral,
408 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
410 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
411 "andis. $dst, $src1, $src2", IIC_IntGeneral,
412 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
415 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
416 "ori $dst, $src1, $src2", IIC_IntSimple,
417 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
418 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
419 "oris $dst, $src1, $src2", IIC_IntSimple,
420 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
421 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
422 "xori $dst, $src1, $src2", IIC_IntSimple,
423 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
424 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
425 "xoris $dst, $src1, $src2", IIC_IntSimple,
426 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
428 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
429 "add", "$rT, $rA, $rB", IIC_IntSimple,
430 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
431 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
432 // initial-exec thread-local storage model.
433 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
434 "add $rT, $rA, $rB", IIC_IntSimple,
435 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
437 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
438 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
439 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
440 PPC970_DGroup_Cracked;
441 let Defs = [CARRY] in
442 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
443 "addic $rD, $rA, $imm", IIC_IntGeneral,
444 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
445 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
446 "addi $rD, $rA, $imm", IIC_IntSimple,
447 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
448 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
449 "addis $rD, $rA, $imm", IIC_IntSimple,
450 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
452 let Defs = [CARRY] in {
453 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
454 "subfic $rD, $rA, $imm", IIC_IntGeneral,
455 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
456 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
457 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
458 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
459 PPC970_DGroup_Cracked;
461 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
462 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
463 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
464 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
465 "neg", "$rT, $rA", IIC_IntSimple,
466 [(set i64:$rT, (ineg i64:$rA))]>;
467 let Uses = [CARRY] in {
468 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
469 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
470 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
471 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
472 "addme", "$rT, $rA", IIC_IntGeneral,
473 [(set i64:$rT, (adde i64:$rA, -1))]>;
474 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
475 "addze", "$rT, $rA", IIC_IntGeneral,
476 [(set i64:$rT, (adde i64:$rA, 0))]>;
477 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
478 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
479 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
480 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
481 "subfme", "$rT, $rA", IIC_IntGeneral,
482 [(set i64:$rT, (sube -1, i64:$rA))]>;
483 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
484 "subfze", "$rT, $rA", IIC_IntGeneral,
485 [(set i64:$rT, (sube 0, i64:$rA))]>;
489 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
490 // previous definition must be marked as CodeGen only to prevent decoding
492 let isAsmParserOnly = 1 in
493 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
494 "add $rT, $rA, $rB", IIC_IntSimple, []>;
496 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
497 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
498 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
499 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
500 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
501 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
503 } // Interpretation64Bit
505 let isCompare = 1, neverHasSideEffects = 1 in {
506 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
507 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
508 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
509 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
510 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
511 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
512 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
513 "cmpldi $dst, $src1, $src2",
514 IIC_IntCompare>, isPPC64;
517 let neverHasSideEffects = 1 in {
518 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
519 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
520 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
521 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
522 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
523 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
524 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
525 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
526 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
528 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
529 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
530 "extsb", "$rA, $rS", IIC_IntSimple,
531 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
532 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
533 "extsh", "$rA, $rS", IIC_IntSimple,
534 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
535 } // Interpretation64Bit
538 let isCodeGenOnly = 1 in {
539 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
540 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
541 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
542 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
543 } // isCodeGenOnly for fast-isel
545 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
546 "extsw", "$rA, $rS", IIC_IntSimple,
547 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
548 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
549 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
550 "extsw", "$rA, $rS", IIC_IntSimple,
551 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
553 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
554 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
555 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
556 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
557 "cntlzd", "$rA, $rS", IIC_IntGeneral,
558 [(set i64:$rA, (ctlz i64:$rS))]>;
559 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
560 "popcntd $rA, $rS", IIC_IntGeneral,
561 [(set i64:$rA, (ctpop i64:$rS))]>;
563 // popcntw also does a population count on the high 32 bits (storing the
564 // results in the high 32-bits of the output). We'll ignore that here (which is
565 // safe because we never separately use the high part of the 64-bit registers).
566 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
567 "popcntw $rA, $rS", IIC_IntGeneral,
568 [(set i32:$rA, (ctpop i32:$rS))]>;
570 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
571 "divd", "$rT, $rA, $rB", IIC_IntDivD,
572 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
573 PPC970_DGroup_First, PPC970_DGroup_Cracked;
574 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
575 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
576 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
577 PPC970_DGroup_First, PPC970_DGroup_Cracked;
578 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
579 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
580 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
581 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
582 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
583 "mulli $rD, $rA, $imm", IIC_IntMulLI,
584 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
587 let neverHasSideEffects = 1 in {
588 let isCommutable = 1 in {
589 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
590 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
591 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
592 []>, isPPC64, RegConstraint<"$rSi = $rA">,
596 // Rotate instructions.
597 defm RLDCL : MDSForm_1r<30, 8,
598 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
599 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
601 defm RLDCR : MDSForm_1r<30, 9,
602 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
603 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
605 defm RLDICL : MDForm_1r<30, 0,
606 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
607 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
610 let isCodeGenOnly = 1 in
611 def RLDICL_32_64 : MDForm_1<30, 0,
613 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
614 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
617 defm RLDICR : MDForm_1r<30, 1,
618 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
619 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
621 defm RLDIC : MDForm_1r<30, 2,
622 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
623 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
626 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
627 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
628 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
629 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
632 let isCommutable = 1 in {
633 // RLWIMI can be commuted if the rotate amount is zero.
634 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
635 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
636 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
637 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
638 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
639 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
643 def ISEL8 : AForm_4<31, 15,
644 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
645 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
647 } // Interpretation64Bit
648 } // neverHasSideEffects = 1
649 } // End FXU Operations.
652 //===----------------------------------------------------------------------===//
653 // Load/Store instructions.
657 // Sign extending loads.
658 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
659 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
660 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
661 "lha $rD, $src", IIC_LdStLHA,
662 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
663 PPC970_DGroup_Cracked;
664 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
665 "lwa $rD, $src", IIC_LdStLWA,
667 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
668 PPC970_DGroup_Cracked;
669 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
670 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
671 "lhax $rD, $src", IIC_LdStLHA,
672 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
673 PPC970_DGroup_Cracked;
674 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
675 "lwax $rD, $src", IIC_LdStLHA,
676 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
677 PPC970_DGroup_Cracked;
679 let isCodeGenOnly = 1, mayLoad = 1 in {
680 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
681 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
682 PPC970_DGroup_Cracked;
683 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
684 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
685 PPC970_DGroup_Cracked;
686 } // end fast-isel isCodeGenOnly
689 let mayLoad = 1, neverHasSideEffects = 1 in {
690 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
691 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
693 "lhau $rD, $addr", IIC_LdStLHAU,
694 []>, RegConstraint<"$addr.reg = $ea_result">,
695 NoEncode<"$ea_result">;
698 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
699 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
701 "lhaux $rD, $addr", IIC_LdStLHAUX,
702 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
703 NoEncode<"$ea_result">;
704 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
706 "lwaux $rD, $addr", IIC_LdStLHAUX,
707 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
708 NoEncode<"$ea_result">, isPPC64;
712 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
713 // Zero extending loads.
714 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
715 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
716 "lbz $rD, $src", IIC_LdStLoad,
717 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
718 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
719 "lhz $rD, $src", IIC_LdStLoad,
720 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
721 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
722 "lwz $rD, $src", IIC_LdStLoad,
723 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
725 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
726 "lbzx $rD, $src", IIC_LdStLoad,
727 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
728 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
729 "lhzx $rD, $src", IIC_LdStLoad,
730 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
731 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
732 "lwzx $rD, $src", IIC_LdStLoad,
733 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
737 let mayLoad = 1, neverHasSideEffects = 1 in {
738 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
739 "lbzu $rD, $addr", IIC_LdStLoadUpd,
740 []>, RegConstraint<"$addr.reg = $ea_result">,
741 NoEncode<"$ea_result">;
742 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
743 "lhzu $rD, $addr", IIC_LdStLoadUpd,
744 []>, RegConstraint<"$addr.reg = $ea_result">,
745 NoEncode<"$ea_result">;
746 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
747 "lwzu $rD, $addr", IIC_LdStLoadUpd,
748 []>, RegConstraint<"$addr.reg = $ea_result">,
749 NoEncode<"$ea_result">;
751 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
753 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
754 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
755 NoEncode<"$ea_result">;
756 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
758 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
759 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
760 NoEncode<"$ea_result">;
761 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
763 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
764 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
765 NoEncode<"$ea_result">;
768 } // Interpretation64Bit
771 // Full 8-byte loads.
772 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
773 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
774 "ld $rD, $src", IIC_LdStLD,
775 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
776 // The following three definitions are selected for small code model only.
777 // Otherwise, we need to create two instructions to form a 32-bit offset,
778 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
779 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
782 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
783 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
786 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
787 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
790 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
792 let hasSideEffects = 1, isCodeGenOnly = 1 in {
793 let RST = 2, DS = 2 in
794 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
795 "ld 2, 8($reg)", IIC_LdStLD,
796 [(PPCload_toc i64:$reg)]>, isPPC64;
798 let RST = 2, DS = 10, RA = 1 in
799 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
800 "ld 2, 40(1)", IIC_LdStLD,
801 [(PPCtoc_restore)]>, isPPC64;
803 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
804 "ldx $rD, $src", IIC_LdStLD,
805 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
806 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
807 "ldbrx $rD, $src", IIC_LdStLoad,
808 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
810 let mayLoad = 1, neverHasSideEffects = 1 in {
811 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
812 "ldu $rD, $addr", IIC_LdStLDU,
813 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
814 NoEncode<"$ea_result">;
816 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
818 "ldux $rD, $addr", IIC_LdStLDUX,
819 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
820 NoEncode<"$ea_result">, isPPC64;
824 def : Pat<(PPCload ixaddr:$src),
826 def : Pat<(PPCload xaddr:$src),
829 // Support for medium and large code model.
830 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
833 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
835 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
838 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
839 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
842 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
844 // Support for thread-local storage.
845 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
848 (PPCaddisGotTprelHA i64:$reg,
849 tglobaltlsaddr:$disp))]>,
851 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
854 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
856 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
857 (ADD8TLS $in, tglobaltlsaddr:$g)>;
858 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
861 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
863 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
866 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
868 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
871 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
873 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
876 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
878 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
881 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
883 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
886 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
888 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
891 (PPCaddisDtprelHA i64:$reg,
892 tglobaltlsaddr:$disp))]>,
894 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
897 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
900 let PPC970_Unit = 2 in {
901 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
902 // Truncating stores.
903 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
904 "stb $rS, $src", IIC_LdStStore,
905 [(truncstorei8 i64:$rS, iaddr:$src)]>;
906 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
907 "sth $rS, $src", IIC_LdStStore,
908 [(truncstorei16 i64:$rS, iaddr:$src)]>;
909 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
910 "stw $rS, $src", IIC_LdStStore,
911 [(truncstorei32 i64:$rS, iaddr:$src)]>;
912 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
913 "stbx $rS, $dst", IIC_LdStStore,
914 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
915 PPC970_DGroup_Cracked;
916 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
917 "sthx $rS, $dst", IIC_LdStStore,
918 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
919 PPC970_DGroup_Cracked;
920 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
921 "stwx $rS, $dst", IIC_LdStStore,
922 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
923 PPC970_DGroup_Cracked;
924 } // Interpretation64Bit
926 // Normal 8-byte stores.
927 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
928 "std $rS, $dst", IIC_LdStSTD,
929 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
930 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
931 "stdx $rS, $dst", IIC_LdStSTD,
932 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
933 PPC970_DGroup_Cracked;
934 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
935 "stdbrx $rS, $dst", IIC_LdStStore,
936 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
937 PPC970_DGroup_Cracked;
940 // Stores with Update (pre-inc).
941 let PPC970_Unit = 2, mayStore = 1 in {
942 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
943 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
944 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
945 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
946 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
947 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
948 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
949 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
950 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
951 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
953 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
954 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
955 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
956 PPC970_DGroup_Cracked;
957 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
958 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
959 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
960 PPC970_DGroup_Cracked;
961 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
962 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
963 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
964 PPC970_DGroup_Cracked;
965 } // Interpretation64Bit
967 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
968 "stdu $rS, $dst", IIC_LdStSTDU, []>,
969 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
972 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
973 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
974 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
975 PPC970_DGroup_Cracked, isPPC64;
978 // Patterns to match the pre-inc stores. We can't put the patterns on
979 // the instruction definitions directly as ISel wants the address base
980 // and offset to be separate operands, not a single complex operand.
981 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
982 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
983 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
984 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
985 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
986 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
987 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
988 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
990 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
991 (STBUX8 $rS, $ptrreg, $ptroff)>;
992 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
993 (STHUX8 $rS, $ptrreg, $ptroff)>;
994 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
995 (STWUX8 $rS, $ptrreg, $ptroff)>;
996 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
997 (STDUX $rS, $ptrreg, $ptroff)>;
1000 //===----------------------------------------------------------------------===//
1001 // Floating point instructions.
1005 let PPC970_Unit = 3, neverHasSideEffects = 1,
1006 Uses = [RM] in { // FPU Operations.
1007 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1008 "fcfid", "$frD, $frB", IIC_FPGeneral,
1009 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1010 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1011 "fctid", "$frD, $frB", IIC_FPGeneral,
1013 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1014 "fctidz", "$frD, $frB", IIC_FPGeneral,
1015 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1017 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1018 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1019 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1020 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1021 "fcfids", "$frD, $frB", IIC_FPGeneral,
1022 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1023 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1024 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1025 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1026 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1027 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1028 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1029 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1030 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1031 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1035 //===----------------------------------------------------------------------===//
1036 // Instruction Patterns
1039 // Extensions and truncates to/from 32-bit regs.
1040 def : Pat<(i64 (zext i32:$in)),
1041 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1043 def : Pat<(i64 (anyext i32:$in)),
1044 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1045 def : Pat<(i32 (trunc i64:$in)),
1046 (EXTRACT_SUBREG $in, sub_32)>;
1048 // Implement the 'not' operation with the NOR instruction.
1049 // (we could use the default xori pattern, but nor has lower latency on some
1050 // cores (such as the A2)).
1051 def i64not : OutPatFrag<(ops node:$in),
1053 def : Pat<(not i64:$in),
1056 // Extending loads with i64 targets.
1057 def : Pat<(zextloadi1 iaddr:$src),
1059 def : Pat<(zextloadi1 xaddr:$src),
1060 (LBZX8 xaddr:$src)>;
1061 def : Pat<(extloadi1 iaddr:$src),
1063 def : Pat<(extloadi1 xaddr:$src),
1064 (LBZX8 xaddr:$src)>;
1065 def : Pat<(extloadi8 iaddr:$src),
1067 def : Pat<(extloadi8 xaddr:$src),
1068 (LBZX8 xaddr:$src)>;
1069 def : Pat<(extloadi16 iaddr:$src),
1071 def : Pat<(extloadi16 xaddr:$src),
1072 (LHZX8 xaddr:$src)>;
1073 def : Pat<(extloadi32 iaddr:$src),
1075 def : Pat<(extloadi32 xaddr:$src),
1076 (LWZX8 xaddr:$src)>;
1078 // Standard shifts. These are represented separately from the real shifts above
1079 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1081 def : Pat<(sra i64:$rS, i32:$rB),
1083 def : Pat<(srl i64:$rS, i32:$rB),
1085 def : Pat<(shl i64:$rS, i32:$rB),
1089 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1090 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1091 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1092 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1095 def : Pat<(rotl i64:$in, i32:$sh),
1096 (RLDCL $in, $sh, 0)>;
1097 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1098 (RLDICL $in, imm:$imm, 0)>;
1100 // Hi and Lo for Darwin Global Addresses.
1101 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1102 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1103 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1104 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1105 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1106 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1107 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1108 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1109 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1110 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1111 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1112 (ADDI8 $in, tglobaltlsaddr:$g)>;
1113 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1114 (ADDIS8 $in, tglobaladdr:$g)>;
1115 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1116 (ADDIS8 $in, tconstpool:$g)>;
1117 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1118 (ADDIS8 $in, tjumptable:$g)>;
1119 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1120 (ADDIS8 $in, tblockaddress:$g)>;
1122 // Patterns to match r+r indexed loads and stores for
1123 // addresses without at least 4-byte alignment.
1124 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1125 (LWAX xoaddr:$src)>;
1126 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1128 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1129 (STDX $rS, xoaddr:$dst)>;