1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
12 //===----------------------------------------------------------------------===//
15 #include "PowerPCInstrBuilder.h"
16 #include "PowerPCInstrInfo.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/Statistic.h"
35 //===----------------------------------------------------------------------===//
36 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
38 class PPC32TargetLowering : public TargetLowering {
39 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
40 int ReturnAddrIndex; // FrameIndex for return slot.
42 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
43 // Set up the TargetLowering object.
45 // Set up the register classes.
46 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
47 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
48 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
50 computeRegisterProperties();
53 /// LowerArguments - This hook must be implemented to indicate how we should
54 /// lower the arguments for the specified function, into the specified DAG.
55 virtual std::vector<SDOperand>
56 LowerArguments(Function &F, SelectionDAG &DAG);
58 /// LowerCallTo - This hook lowers an abstract call to a function into an
60 virtual std::pair<SDOperand, SDOperand>
61 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
62 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
64 virtual std::pair<SDOperand, SDOperand>
65 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
67 virtual std::pair<SDOperand,SDOperand>
68 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
69 const Type *ArgTy, SelectionDAG &DAG);
71 virtual std::pair<SDOperand, SDOperand>
72 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
78 std::vector<SDOperand>
79 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
81 // add beautiful description of PPC stack frame format, or at least some docs
83 MachineFunction &MF = DAG.getMachineFunction();
84 MachineFrameInfo *MFI = MF.getFrameInfo();
85 MachineBasicBlock& BB = MF.front();
86 std::vector<SDOperand> ArgValues;
88 // Due to the rather complicated nature of the PowerPC ABI, rather than a
89 // fixed size array of physical args, for the sake of simplicity let the STL
90 // handle tracking them for us.
91 std::vector<unsigned> argVR, argPR, argOp;
92 unsigned ArgOffset = 24;
93 unsigned GPR_remaining = 8;
94 unsigned FPR_remaining = 13;
95 unsigned GPR_idx = 0, FPR_idx = 0;
96 static const unsigned GPR[] = {
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
100 static const unsigned FPR[] = {
101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
102 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
105 // Add DAG nodes to load the arguments... On entry to a function on PPC,
106 // the arguments start at offset 24, although they are likely to be passed
108 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
109 SDOperand newroot, argt;
111 bool needsLoad = false;
112 MVT::ValueType ObjectVT = getValueType(I->getType());
115 default: assert(0 && "Unhandled argument type!");
121 if (GPR_remaining > 0) {
122 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
124 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
125 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
126 if (ObjectVT != MVT::i32)
127 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
128 argVR.push_back(virtReg);
129 argPR.push_back(GPR[GPR_idx]);
130 argOp.push_back(PPC::OR);
135 case MVT::i64: ObjSize = 8;
136 // FIXME: can split 64b load between reg/mem if it is last arg in regs
137 if (GPR_remaining > 1) {
138 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
139 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
140 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
142 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
143 // FIXME: is this correct?
144 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
145 argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
146 // Push the arguments for emitting into BB later
147 argVR.push_back(virtReg); argVR.push_back(virtReg+1);
148 argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
149 argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
154 case MVT::f32: ObjSize = 4;
155 case MVT::f64: ObjSize = 8;
156 if (FPR_remaining > 0) {
157 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
159 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
160 argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
161 argVR.push_back(virtReg);
162 argPR.push_back(FPR[FPR_idx]);
163 argOp.push_back(PPC::FMR);
172 // We need to load the argument to a virtual register if we determined above
173 // that we ran out of physical registers of the appropriate type
175 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
176 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
177 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
180 // Every 4 bytes of argument space consumes one of the GPRs available for
182 if (GPR_remaining > 0) {
183 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
184 GPR_remaining -= delta;
187 ArgOffset += ObjSize;
189 DAG.setRoot(newroot.getValue(1));
190 ArgValues.push_back(argt);
193 for (int i = 0, count = argVR.size(); i < count; ++i) {
194 if (argOp[i] == PPC::FMR)
195 BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
197 BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
200 // If the function takes variable number of arguments, make a frame index for
201 // the start of the first vararg value... for expansion of llvm.va_start.
203 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
208 std::pair<SDOperand, SDOperand>
209 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
210 const Type *RetTy, bool isVarArg,
211 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
212 // args_to_use will accumulate outgoing args for the ISD::CALL case in
213 // SelectExpr to use to put the arguments in the appropriate registers.
214 std::vector<SDOperand> args_to_use;
216 // Count how many bytes are to be pushed on the stack, including the linkage
217 // area, and parameter passing area.
218 unsigned NumBytes = 24;
221 NumBytes = 0; // Save zero bytes.
223 for (unsigned i = 0, e = Args.size(); i != e; ++i)
224 switch (getValueType(Args[i].second)) {
225 default: assert(0 && "Unknown value type!");
239 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
240 // plus 32 bytes of argument space in case any called code gets funky on us.
241 if (NumBytes < 56) NumBytes = 56;
243 // Adjust the stack pointer for the new arguments...
244 // These operations are automatically eliminated by the prolog/epilog pass
245 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
246 DAG.getConstant(NumBytes, getPointerTy()));
248 // Set up a copy of the stack pointer for use loading and storing any
249 // arguments that may not fit in the registers available for argument
251 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
254 // Figure out which arguments are going to go in registers, and which in
255 // memory. Also, if this is a vararg function, floating point operations
256 // must be stored to our stack, and loaded into integer regs as well, if
257 // any integer regs are available for argument passing.
258 unsigned ArgOffset = 24;
259 unsigned GPR_remaining = 8;
260 unsigned FPR_remaining = 13;
261 std::vector<SDOperand> Stores;
262 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
263 // PtrOff will be used to store the current argument to the stack if a
264 // register cannot be found for it.
265 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
266 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
267 MVT::ValueType ArgVT = getValueType(Args[i].second);
270 default: assert(0 && "Unexpected ValueType for argument!");
274 // Promote the integer to 32 bits. If the input type is signed use a
275 // sign extend, otherwise use a zero extend.
276 if (Args[i].second->isSigned())
277 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
279 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
282 if (GPR_remaining > 0) {
283 args_to_use.push_back(Args[i].first);
286 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
287 Args[i].first, PtrOff));
292 // If we have one free GPR left, we can place the upper half of the i64
293 // in it, and store the other half to the stack. If we have two or more
294 // free GPRs, then we can pass both halves of the i64 in registers.
295 if (GPR_remaining > 0) {
296 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
297 Args[i].first, DAG.getConstant(1, MVT::i32));
298 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
299 Args[i].first, DAG.getConstant(0, MVT::i32));
300 args_to_use.push_back(Hi);
301 if (GPR_remaining > 1) {
302 args_to_use.push_back(Lo);
305 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
306 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
307 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
312 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
313 Args[i].first, PtrOff));
319 if (FPR_remaining > 0) {
321 // FIXME: Need FunctionType information so we can conditionally
322 // store only the non-fixed arguments in a vararg function.
323 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
324 Args[i].first, PtrOff));
325 // FIXME: Need a way to communicate to the ISD::CALL select code
326 // that a particular argument is non-fixed so that we can load them
327 // into the correct GPR to shadow the FPR
329 args_to_use.push_back(Args[i].first);
331 // If we have any FPRs remaining, we may also have GPRs remaining.
332 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
334 if (GPR_remaining > 0) --GPR_remaining;
335 if (GPR_remaining > 0 && MVT::f64 == ArgVT) --GPR_remaining;
337 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
338 Args[i].first, PtrOff));
340 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
344 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
347 std::vector<MVT::ValueType> RetVals;
348 MVT::ValueType RetTyVT = getValueType(RetTy);
349 if (RetTyVT != MVT::isVoid)
350 RetVals.push_back(RetTyVT);
351 RetVals.push_back(MVT::Other);
353 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
354 Chain, Callee, args_to_use), 0);
355 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
356 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
357 DAG.getConstant(NumBytes, getPointerTy()));
358 return std::make_pair(TheCall, Chain);
361 std::pair<SDOperand, SDOperand>
362 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
363 //vastart just returns the address of the VarArgsFrameIndex slot.
364 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
367 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
368 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
369 const Type *ArgTy, SelectionDAG &DAG) {
370 MVT::ValueType ArgVT = getValueType(ArgTy);
373 Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
376 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
379 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
380 "Other types should have been promoted for varargs!");
383 Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
384 DAG.getConstant(Amt, VAList.getValueType()));
386 return std::make_pair(Result, Chain);
390 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
391 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
398 //===--------------------------------------------------------------------===//
399 /// ISel - PPC32 specific code to select PPC32 machine instructions for
400 /// SelectionDAG operations.
401 //===--------------------------------------------------------------------===//
402 class ISel : public SelectionDAGISel {
405 PPC32TargetLowering PPC32Lowering;
407 /// ExprMap - As shared expressions are codegen'd, we keep track of which
408 /// vreg the value is produced in, so we only emit one copy of each compiled
410 std::map<SDOperand, unsigned> ExprMap;
412 unsigned GlobalBaseReg;
413 bool GlobalBaseInitialized;
416 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM)
419 /// runOnFunction - Override this function in order to reset our per-function
421 virtual bool runOnFunction(Function &Fn) {
422 // Make sure we re-emit a set of the global base reg if necessary
423 GlobalBaseInitialized = false;
424 return SelectionDAGISel::runOnFunction(Fn);
427 /// InstructionSelectBasicBlock - This callback is invoked by
428 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
429 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
431 // Codegen the basic block.
432 Select(DAG.getRoot());
434 // Clear state used for selection.
438 unsigned ISel::getGlobalBaseReg();
439 unsigned SelectExpr(SDOperand N);
440 unsigned SelectExprFP(SDOperand N, unsigned Result);
441 void Select(SDOperand N);
443 void SelectAddr(SDOperand N, unsigned& Reg, int& offset);
444 void SelectBranchCC(SDOperand N);
447 /// canUseAsImmediateForOpcode - This method returns a value indicating whether
448 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
449 /// values are either 0, 1 or 2. 0 indicates that either N is not a
450 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
451 /// of 1 indicates that the constant may be used in normal immediate form. A
452 /// return value of 2 indicates that the constant may be used in shifted
453 /// immediate form. If the return value is nonzero, the constant value is
456 static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
458 if (N.getOpcode() != ISD::Constant) return 0;
460 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
465 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
466 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
471 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
472 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
475 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
482 /// getGlobalBaseReg - Output the instructions required to put the
483 /// base address to use for accessing globals into a register.
485 unsigned ISel::getGlobalBaseReg() {
486 if (!GlobalBaseInitialized) {
487 // Insert the set of GlobalBaseReg into the first MBB of the function
488 MachineBasicBlock &FirstMBB = BB->getParent()->front();
489 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
490 GlobalBaseReg = MakeReg(MVT::i32);
491 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
492 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
493 GlobalBaseInitialized = true;
495 return GlobalBaseReg;
498 //Check to see if the load is a constant offset from a base register
499 void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
506 void ISel::SelectBranchCC(SDOperand N)
508 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
509 MachineBasicBlock *Dest =
510 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
513 Select(N.getOperand(0)); //chain
514 SDOperand CC = N.getOperand(1);
516 //Giveup and do the stupid thing
517 unsigned Tmp1 = SelectExpr(CC);
518 BuildMI(BB, PPC::BNE, 2).addReg(Tmp1).addMBB(Dest);
522 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
524 unsigned Tmp1, Tmp2, Tmp3;
526 SDNode *Node = N.Val;
527 MVT::ValueType DestType = N.getValueType();
528 unsigned opcode = N.getOpcode();
533 assert(0 && "Node not handled!\n");
539 assert (DestType == MVT::f32 &&
540 N.getOperand(0).getValueType() == MVT::f64 &&
541 "only f64 to f32 conversion supported here");
542 Tmp1 = SelectExpr(N.getOperand(0));
543 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
547 assert (DestType == MVT::f64 &&
548 N.getOperand(0).getValueType() == MVT::f32 &&
549 "only f32 to f64 conversion supported here");
550 Tmp1 = SelectExpr(N.getOperand(0));
551 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
554 case ISD::CopyFromReg:
556 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
557 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
558 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
565 case ISD::ConstantFP:
573 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
574 case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
575 case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
576 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
579 Tmp1 = SelectExpr(N.getOperand(0));
580 Tmp2 = SelectExpr(N.getOperand(1));
581 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
584 case ISD::UINT_TO_FP:
585 case ISD::SINT_TO_FP:
588 assert(0 && "should not get here");
592 unsigned ISel::SelectExpr(SDOperand N) {
594 unsigned Tmp1, Tmp2, Tmp3;
596 unsigned opcode = N.getOpcode();
598 SDNode *Node = N.Val;
599 MVT::ValueType DestType = N.getValueType();
601 unsigned &Reg = ExprMap[N];
604 if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
605 N.getOpcode() != ISD::SUB_PARTS)
606 Reg = Result = (N.getValueType() != MVT::Other) ?
607 MakeReg(N.getValueType()) : 1;
609 // If this is a call instruction, make sure to prepare ALL of the result
610 // values as well as the chain.
611 if (N.getOpcode() == ISD::CALL) {
612 if (Node->getNumValues() == 1)
613 Reg = Result = 1; // Void call, just a chain.
615 Result = MakeReg(Node->getValueType(0));
616 ExprMap[N.getValue(0)] = Result;
617 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
618 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
619 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
622 Result = MakeReg(Node->getValueType(0));
623 ExprMap[N.getValue(0)] = Result;
624 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
625 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
629 if (DestType == MVT::f64 || DestType == MVT::f32)
630 return SelectExprFP(N, Result);
635 assert(0 && "Node not handled!\n");
637 case ISD::DYNAMIC_STACKALLOC:
638 // Generate both result values. FIXME: Need a better commment here?
640 ExprMap[N.getValue(1)] = 1;
642 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
644 // FIXME: We are currently ignoring the requested alignment for handling
645 // greater than the stack alignment. This will need to be revisited at some
646 // point. Align = N.getOperand(2);
647 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
648 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
649 std::cerr << "Cannot allocate stack object with greater alignment than"
650 << " the stack alignment yet!";
653 Select(N.getOperand(0));
654 Tmp1 = SelectExpr(N.getOperand(1));
655 // Subtract size from stack pointer, thereby allocating some space.
656 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
657 // Put a pointer to the space into the result register by copying the SP
658 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
661 case ISD::ConstantPool:
664 case ISD::FrameIndex:
667 case ISD::GlobalAddress: {
668 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
669 unsigned Tmp1 = MakeReg(MVT::i32);
670 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
671 .addGlobalAddress(GV);
672 if (GV->hasWeakLinkage() || GV->isExternal()) {
673 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
675 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
683 case ISD::SEXTLOAD: {
684 // Make sure we generate both values.
686 ExprMap[N.getValue(1)] = 1; // Generate the token
688 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
690 SDOperand Chain = N.getOperand(0);
691 SDOperand Address = N.getOperand(1);
694 switch (Node->getValueType(0)) {
695 default: assert(0 && "Cannot load this type!");
696 case MVT::i1: Opc = PPC::LBZ; Tmp3 = 0; break;
697 case MVT::i8: Opc = PPC::LBZ; Tmp3 = 1; break;
698 case MVT::i16: Opc = PPC::LHZ; Tmp3 = 0; break;
699 case MVT::i32: Opc = PPC::LWZ; Tmp3 = 0; break;
702 if(Address.getOpcode() == ISD::FrameIndex) {
703 BuildMI(BB, Opc, 2, Result)
704 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
708 SelectAddr(Address, Tmp1, offset);
709 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
715 // Lower the chain for this call.
716 Select(N.getOperand(0));
717 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
719 // get the virtual reg for each argument
720 std::vector<unsigned> VRegs;
721 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
722 VRegs.push_back(SelectExpr(N.getOperand(i)));
724 // The ABI specifies that the first 32 bytes of args may be passed in GPRs,
725 // and that 13 FPRs may also be used for passing any floating point args.
726 int GPR_remaining = 8, FPR_remaining = 13;
727 unsigned GPR_idx = 0, FPR_idx = 0;
728 static const unsigned GPR[] = {
729 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
730 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
732 static const unsigned FPR[] = {
733 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
734 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
738 // move the vregs into the appropriate architected register or stack slot
739 for(int i = 0, e = VRegs.size(); i < e; ++i) {
740 unsigned OperandType = N.getOperand(i+2).getValueType();
741 switch(OperandType) {
744 N.getOperand(i).Val->dump();
745 std::cerr << "Type for " << i << " is: " <<
746 N.getOperand(i+2).getValueType() << "\n";
747 assert(0 && "Unknown value type for call");
752 if (GPR_remaining > 0)
753 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(VRegs[i])
758 if (FPR_remaining > 0) {
759 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(VRegs[i]);
765 // All arguments consume GPRs available for argument passing
766 if (GPR_remaining > 0) {
770 if (MVT::f64 == OperandType && GPR_remaining > 0) {
776 // Emit the correct call instruction based on the type of symbol called.
777 if (GlobalAddressSDNode *GASD =
778 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
779 BuildMI(BB, PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), true);
780 } else if (ExternalSymbolSDNode *ESSDN =
781 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
782 BuildMI(BB, PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), true);
784 Tmp1 = SelectExpr(N.getOperand(1));
785 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
786 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
787 BuildMI(BB, PPC::CALLindirect, 3).addImm(20).addImm(0).addReg(PPC::R12);
790 switch (Node->getValueType(0)) {
791 default: assert(0 && "Unknown value type for call result!");
792 case MVT::Other: return 1;
797 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
798 if (Node->getValueType(1) == MVT::i32)
799 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4).addReg(PPC::R4);
803 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
806 return Result+N.ResNo;
809 case ISD::SIGN_EXTEND:
810 case ISD::SIGN_EXTEND_INREG:
811 Tmp1 = SelectExpr(N.getOperand(0));
812 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
815 case ISD::ZERO_EXTEND_INREG:
816 Tmp1 = SelectExpr(N.getOperand(0));
817 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
820 assert(0 && "Zero Extend InReg not there yet");
822 case MVT::i16: Tmp2 = 16; break;
823 case MVT::i8: Tmp2 = 24; break;
824 case MVT::i1: Tmp2 = 31; break;
826 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
827 .addImm(Tmp2).addImm(31);
830 case ISD::CopyFromReg:
832 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
833 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
834 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
838 Tmp1 = SelectExpr(N.getOperand(0));
839 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
840 Tmp2 = CN->getValue() & 0x1F;
841 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
844 Tmp2 = SelectExpr(N.getOperand(1));
845 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
850 Tmp1 = SelectExpr(N.getOperand(0));
851 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
852 Tmp2 = CN->getValue() & 0x1F;
853 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(32-Tmp2)
854 .addImm(Tmp2).addImm(31);
856 Tmp2 = SelectExpr(N.getOperand(1));
857 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
862 Tmp1 = SelectExpr(N.getOperand(0));
863 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
864 Tmp2 = CN->getValue() & 0x1F;
865 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
867 Tmp2 = SelectExpr(N.getOperand(1));
868 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
873 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
874 Tmp1 = SelectExpr(N.getOperand(0));
875 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
876 default: assert(0 && "unhandled result code");
877 case 0: // No immediate
878 Tmp2 = SelectExpr(N.getOperand(1));
879 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
881 case 1: // Low immediate
882 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
884 case 2: // Shifted immediate
885 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
893 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
894 Tmp1 = SelectExpr(N.getOperand(0));
895 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
896 default: assert(0 && "unhandled result code");
897 case 0: // No immediate
898 Tmp2 = SelectExpr(N.getOperand(1));
900 case ISD::AND: Opc = PPC::AND; break;
901 case ISD::OR: Opc = PPC::OR; break;
902 case ISD::XOR: Opc = PPC::XOR; break;
904 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
906 case 1: // Low immediate
908 case ISD::AND: Opc = PPC::ANDIo; break;
909 case ISD::OR: Opc = PPC::ORI; break;
910 case ISD::XOR: Opc = PPC::XORI; break;
912 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
914 case 2: // Shifted immediate
916 case ISD::AND: Opc = PPC::ANDISo; break;
917 case ISD::OR: Opc = PPC::ORIS; break;
918 case ISD::XOR: Opc = PPC::XORIS; break;
920 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
926 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
927 Tmp1 = SelectExpr(N.getOperand(0));
928 Tmp2 = SelectExpr(N.getOperand(1));
929 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
933 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
934 Tmp1 = SelectExpr(N.getOperand(0));
935 if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
936 BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
938 Tmp2 = SelectExpr(N.getOperand(1));
939 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
951 case ISD::FP_TO_UINT:
952 case ISD::FP_TO_SINT:
962 switch (N.getValueType()) {
963 default: assert(0 && "Cannot use constants of this type!");
965 BuildMI(BB, PPC::LI, 1, Result)
966 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
970 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
971 if (v < 32768 && v >= -32768) {
972 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
974 Tmp1 = MakeReg(MVT::i32);
975 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
976 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
986 void ISel::Select(SDOperand N) {
987 unsigned Tmp1, Tmp2, Opc;
988 unsigned opcode = N.getOpcode();
990 if (!ExprMap.insert(std::make_pair(N, 1)).second)
991 return; // Already selected.
993 SDNode *Node = N.Val;
995 switch (Node->getOpcode()) {
997 Node->dump(); std::cerr << "\n";
998 assert(0 && "Node not handled yet!");
999 case ISD::EntryToken: return; // Noop
1000 case ISD::TokenFactor:
1001 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1002 Select(Node->getOperand(i));
1004 case ISD::ADJCALLSTACKDOWN:
1005 case ISD::ADJCALLSTACKUP:
1006 Select(N.getOperand(0));
1007 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1008 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
1009 PPC::ADJCALLSTACKUP;
1010 BuildMI(BB, Opc, 1).addImm(Tmp1);
1013 MachineBasicBlock *Dest =
1014 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
1015 Select(N.getOperand(0));
1016 BuildMI(BB, PPC::B, 1).addMBB(Dest);
1022 case ISD::CopyToReg:
1023 Select(N.getOperand(0));
1024 Tmp1 = SelectExpr(N.getOperand(1));
1025 Tmp2 = cast<RegSDNode>(N)->getReg();
1028 if (N.getOperand(1).getValueType() == MVT::f64 ||
1029 N.getOperand(1).getValueType() == MVT::f32)
1030 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
1032 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1035 case ISD::ImplicitDef:
1036 Select(N.getOperand(0));
1037 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
1040 switch (N.getNumOperands()) {
1042 assert(0 && "Unknown return instruction!");
1044 assert(N.getOperand(1).getValueType() == MVT::i32 &&
1045 N.getOperand(2).getValueType() == MVT::i32 &&
1046 "Unknown two-register value!");
1047 Select(N.getOperand(0));
1048 Tmp1 = SelectExpr(N.getOperand(1));
1049 Tmp2 = SelectExpr(N.getOperand(2));
1050 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
1051 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
1054 Select(N.getOperand(0));
1055 Tmp1 = SelectExpr(N.getOperand(1));
1056 switch (N.getOperand(1).getValueType()) {
1058 assert(0 && "Unknown return type!");
1061 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
1064 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
1068 Select(N.getOperand(0));
1071 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
1073 case ISD::TRUNCSTORE:
1076 SDOperand Chain = N.getOperand(0);
1077 SDOperand Value = N.getOperand(1);
1078 SDOperand Address = N.getOperand(2);
1081 Tmp1 = SelectExpr(Value); //value
1083 if (opcode == ISD::STORE) {
1084 switch(Value.getValueType()) {
1085 default: assert(0 && "unknown Type in store");
1086 case MVT::i32: Opc = PPC::STW; break;
1087 case MVT::f64: Opc = PPC::STFD; break;
1088 case MVT::f32: Opc = PPC::STFS; break;
1090 } else { //ISD::TRUNCSTORE
1091 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1092 default: assert(0 && "unknown Type in store");
1093 case MVT::i1: //FIXME: DAG does not promote this load
1094 case MVT::i8: Opc = PPC::STB; break;
1095 case MVT::i16: Opc = PPC::STH; break;
1099 if (Address.getOpcode() == ISD::GlobalAddress)
1101 BuildMI(BB, Opc, 2).addReg(Tmp1)
1102 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
1104 else if(Address.getOpcode() == ISD::FrameIndex)
1106 BuildMI(BB, Opc, 2).addReg(Tmp1)
1107 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
1112 SelectAddr(Address, Tmp2, offset);
1113 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
1121 case ISD::CopyFromReg:
1123 case ISD::DYNAMIC_STACKALLOC:
1128 assert(0 && "Should not be reached!");
1132 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
1133 /// into a machine code representation using pattern matching and a machine
1134 /// description file.
1136 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
1137 return new ISel(TM);