1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
12 //===----------------------------------------------------------------------===//
15 #include "PowerPCInstrBuilder.h"
16 #include "PowerPCInstrInfo.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/Statistic.h"
35 //===----------------------------------------------------------------------===//
36 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
38 class PPC32TargetLowering : public TargetLowering {
39 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
40 int ReturnAddrIndex; // FrameIndex for return slot.
42 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
43 // Set up the TargetLowering object.
45 // Set up the register classes.
46 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
47 addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
50 computeRegisterProperties();
53 /// LowerArguments - This hook must be implemented to indicate how we should
54 /// lower the arguments for the specified function, into the specified DAG.
55 virtual std::vector<SDOperand>
56 LowerArguments(Function &F, SelectionDAG &DAG);
58 /// LowerCallTo - This hook lowers an abstract call to a function into an
60 virtual std::pair<SDOperand, SDOperand>
61 LowerCallTo(SDOperand Chain, const Type *RetTy, SDOperand Callee,
62 ArgListTy &Args, SelectionDAG &DAG);
64 virtual std::pair<SDOperand, SDOperand>
65 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
67 virtual std::pair<SDOperand,SDOperand>
68 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
69 const Type *ArgTy, SelectionDAG &DAG);
71 virtual std::pair<SDOperand, SDOperand>
72 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
78 std::vector<SDOperand>
79 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
81 // add beautiful description of PPC stack frame format, or at least some docs
83 MachineFunction &MF = DAG.getMachineFunction();
84 MachineFrameInfo *MFI = MF.getFrameInfo();
85 MachineBasicBlock& BB = MF.front();
86 std::vector<SDOperand> ArgValues;
88 // Due to the rather complicated nature of the PowerPC ABI, rather than a
89 // fixed size array of physical args, for the sake of simplicity let the STL
90 // handle tracking them for us.
91 std::vector<unsigned> argVR, argPR, argOp;
92 unsigned ArgOffset = 24;
93 unsigned GPR_remaining = 8;
94 unsigned FPR_remaining = 13;
95 unsigned GPR_idx = 0, FPR_idx = 0;
96 static const unsigned GPR[] = {
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
100 static const unsigned FPR[] = {
101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
102 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
105 // Add DAG nodes to load the arguments... On entry to a function on PPC,
106 // the arguments start at offset 24, although they are likely to be passed
108 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
109 SDOperand newroot, argt;
111 bool needsLoad = false;
112 MVT::ValueType ObjectVT = getValueType(I->getType());
115 default: assert(0 && "Unhandled argument type!");
121 if (GPR_remaining > 0) {
122 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
124 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
125 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
126 if (ObjectVT != MVT::i32)
127 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
128 argVR.push_back(virtReg);
129 argPR.push_back(GPR[GPR_idx]);
130 argOp.push_back(PPC::OR);
135 case MVT::i64: ObjSize = 8;
136 if (GPR_remaining > 1) {
137 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
138 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
139 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
141 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
142 // FIXME: is this correct?
143 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
144 argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
145 // Push the arguments for emitting into BB later
146 argVR.push_back(virtReg); argVR.push_back(virtReg+1);
147 argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
148 argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
153 case MVT::f32: ObjSize = 4;
154 case MVT::f64: ObjSize = 8;
155 if (FPR_remaining > 0) {
156 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
158 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
159 argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
160 argVR.push_back(virtReg);
161 argPR.push_back(FPR[FPR_idx]);
162 argOp.push_back(PPC::FMR);
171 // We need to load the argument to a virtual register if we determined above
172 // that we ran out of physical registers of the appropriate type
174 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
175 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
176 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
179 // Every 4 bytes of argument space consumes one of the GPRs available for
181 if (GPR_remaining > 0) {
182 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
183 GPR_remaining -= delta;
186 ArgOffset += ObjSize;
188 DAG.setRoot(newroot.getValue(1));
189 ArgValues.push_back(argt);
192 for (int i = 0, count = argVR.size(); i < count; ++i) {
193 if (argOp[i] == PPC::FMR)
194 BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
196 BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
199 // If the function takes variable number of arguments, make a frame index for
200 // the start of the first vararg value... for expansion of llvm.va_start.
202 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
207 std::pair<SDOperand, SDOperand>
208 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
209 const Type *RetTy, SDOperand Callee,
210 ArgListTy &Args, SelectionDAG &DAG) {
214 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
215 DAG.getConstant(NumBytes, getPointerTy()));
216 std::vector<SDOperand> args_to_use;
217 for (unsigned i = 0, e = Args.size(); i != e; ++i)
219 switch (getValueType(Args[i].second)) {
220 default: assert(0 && "Unexpected ValueType for argument!");
230 args_to_use.push_back(Args[i].first);
233 std::vector<MVT::ValueType> RetVals;
234 MVT::ValueType RetTyVT = getValueType(RetTy);
235 if (RetTyVT != MVT::isVoid)
236 RetVals.push_back(RetTyVT);
237 RetVals.push_back(MVT::Other);
239 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
240 Chain, Callee, args_to_use), 0);
241 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
242 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
243 DAG.getConstant(NumBytes, getPointerTy()));
244 return std::make_pair(TheCall, Chain);
247 std::pair<SDOperand, SDOperand>
248 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
249 //vastart just returns the address of the VarArgsFrameIndex slot.
250 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
253 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
254 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
255 const Type *ArgTy, SelectionDAG &DAG) {
260 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
261 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
268 //===--------------------------------------------------------------------===//
269 /// ISel - PPC32 specific code to select PPC32 machine instructions for
270 /// SelectionDAG operations.
271 //===--------------------------------------------------------------------===//
272 class ISel : public SelectionDAGISel {
275 PPC32TargetLowering PPC32Lowering;
277 /// ExprMap - As shared expressions are codegen'd, we keep track of which
278 /// vreg the value is produced in, so we only emit one copy of each compiled
280 std::map<SDOperand, unsigned> ExprMap;
283 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM)
286 /// InstructionSelectBasicBlock - This callback is invoked by
287 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
288 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
290 // Codegen the basic block.
291 Select(DAG.getRoot());
293 // Clear state used for selection.
297 unsigned SelectExpr(SDOperand N);
298 unsigned SelectExprFP(SDOperand N, unsigned Result);
299 void Select(SDOperand N);
301 void SelectAddr(SDOperand N, unsigned& Reg, int& offset);
302 void SelectBranchCC(SDOperand N);
305 /// canUseAsImmediateForOpcode - This method returns a value indicating whether
306 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
307 /// values are either 0, 1 or 2. 0 indicates that either N is not a
308 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
309 /// of 1 indicates that the constant may be used in normal immediate form. A
310 /// return value of 2 indicates that the constant may be used in shifted
311 /// immediate form. If the return value is nonzero, the constant value is
314 static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
316 if (N.getOpcode() != ISD::Constant) return 0;
318 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
323 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
324 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
329 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
330 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
337 //Check to see if the load is a constant offset from a base register
338 void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
345 void ISel::SelectBranchCC(SDOperand N)
347 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
348 MachineBasicBlock *Dest =
349 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
352 Select(N.getOperand(0)); //chain
353 SDOperand CC = N.getOperand(1);
355 //Giveup and do the stupid thing
356 unsigned Tmp1 = SelectExpr(CC);
357 BuildMI(BB, PPC::BNE, 2).addReg(Tmp1).addMBB(Dest);
361 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
363 unsigned Tmp1, Tmp2, Tmp3;
365 SDNode *Node = N.Val;
366 MVT::ValueType DestType = N.getValueType();
367 unsigned opcode = N.getOpcode();
372 assert(0 && "Node not handled!\n");
378 assert (DestType == MVT::f32 &&
379 N.getOperand(0).getValueType() == MVT::f64 &&
380 "only f64 to f32 conversion supported here");
381 Tmp1 = SelectExpr(N.getOperand(0));
382 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
386 assert (DestType == MVT::f64 &&
387 N.getOperand(0).getValueType() == MVT::f32 &&
388 "only f32 to f64 conversion supported here");
389 Tmp1 = SelectExpr(N.getOperand(0));
390 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
393 case ISD::CopyFromReg:
394 // FIXME: Handle copy from physregs!
395 // Just use the specified register as our input.
396 return dyn_cast<RegSDNode>(Node)->getReg();
402 case ISD::ConstantFP:
410 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
411 case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
412 case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
413 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
416 Tmp1 = SelectExpr(N.getOperand(0));
417 Tmp2 = SelectExpr(N.getOperand(1));
418 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
421 case ISD::UINT_TO_FP:
422 case ISD::SINT_TO_FP:
425 assert(0 && "should not get here");
429 unsigned ISel::SelectExpr(SDOperand N) {
431 unsigned Tmp1, Tmp2, Tmp3;
433 unsigned opcode = N.getOpcode();
435 SDNode *Node = N.Val;
436 MVT::ValueType DestType = N.getValueType();
438 unsigned &Reg = ExprMap[N];
441 if (DestType == MVT::f64 || DestType == MVT::f32)
442 return SelectExprFP(N, Result);
444 if (N.getOpcode() != ISD::CALL)
445 Reg = Result = (N.getValueType() != MVT::Other) ?
446 MakeReg(N.getValueType()) : 1;
448 abort(); // FIXME: Implement Call
453 assert(0 && "Node not handled!\n");
455 case ISD::DYNAMIC_STACKALLOC:
456 // Generate both result values. FIXME: Need a better commment here?
458 ExprMap[N.getValue(1)] = 1;
460 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
462 // FIXME: We are currently ignoring the requested alignment for handling
463 // greater than the stack alignment. This will need to be revisited at some
464 // point. Align = N.getOperand(2);
465 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
466 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
467 std::cerr << "Cannot allocate stack object with greater alignment than"
468 << " the stack alignment yet!";
471 Select(N.getOperand(0));
472 Tmp1 = SelectExpr(N.getOperand(1));
473 // Subtract size from stack pointer, thereby allocating some space.
474 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
475 // Put a pointer to the space into the result register by copying the SP
476 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
479 case ISD::ConstantPool:
482 case ISD::FrameIndex:
489 // Make sure we generate both values.
491 ExprMap[N.getValue(1)] = 1; // Generate the token
493 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
495 SDOperand Chain = N.getOperand(0);
496 SDOperand Address = N.getOperand(1);
499 switch (Node->getValueType(0)) {
500 default: assert(0 && "Cannot load this type!");
502 case MVT::i8: Opc = PPC::LBZ; break;
503 case MVT::i16: Opc = PPC::LHZ; break;
504 case MVT::i32: Opc = PPC::LWZ; break;
507 if (Address.getOpcode() == ISD::GlobalAddress) { // FIXME
508 BuildMI(BB, Opc, 2, Result)
509 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal())
512 else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
513 BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
516 else if(Address.getOpcode() == ISD::FrameIndex) {
517 BuildMI(BB, Opc, 2, Result)
518 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
522 SelectAddr(Address, Tmp1, offset);
523 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
529 case ISD::GlobalAddress:
533 case ISD::SIGN_EXTEND:
534 case ISD::SIGN_EXTEND_INREG:
535 Tmp1 = SelectExpr(N.getOperand(0));
536 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
539 case ISD::ZERO_EXTEND_INREG:
540 Tmp1 = SelectExpr(N.getOperand(0));
541 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
544 assert(0 && "Zero Extend InReg not there yet");
546 case MVT::i16: Tmp2 = 16; break;
547 case MVT::i8: Tmp2 = 24; break;
548 case MVT::i1: Tmp2 = 31; break;
550 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
551 .addImm(Tmp2).addImm(31);
557 case ISD::CopyFromReg:
559 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
560 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
561 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
565 Tmp1 = SelectExpr(N.getOperand(0));
566 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
567 Tmp2 = CN->getValue() & 0x1F;
568 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
571 Tmp2 = SelectExpr(N.getOperand(1));
572 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
577 Tmp1 = SelectExpr(N.getOperand(0));
578 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
579 Tmp2 = CN->getValue() & 0x1F;
580 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(32-Tmp2)
581 .addImm(Tmp2).addImm(31);
583 Tmp2 = SelectExpr(N.getOperand(1));
584 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
589 Tmp1 = SelectExpr(N.getOperand(0));
590 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
591 Tmp2 = CN->getValue() & 0x1F;
592 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
594 Tmp2 = SelectExpr(N.getOperand(1));
595 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
600 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
601 Tmp1 = SelectExpr(N.getOperand(0));
602 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
603 default: assert(0 && "unhandled result code");
604 case 0: // No immediate
605 Tmp2 = SelectExpr(N.getOperand(1));
606 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
608 case 1: // Low immediate
609 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
611 case 2: // Shifted immediate
612 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
618 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
619 Tmp1 = SelectExpr(N.getOperand(0));
620 Tmp2 = SelectExpr(N.getOperand(1));
621 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
627 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
628 Tmp1 = SelectExpr(N.getOperand(0));
629 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
630 default: assert(0 && "unhandled result code");
631 case 0: // No immediate
632 Tmp2 = SelectExpr(N.getOperand(1));
634 case ISD::AND: Opc = PPC::AND; break;
635 case ISD::OR: Opc = PPC::OR; break;
636 case ISD::XOR: Opc = PPC::XOR; break;
638 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
640 case 1: // Low immediate
642 case ISD::AND: Opc = PPC::ANDIo; break;
643 case ISD::OR: Opc = PPC::ORI; break;
644 case ISD::XOR: Opc = PPC::XORI; break;
646 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
648 case 2: // Shifted immediate
650 case ISD::AND: Opc = PPC::ANDISo; break;
651 case ISD::OR: Opc = PPC::ORIS; break;
652 case ISD::XOR: Opc = PPC::XORIS; break;
654 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
666 case ISD::FP_TO_UINT:
667 case ISD::FP_TO_SINT:
674 switch (N.getValueType()) {
675 default: assert(0 && "Cannot use constants of this type!");
677 BuildMI(BB, PPC::LI, 1, Result)
678 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
682 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
683 if (v < 32768 && v >= -32768) {
684 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
686 Tmp1 = MakeReg(MVT::i32);
687 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
688 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
698 void ISel::Select(SDOperand N) {
699 unsigned Tmp1, Tmp2, Opc;
700 unsigned opcode = N.getOpcode();
702 if (!ExprMap.insert(std::make_pair(N, 1)).second)
703 return; // Already selected.
705 SDNode *Node = N.Val;
707 switch (Node->getOpcode()) {
709 Node->dump(); std::cerr << "\n";
710 assert(0 && "Node not handled yet!");
711 case ISD::EntryToken: return; // Noop
712 case ISD::TokenFactor:
713 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
714 Select(Node->getOperand(i));
716 case ISD::ADJCALLSTACKDOWN:
717 case ISD::ADJCALLSTACKUP:
718 Select(N.getOperand(0));
719 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
720 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
722 BuildMI(BB, Opc, 1).addImm(Tmp1);
725 MachineBasicBlock *Dest =
726 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
727 Select(N.getOperand(0));
728 BuildMI(BB, PPC::B, 1).addMBB(Dest);
735 Select(N.getOperand(0));
736 Tmp1 = SelectExpr(N.getOperand(1));
737 Tmp2 = cast<RegSDNode>(N)->getReg();
740 if (N.getOperand(1).getValueType() == MVT::f64 ||
741 N.getOperand(1).getValueType() == MVT::f32)
742 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
744 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
747 case ISD::ImplicitDef:
748 Select(N.getOperand(0));
749 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
752 switch (N.getNumOperands()) {
754 assert(0 && "Unknown return instruction!");
756 assert(N.getOperand(1).getValueType() == MVT::i32 &&
757 N.getOperand(2).getValueType() == MVT::i32 &&
758 "Unknown two-register value!");
759 Select(N.getOperand(0));
760 Tmp1 = SelectExpr(N.getOperand(1));
761 Tmp2 = SelectExpr(N.getOperand(2));
762 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
763 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
766 Select(N.getOperand(0));
767 Tmp1 = SelectExpr(N.getOperand(1));
768 switch (N.getOperand(1).getValueType()) {
770 assert(0 && "Unknown return type!");
773 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
776 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
780 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
782 case ISD::TRUNCSTORE:
785 SDOperand Chain = N.getOperand(0);
786 SDOperand Value = N.getOperand(1);
787 SDOperand Address = N.getOperand(2);
790 Tmp1 = SelectExpr(Value); //value
792 if (opcode == ISD::STORE) {
793 switch(Value.getValueType()) {
794 default: assert(0 && "unknown Type in store");
795 case MVT::i32: Opc = PPC::STW; break;
796 case MVT::f64: Opc = PPC::STFD; break;
797 case MVT::f32: Opc = PPC::STFS; break;
799 } else { //ISD::TRUNCSTORE
800 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
801 default: assert(0 && "unknown Type in store");
802 case MVT::i1: //FIXME: DAG does not promote this load
803 case MVT::i8: Opc = PPC::STB; break;
804 case MVT::i16: Opc = PPC::STH; break;
808 if (Address.getOpcode() == ISD::GlobalAddress)
810 BuildMI(BB, Opc, 2).addReg(Tmp1)
811 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
813 else if(Address.getOpcode() == ISD::FrameIndex)
815 BuildMI(BB, Opc, 2).addReg(Tmp1)
816 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
821 SelectAddr(Address, Tmp2, offset);
822 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
830 case ISD::CopyFromReg:
832 case ISD::DYNAMIC_STACKALLOC:
837 assert(0 && "Should not be reached!");
841 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
842 /// into a machine code representation using pattern matching and a machine
843 /// description file.
845 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {