1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to,
45 /// then a SRCVALUE for the address.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
63 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
64 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
65 /// compute an allocation on the stack.
68 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
69 /// at function entry, used for PIC code.
72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
73 /// shift amounts. These nodes are generated by the multi-precision shift
77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
81 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
84 /// CALL - A direct function call.
87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
88 /// MTCTR instruction.
91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
92 /// BCTRL instruction.
93 BCTRL_Macho, BCTRL_ELF,
95 /// Return with a flag operand, matched by 'blr'
98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
99 /// This copies the bits corresponding to the specified CRREG into the
100 /// resultant GPR. Bits corresponding to other CR regs are undefined.
103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
104 /// instructions. For lack of better number, we use the opcode number
105 /// encoding for the OPC field to identify the compare. For example, 838
109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
110 /// altivec VCMP*o instructions. For lack of better number, we use the
111 /// opcode number encoding for the OPC field to identify the compare. For
112 /// example, 838 is VCMPGTSH.
115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
117 /// condition register to branch on, OPC is the branch opcode to use (e.g.
118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
119 /// an optional input flag argument.
122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
134 // The following 5 instructions are used only as part of the
135 // long double-to-int conversion sequence.
137 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
141 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
144 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
147 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
148 /// rounding towards zero. It has flags added so it won't move past the
149 /// FPSCR-setting instructions.
152 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
155 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
156 /// reserve indexed. This is used to implement atomic operations.
159 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
160 /// indexed. This is used to implement atomic operations.
163 /// TAILCALL - Indicates a tail call should be taken.
165 /// TC_RETURN - A tail call return.
167 /// operand #1 callee (register or absolute)
168 /// operand #2 stack adjustment
169 /// operand #3 optional in flag
174 /// Define some predicates that are used for node matching.
176 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
177 /// VPKUHUM instruction.
178 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
180 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
181 /// VPKUWUM instruction.
182 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
184 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
185 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
186 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
189 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
190 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
191 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
194 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
195 /// amount, otherwise return -1.
196 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
198 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
199 /// specifies a splat of a single element that is suitable for input to
200 /// VSPLTB/VSPLTH/VSPLTW.
201 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
203 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
205 bool isAllNegativeZeroVector(SDNode *N);
207 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
208 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
209 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
211 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
212 /// formed by using a vspltis[bhw] instruction of the specified element
213 /// size, return the constant being splatted. The ByteSize field indicates
214 /// the number of bytes of each element [124] -> [bhw].
215 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
218 class PPCTargetLowering : public TargetLowering {
219 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
220 int VarArgsStackOffset; // StackOffset for start of stack
222 unsigned VarArgsNumGPR; // Index of the first unused integer
223 // register for parameter passing.
224 unsigned VarArgsNumFPR; // Index of the first unused double
225 // register for parameter passing.
226 const PPCSubtarget &PPCSubTarget;
228 explicit PPCTargetLowering(PPCTargetMachine &TM);
230 /// getTargetNodeName() - This method returns the name of a target specific
232 virtual const char *getTargetNodeName(unsigned Opcode) const;
234 /// getSetCCResultType - Return the ISD::SETCC ValueType
235 virtual MVT getSetCCResultType(MVT VT) const;
237 /// getPreIndexedAddressParts - returns true by value, base pointer and
238 /// offset pointer and addressing mode by reference if the node's address
239 /// can be legally represented as pre-indexed load / store address.
240 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
242 ISD::MemIndexedMode &AM,
243 SelectionDAG &DAG) const;
245 /// SelectAddressRegReg - Given the specified addressed, check to see if it
246 /// can be represented as an indexed [r+r] operation. Returns false if it
247 /// can be more efficiently represented with [r+imm].
248 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
249 SelectionDAG &DAG) const;
251 /// SelectAddressRegImm - Returns true if the address N can be represented
252 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
253 /// is not better represented as reg+reg.
254 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
255 SelectionDAG &DAG) const;
257 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
258 /// represented as an indexed [r+r] operation.
259 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
260 SelectionDAG &DAG) const;
262 /// SelectAddressRegImmShift - Returns true if the address N can be
263 /// represented by a base register plus a signed 14-bit displacement
264 /// [r+imm*4]. Suitable for use by STD and friends.
265 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
266 SelectionDAG &DAG) const;
269 /// LowerOperation - Provide custom lowering hooks for some operations.
271 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
273 /// ReplaceNodeResults - Replace the results of node with an illegal result
274 /// type with new values built out of custom code.
276 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
279 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
281 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
285 const SelectionDAG &DAG,
286 unsigned Depth = 0) const;
288 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
289 MachineBasicBlock *MBB) const;
290 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
291 MachineBasicBlock *MBB, bool is64Bit,
292 unsigned BinOpcode) const;
293 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
294 MachineBasicBlock *MBB,
295 bool is8bit, unsigned Opcode) const;
297 ConstraintType getConstraintType(const std::string &Constraint) const;
298 std::pair<unsigned, const TargetRegisterClass*>
299 getRegForInlineAsmConstraint(const std::string &Constraint,
302 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
303 /// function arguments in the caller parameter area. This is the actual
304 /// alignment, not its logarithm.
305 unsigned getByValTypeAlignment(const Type *Ty) const;
307 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
308 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
309 /// true it means one of the asm constraint of the inline asm instruction
310 /// being processed is 'm'.
311 virtual void LowerAsmOperandForConstraint(SDValue Op,
312 char ConstraintLetter,
314 std::vector<SDValue> &Ops,
315 SelectionDAG &DAG) const;
317 /// isLegalAddressingMode - Return true if the addressing mode represented
318 /// by AM is legal for this target, for a load/store of the specified type.
319 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
321 /// isLegalAddressImmediate - Return true if the integer value can be used
322 /// as the offset of the target addressing mode for load / store of the
324 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
326 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
327 /// the offset of the target addressing mode.
328 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
330 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
331 /// for tail call optimization. Target which want to do tail call
332 /// optimization should implement this function.
333 virtual bool IsEligibleForTailCallOptimization(CallSDNode *TheCall,
335 SelectionDAG &DAG) const;
337 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
339 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
340 bool isSrcConst, bool isSrcStr,
341 SelectionDAG &DAG) const;
343 /// getFunctionAlignment - Return the Log2 alignment of this function.
344 virtual unsigned getFunctionAlignment(const Function *F) const;
347 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
348 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
350 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
358 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
359 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
360 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
361 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
362 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
363 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
364 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
365 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
366 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
367 int VarArgsFrameIndex, int VarArgsStackOffset,
368 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
369 const PPCSubtarget &Subtarget);
370 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
371 int VarArgsStackOffset, unsigned VarArgsNumGPR,
372 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
373 SDValue LowerFORMAL_ARGUMENTS_SVR4(SDValue Op, SelectionDAG &DAG,
374 int &VarArgsFrameIndex,
375 int &VarArgsStackOffset,
376 unsigned &VarArgsNumGPR,
377 unsigned &VarArgsNumFPR,
378 const PPCSubtarget &Subtarget);
379 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
380 int &VarArgsFrameIndex,
381 int &VarArgsStackOffset,
382 unsigned &VarArgsNumGPR,
383 unsigned &VarArgsNumFPR,
384 const PPCSubtarget &Subtarget);
385 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG,
386 const PPCSubtarget &Subtarget, TargetMachine &TM);
387 SDValue LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
388 const PPCSubtarget &Subtarget, TargetMachine &TM);
389 SDValue LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM);
390 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
391 const PPCSubtarget &Subtarget);
392 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
393 const PPCSubtarget &Subtarget);
394 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
395 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
396 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
397 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
398 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
399 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
400 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
401 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
402 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
403 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
404 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
405 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
409 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H