1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
28 /// FSEL - Traditional three-operand fsel node.
32 /// FCFID - The FCFID instruction, taking an f64 operand and producing
33 /// and f64 value containing the FP representation of the integer that
34 /// was temporarily in the f64 operand.
37 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
38 /// operand, producing an f64 value containing the integer representation
42 /// STFIWX - The STFIWX instruction. The first operand is an input token
43 /// chain, then an f64 value to store, then an address to store it to,
44 /// then a SRCVALUE for the address.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// LVE_X - The PPC LVE*X instructions. The size of the element loaded is
52 /// the size of the element type of the vector result. The element loaded
53 /// depends on the alignment of the input pointer.
55 /// The first operand is a token chain, the second is the address to load
56 /// the third is the SRCVALUE node.
59 /// VPERM - The PPC VPERM Instruction.
63 /// Hi/Lo - These represent the high and low 16-bit parts of a global
64 /// address respectively. These nodes have two operands, the first of
65 /// which must be a TargetGlobalAddress, and the second of which must be a
66 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
67 /// though these are usually folded into other nodes.
70 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
71 /// at function entry, used for PIC code.
74 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
75 /// shift amounts. These nodes are generated by the multi-precision shift
79 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
83 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
86 /// CALL - A function call.
89 /// Return with a flag operand, matched by 'blr'
94 /// Define some predicates that are used for node matching.
96 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
97 /// specifies a splat of a single element that is suitable for input to
98 /// VSPLTB/VSPLTH/VSPLTW.
99 bool isSplatShuffleMask(SDNode *N);
101 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
102 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
103 unsigned getVSPLTImmediate(SDNode *N);
105 /// isZeroVector - Return true if this build_vector is an all-zero vector.
107 bool isZeroVector(SDNode *N);
109 /// isVecSplatImm - Return true if this is a build_vector of constants which
110 /// can be formed by using a vspltis[bhw] instruction. The ByteSize field
111 /// indicates the number of bytes of each element [124] -> [bhw].
112 bool isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val = 0);
115 class PPCTargetLowering : public TargetLowering {
116 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
117 int ReturnAddrIndex; // FrameIndex for return slot.
119 PPCTargetLowering(TargetMachine &TM);
121 /// getTargetNodeName() - This method returns the name of a target specific
123 virtual const char *getTargetNodeName(unsigned Opcode) const;
125 /// LowerOperation - Provide custom lowering hooks for some operations.
127 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
129 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
131 /// LowerArguments - This hook must be implemented to indicate how we should
132 /// lower the arguments for the specified function, into the specified DAG.
133 virtual std::vector<SDOperand>
134 LowerArguments(Function &F, SelectionDAG &DAG);
136 /// LowerCallTo - This hook lowers an abstract call to a function into an
138 virtual std::pair<SDOperand, SDOperand>
139 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
141 bool isTailCall, SDOperand Callee, ArgListTy &Args,
144 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
145 MachineBasicBlock *MBB);
147 ConstraintType getConstraintType(char ConstraintLetter) const;
148 std::vector<unsigned>
149 getRegClassForInlineAsmConstraint(const std::string &Constraint,
150 MVT::ValueType VT) const;
151 bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
153 /// isLegalAddressImmediate - Return true if the integer value can be used
154 /// as the offset of the target addressing mode.
155 virtual bool isLegalAddressImmediate(int64_t V) const;
159 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H