1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to,
45 /// then a SRCVALUE for the address.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
63 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
64 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
65 /// compute an allocation on the stack.
68 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
69 /// at function entry, used for PIC code.
72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
73 /// shift amounts. These nodes are generated by the multi-precision shift
77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
81 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
84 /// CALL - A direct function call.
85 CALL_Darwin, CALL_SVR4,
87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
88 /// MTCTR instruction.
91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
92 /// BCTRL instruction.
93 BCTRL_Darwin, BCTRL_SVR4,
95 /// Return with a flag operand, matched by 'blr'
98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
99 /// This copies the bits corresponding to the specified CRREG into the
100 /// resultant GPR. Bits corresponding to other CR regs are undefined.
103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
104 /// instructions. For lack of better number, we use the opcode number
105 /// encoding for the OPC field to identify the compare. For example, 838
109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
110 /// altivec VCMP*o instructions. For lack of better number, we use the
111 /// opcode number encoding for the OPC field to identify the compare. For
112 /// example, 838 is VCMPGTSH.
115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
117 /// condition register to branch on, OPC is the branch opcode to use (e.g.
118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
119 /// an optional input flag argument.
122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
134 // The following 5 instructions are used only as part of the
135 // long double-to-int conversion sequence.
137 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
141 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
144 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
147 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
148 /// rounding towards zero. It has flags added so it won't move past the
149 /// FPSCR-setting instructions.
152 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
155 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
156 /// reserve indexed. This is used to implement atomic operations.
159 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
160 /// indexed. This is used to implement atomic operations.
163 /// TC_RETURN - A tail call return.
165 /// operand #1 callee (register or absolute)
166 /// operand #2 stack adjustment
167 /// operand #3 optional in flag
172 /// Define some predicates that are used for node matching.
174 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
175 /// VPKUHUM instruction.
176 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
178 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
179 /// VPKUWUM instruction.
180 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
182 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
183 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
184 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
187 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
188 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
189 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
192 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
193 /// amount, otherwise return -1.
194 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
196 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
197 /// specifies a splat of a single element that is suitable for input to
198 /// VSPLTB/VSPLTH/VSPLTW.
199 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
201 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
203 bool isAllNegativeZeroVector(SDNode *N);
205 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
206 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
207 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
209 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
210 /// formed by using a vspltis[bhw] instruction of the specified element
211 /// size, return the constant being splatted. The ByteSize field indicates
212 /// the number of bytes of each element [124] -> [bhw].
213 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
216 class PPCTargetLowering : public TargetLowering {
217 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
218 int VarArgsStackOffset; // StackOffset for start of stack
220 unsigned VarArgsNumGPR; // Index of the first unused integer
221 // register for parameter passing.
222 unsigned VarArgsNumFPR; // Index of the first unused double
223 // register for parameter passing.
224 const PPCSubtarget &PPCSubTarget;
226 explicit PPCTargetLowering(PPCTargetMachine &TM);
228 /// getTargetNodeName() - This method returns the name of a target specific
230 virtual const char *getTargetNodeName(unsigned Opcode) const;
232 /// getSetCCResultType - Return the ISD::SETCC ValueType
233 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
235 /// getPreIndexedAddressParts - returns true by value, base pointer and
236 /// offset pointer and addressing mode by reference if the node's address
237 /// can be legally represented as pre-indexed load / store address.
238 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
240 ISD::MemIndexedMode &AM,
241 SelectionDAG &DAG) const;
243 /// SelectAddressRegReg - Given the specified addressed, check to see if it
244 /// can be represented as an indexed [r+r] operation. Returns false if it
245 /// can be more efficiently represented with [r+imm].
246 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
247 SelectionDAG &DAG) const;
249 /// SelectAddressRegImm - Returns true if the address N can be represented
250 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
251 /// is not better represented as reg+reg.
252 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
253 SelectionDAG &DAG) const;
255 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
256 /// represented as an indexed [r+r] operation.
257 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
258 SelectionDAG &DAG) const;
260 /// SelectAddressRegImmShift - Returns true if the address N can be
261 /// represented by a base register plus a signed 14-bit displacement
262 /// [r+imm*4]. Suitable for use by STD and friends.
263 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
264 SelectionDAG &DAG) const;
267 /// LowerOperation - Provide custom lowering hooks for some operations.
269 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
271 /// ReplaceNodeResults - Replace the results of node with an illegal result
272 /// type with new values built out of custom code.
274 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
277 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
279 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
283 const SelectionDAG &DAG,
284 unsigned Depth = 0) const;
286 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
287 MachineBasicBlock *MBB) const;
288 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
289 MachineBasicBlock *MBB, bool is64Bit,
290 unsigned BinOpcode) const;
291 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
292 MachineBasicBlock *MBB,
293 bool is8bit, unsigned Opcode) const;
295 ConstraintType getConstraintType(const std::string &Constraint) const;
296 std::pair<unsigned, const TargetRegisterClass*>
297 getRegForInlineAsmConstraint(const std::string &Constraint,
300 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
301 /// function arguments in the caller parameter area. This is the actual
302 /// alignment, not its logarithm.
303 unsigned getByValTypeAlignment(const Type *Ty) const;
305 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
306 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
307 /// true it means one of the asm constraint of the inline asm instruction
308 /// being processed is 'm'.
309 virtual void LowerAsmOperandForConstraint(SDValue Op,
310 char ConstraintLetter,
312 std::vector<SDValue> &Ops,
313 SelectionDAG &DAG) const;
315 /// isLegalAddressingMode - Return true if the addressing mode represented
316 /// by AM is legal for this target, for a load/store of the specified type.
317 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
319 /// isLegalAddressImmediate - Return true if the integer value can be used
320 /// as the offset of the target addressing mode for load / store of the
322 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
324 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
325 /// the offset of the target addressing mode.
326 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
329 IsEligibleForTailCallOptimization(SDValue Callee,
332 const SmallVectorImpl<ISD::InputArg> &Ins,
333 SelectionDAG& DAG) const;
335 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
337 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
338 bool isSrcConst, bool isSrcStr,
339 SelectionDAG &DAG) const;
341 /// getFunctionAlignment - Return the Log2 alignment of this function.
342 virtual unsigned getFunctionAlignment(const Function *F) const;
345 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
346 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
348 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
356 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
357 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
358 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
359 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
360 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
361 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
362 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
363 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
364 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
365 int VarArgsFrameIndex, int VarArgsStackOffset,
366 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
367 const PPCSubtarget &Subtarget);
368 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
369 int VarArgsStackOffset, unsigned VarArgsNumGPR,
370 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
371 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
372 const PPCSubtarget &Subtarget);
373 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
374 const PPCSubtarget &Subtarget);
375 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
376 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
377 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
378 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
379 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
380 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
381 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
382 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
383 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
384 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
385 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
386 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
388 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
389 unsigned CallConv, bool isVarArg,
390 const SmallVectorImpl<ISD::InputArg> &Ins,
391 DebugLoc dl, SelectionDAG &DAG,
392 SmallVectorImpl<SDValue> &InVals);
393 SDValue FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
396 SmallVector<std::pair<unsigned, SDValue>, 8>
398 SDValue InFlag, SDValue Chain,
400 int SPDiff, unsigned NumBytes,
401 const SmallVectorImpl<ISD::InputArg> &Ins,
402 SmallVectorImpl<SDValue> &InVals);
405 LowerFormalArguments(SDValue Chain,
406 unsigned CallConv, bool isVarArg,
407 const SmallVectorImpl<ISD::InputArg> &Ins,
408 DebugLoc dl, SelectionDAG &DAG,
409 SmallVectorImpl<SDValue> &InVals);
412 LowerCall(SDValue Chain, SDValue Callee,
413 unsigned CallConv, bool isVarArg, bool isTailCall,
414 const SmallVectorImpl<ISD::OutputArg> &Outs,
415 const SmallVectorImpl<ISD::InputArg> &Ins,
416 DebugLoc dl, SelectionDAG &DAG,
417 SmallVectorImpl<SDValue> &InVals);
420 LowerReturn(SDValue Chain,
421 unsigned CallConv, bool isVarArg,
422 const SmallVectorImpl<ISD::OutputArg> &Outs,
423 DebugLoc dl, SelectionDAG &DAG);
426 LowerFormalArguments_Darwin(SDValue Chain,
427 unsigned CallConv, bool isVarArg,
428 const SmallVectorImpl<ISD::InputArg> &Ins,
429 DebugLoc dl, SelectionDAG &DAG,
430 SmallVectorImpl<SDValue> &InVals);
432 LowerFormalArguments_SVR4(SDValue Chain,
433 unsigned CallConv, bool isVarArg,
434 const SmallVectorImpl<ISD::InputArg> &Ins,
435 DebugLoc dl, SelectionDAG &DAG,
436 SmallVectorImpl<SDValue> &InVals);
439 LowerCall_Darwin(SDValue Chain, SDValue Callee,
440 unsigned CallConv, bool isVarArg, bool isTailCall,
441 const SmallVectorImpl<ISD::OutputArg> &Outs,
442 const SmallVectorImpl<ISD::InputArg> &Ins,
443 DebugLoc dl, SelectionDAG &DAG,
444 SmallVectorImpl<SDValue> &InVals);
446 LowerCall_SVR4(SDValue Chain, SDValue Callee,
447 unsigned CallConv, bool isVarArg, bool isTailCall,
448 const SmallVectorImpl<ISD::OutputArg> &Outs,
449 const SmallVectorImpl<ISD::InputArg> &Ins,
450 DebugLoc dl, SelectionDAG &DAG,
451 SmallVectorImpl<SDValue> &InVals);
455 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H