1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// Hi/Lo - These represent the high and low 16-bit parts of a global
65 /// address respectively. These nodes have two operands, the first of
66 /// which must be a TargetGlobalAddress, and the second of which must be a
67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
68 /// though these are usually folded into other nodes.
73 /// The following two target-specific nodes are used for calls through
74 /// function pointers in the 64-bit SVR4 ABI.
76 /// Like a regular LOAD but additionally taking/producing a flag.
79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
85 /// compute an allocation on the stack.
88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
89 /// at function entry, used for PIC code.
92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
93 /// shift amounts. These nodes are generated by the multi-precision shift
97 /// CALL - A direct function call.
98 /// CALL_NOP is a call with the special NOP which follows 64-bit
102 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used
103 /// to access TLS variables.
104 CALL_TLS, CALL_NOP_TLS,
106 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
107 /// MTCTR instruction.
110 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
111 /// BCTRL instruction.
114 /// Return with a flag operand, matched by 'blr'
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
118 /// This copies the bits corresponding to the specified CRREG into the
119 /// resultant GPR. Bits corresponding to other CR regs are undefined.
122 // FIXME: Remove these once the ANDI glue bug is fixed:
123 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
124 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
125 /// implement truncation of i32 or i64 to i1.
126 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
128 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
129 // target (returns (Lo, Hi)). It takes a chain operand.
132 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
135 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
138 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
139 /// instructions. For lack of better number, we use the opcode number
140 /// encoding for the OPC field to identify the compare. For example, 838
144 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
145 /// altivec VCMP*o instructions. For lack of better number, we use the
146 /// opcode number encoding for the OPC field to identify the compare. For
147 /// example, 838 is VCMPGTSH.
150 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
151 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
152 /// condition register to branch on, OPC is the branch opcode to use (e.g.
153 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
154 /// an optional input flag argument.
157 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
161 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
162 /// towards zero. Used only as part of the long double-to-int
163 /// conversion sequence.
166 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
169 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
170 /// reserve indexed. This is used to implement atomic operations.
173 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
174 /// indexed. This is used to implement atomic operations.
177 /// TC_RETURN - A tail call return.
179 /// operand #1 callee (register or absolute)
180 /// operand #2 stack adjustment
181 /// operand #3 optional in flag
184 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
188 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
192 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
193 /// local dynamic TLS on PPC32.
196 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
197 /// TLS model, produces an ADDIS8 instruction that adds the GOT
198 /// base to sym\@got\@tprel\@ha.
201 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
202 /// TLS model, produces a LD instruction with base register G8RReg
203 /// and offset sym\@got\@tprel\@l. This completes the addition that
204 /// finds the offset of "sym" relative to the thread pointer.
207 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
208 /// model, produces an ADD instruction that adds the contents of
209 /// G8RReg to the thread pointer. Symbol contains a relocation
210 /// sym\@tls which is to be replaced by the thread pointer and
211 /// identifies to the linker that the instruction is part of a
215 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
216 /// model, produces an ADDIS8 instruction that adds the GOT base
217 /// register to sym\@got\@tlsgd\@ha.
220 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
221 /// model, produces an ADDI8 instruction that adds G8RReg to
222 /// sym\@got\@tlsgd\@l.
225 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
226 /// model, produces an ADDIS8 instruction that adds the GOT base
227 /// register to sym\@got\@tlsld\@ha.
230 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
231 /// model, produces an ADDI8 instruction that adds G8RReg to
232 /// sym\@got\@tlsld\@l.
235 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
236 /// local-dynamic TLS model, produces an ADDIS8 instruction
237 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
238 /// to tie this in place following a copy to %X3 from the result
239 /// of a GET_TLSLD_ADDR.
242 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
243 /// model, produces an ADDI8 instruction that adds G8RReg to
244 /// sym\@got\@dtprel\@l.
247 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
248 /// during instruction selection to optimize a BUILD_VECTOR into
249 /// operations on splats. This is necessary to avoid losing these
250 /// optimizations due to constant folding.
253 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
254 /// operand identifies the operating system entry point.
257 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
258 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
259 /// or stxvd2x instruction. The chain is necessary because the
260 /// sequence replaces a load and needs to provide the same number
264 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
265 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
266 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
268 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
270 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
271 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
272 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
276 /// STFIWX - The STFIWX instruction. The first operand is an input token
277 /// chain, then an f64 value to store, then an address to store it to.
280 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
281 /// load which sign-extends from a 32-bit integer value into the
282 /// destination 64-bit register.
285 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
286 /// load which zero-extends from a 32-bit integer value into the
287 /// destination 64-bit register.
290 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
291 /// produces an ADDIS8 instruction that adds the TOC base register to
295 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
296 /// produces a LD instruction with base register G8RReg and offset
297 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
300 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
301 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
302 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
305 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
306 /// Maps directly to an lxvd2x instruction that will be followed by
310 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
311 /// Maps directly to an stxvd2x instruction that will be preceded by
317 /// Define some predicates that are used for node matching.
319 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
320 /// VPKUHUM instruction.
321 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
324 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
325 /// VPKUWUM instruction.
326 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
329 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
330 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
331 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
332 unsigned ShuffleKind, SelectionDAG &DAG);
334 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
335 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
336 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
337 unsigned ShuffleKind, SelectionDAG &DAG);
339 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
340 /// shift amount, otherwise return -1.
341 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
344 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
345 /// specifies a splat of a single element that is suitable for input to
346 /// VSPLTB/VSPLTH/VSPLTW.
347 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
349 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
351 bool isAllNegativeZeroVector(SDNode *N);
353 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
354 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
355 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
357 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
358 /// formed by using a vspltis[bhw] instruction of the specified element
359 /// size, return the constant being splatted. The ByteSize field indicates
360 /// the number of bytes of each element [124] -> [bhw].
361 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
365 class PPCTargetLowering : public TargetLowering {
366 const PPCSubtarget &Subtarget;
369 explicit PPCTargetLowering(const PPCTargetMachine &TM);
371 /// getTargetNodeName() - This method returns the name of a target specific
373 const char *getTargetNodeName(unsigned Opcode) const override;
375 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
377 /// getSetCCResultType - Return the ISD::SETCC ValueType
378 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
380 /// Return true if target always beneficiates from combining into FMA for a
381 /// given value type. This must typically return false on targets where FMA
382 /// takes more cycles to execute than FADD.
383 bool enableAggressiveFMAFusion(EVT VT) const override;
385 /// getPreIndexedAddressParts - returns true by value, base pointer and
386 /// offset pointer and addressing mode by reference if the node's address
387 /// can be legally represented as pre-indexed load / store address.
388 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
390 ISD::MemIndexedMode &AM,
391 SelectionDAG &DAG) const override;
393 /// SelectAddressRegReg - Given the specified addressed, check to see if it
394 /// can be represented as an indexed [r+r] operation. Returns false if it
395 /// can be more efficiently represented with [r+imm].
396 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
397 SelectionDAG &DAG) const;
399 /// SelectAddressRegImm - Returns true if the address N can be represented
400 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
401 /// is not better represented as reg+reg. If Aligned is true, only accept
402 /// displacements suitable for STD and friends, i.e. multiples of 4.
403 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
404 SelectionDAG &DAG, bool Aligned) const;
406 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
407 /// represented as an indexed [r+r] operation.
408 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
409 SelectionDAG &DAG) const;
411 Sched::Preference getSchedulingPreference(SDNode *N) const override;
413 /// LowerOperation - Provide custom lowering hooks for some operations.
415 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
417 /// ReplaceNodeResults - Replace the results of node with an illegal result
418 /// type with new values built out of custom code.
420 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
421 SelectionDAG &DAG) const override;
423 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
424 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
426 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
428 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
430 void computeKnownBitsForTargetNode(const SDValue Op,
433 const SelectionDAG &DAG,
434 unsigned Depth = 0) const override;
436 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
437 bool IsStore, bool IsLoad) const override;
438 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
439 bool IsStore, bool IsLoad) const override;
442 EmitInstrWithCustomInserter(MachineInstr *MI,
443 MachineBasicBlock *MBB) const override;
444 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
445 MachineBasicBlock *MBB, bool is64Bit,
446 unsigned BinOpcode) const;
447 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
448 MachineBasicBlock *MBB,
449 bool is8bit, unsigned Opcode) const;
451 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
452 MachineBasicBlock *MBB) const;
454 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
455 MachineBasicBlock *MBB) const;
458 getConstraintType(const std::string &Constraint) const override;
460 /// Examine constraint string and operand type and determine a weight value.
461 /// The operand object must already have been set up with the operand type.
462 ConstraintWeight getSingleConstraintMatchWeight(
463 AsmOperandInfo &info, const char *constraint) const override;
465 std::pair<unsigned, const TargetRegisterClass*>
466 getRegForInlineAsmConstraint(const std::string &Constraint,
467 MVT VT) const override;
469 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
470 /// function arguments in the caller parameter area. This is the actual
471 /// alignment, not its logarithm.
472 unsigned getByValTypeAlignment(Type *Ty) const override;
474 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
475 /// vector. If it is invalid, don't add anything to Ops.
476 void LowerAsmOperandForConstraint(SDValue Op,
477 std::string &Constraint,
478 std::vector<SDValue> &Ops,
479 SelectionDAG &DAG) const override;
481 /// isLegalAddressingMode - Return true if the addressing mode represented
482 /// by AM is legal for this target, for a load/store of the specified type.
483 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
485 /// isLegalICmpImmediate - Return true if the specified immediate is legal
486 /// icmp immediate, that is the target has icmp instructions which can
487 /// compare a register against the immediate without having to materialize
488 /// the immediate into a register.
489 bool isLegalICmpImmediate(int64_t Imm) const override;
491 /// isLegalAddImmediate - Return true if the specified immediate is legal
492 /// add immediate, that is the target has add instructions which can
493 /// add a register and the immediate without having to materialize
494 /// the immediate into a register.
495 bool isLegalAddImmediate(int64_t Imm) const override;
497 /// isTruncateFree - Return true if it's free to truncate a value of
498 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
499 /// register X1 to i32 by referencing its sub-register R1.
500 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
501 bool isTruncateFree(EVT VT1, EVT VT2) const override;
503 /// \brief Returns true if it is beneficial to convert a load of a constant
504 /// to just the constant itself.
505 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
506 Type *Ty) const override;
508 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
510 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
512 unsigned Intrinsic) const override;
514 /// getOptimalMemOpType - Returns the target specific optimal type for load
515 /// and store operations as a result of memset, memcpy, and memmove
516 /// lowering. If DstAlign is zero that means it's safe to destination
517 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
518 /// means there isn't a need to check it against alignment requirement,
519 /// probably because the source does not need to be loaded. If 'IsMemset' is
520 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
521 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
522 /// source is constant so it does not need to be loaded.
523 /// It returns EVT::Other if the type should be determined using generic
524 /// target-independent logic.
526 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
527 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
528 MachineFunction &MF) const override;
530 /// Is unaligned memory access allowed for the given type, and is it fast
531 /// relative to software emulation.
532 bool allowsMisalignedMemoryAccesses(EVT VT,
535 bool *Fast = nullptr) const override;
537 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
538 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
539 /// expanded to FMAs when this method returns true, otherwise fmuladd is
540 /// expanded to fmul + fadd.
541 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
543 // Should we expand the build vector with shuffles?
545 shouldExpandBuildVectorWithShuffles(EVT VT,
546 unsigned DefinedValues) const override;
548 /// createFastISel - This method returns a target-specific FastISel object,
549 /// or null if the target does not support "fast" instruction selection.
550 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
551 const TargetLibraryInfo *LibInfo) const override;
553 /// \brief Returns true if an argument of type Ty needs to be passed in a
554 /// contiguous block of registers in calling convention CallConv.
555 bool functionArgumentNeedsConsecutiveRegisters(
556 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
557 // We support any array type as "consecutive" block in the parameter
558 // save area. The element type defines the alignment requirement and
559 // whether the argument should go in GPRs, FPRs, or VRs if available.
561 // Note that clang uses this capability both to implement the ELFv2
562 // homogeneous float/vector aggregate ABI, and to avoid having to use
563 // "byval" when passing aggregates that might fully fit in registers.
564 return Ty->isArrayTy();
568 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
569 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
572 IsEligibleForTailCallOptimization(SDValue Callee,
573 CallingConv::ID CalleeCC,
575 const SmallVectorImpl<ISD::InputArg> &Ins,
576 SelectionDAG& DAG) const;
578 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
586 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
588 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
589 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
590 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl,
591 SelectionDAG &DAG) const;
592 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
593 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
594 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
595 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
596 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
597 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
598 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
599 const PPCSubtarget &Subtarget) const;
600 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
601 const PPCSubtarget &Subtarget) const;
602 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
603 const PPCSubtarget &Subtarget) const;
604 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
605 const PPCSubtarget &Subtarget) const;
606 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
607 const PPCSubtarget &Subtarget) const;
608 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
612 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
613 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
614 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
616 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
617 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
618 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
619 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
620 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
621 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
622 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
623 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
625 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
626 CallingConv::ID CallConv, bool isVarArg,
627 const SmallVectorImpl<ISD::InputArg> &Ins,
628 SDLoc dl, SelectionDAG &DAG,
629 SmallVectorImpl<SDValue> &InVals) const;
630 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
633 SmallVector<std::pair<unsigned, SDValue>, 8>
635 SDValue InFlag, SDValue Chain,
637 int SPDiff, unsigned NumBytes,
638 const SmallVectorImpl<ISD::InputArg> &Ins,
639 SmallVectorImpl<SDValue> &InVals) const;
642 LowerFormalArguments(SDValue Chain,
643 CallingConv::ID CallConv, bool isVarArg,
644 const SmallVectorImpl<ISD::InputArg> &Ins,
645 SDLoc dl, SelectionDAG &DAG,
646 SmallVectorImpl<SDValue> &InVals) const override;
649 LowerCall(TargetLowering::CallLoweringInfo &CLI,
650 SmallVectorImpl<SDValue> &InVals) const override;
653 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
655 const SmallVectorImpl<ISD::OutputArg> &Outs,
656 LLVMContext &Context) const override;
659 LowerReturn(SDValue Chain,
660 CallingConv::ID CallConv, bool isVarArg,
661 const SmallVectorImpl<ISD::OutputArg> &Outs,
662 const SmallVectorImpl<SDValue> &OutVals,
663 SDLoc dl, SelectionDAG &DAG) const override;
666 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
667 SDValue ArgVal, SDLoc dl) const;
670 LowerFormalArguments_Darwin(SDValue Chain,
671 CallingConv::ID CallConv, bool isVarArg,
672 const SmallVectorImpl<ISD::InputArg> &Ins,
673 SDLoc dl, SelectionDAG &DAG,
674 SmallVectorImpl<SDValue> &InVals) const;
676 LowerFormalArguments_64SVR4(SDValue Chain,
677 CallingConv::ID CallConv, bool isVarArg,
678 const SmallVectorImpl<ISD::InputArg> &Ins,
679 SDLoc dl, SelectionDAG &DAG,
680 SmallVectorImpl<SDValue> &InVals) const;
682 LowerFormalArguments_32SVR4(SDValue Chain,
683 CallingConv::ID CallConv, bool isVarArg,
684 const SmallVectorImpl<ISD::InputArg> &Ins,
685 SDLoc dl, SelectionDAG &DAG,
686 SmallVectorImpl<SDValue> &InVals) const;
689 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
690 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
691 SelectionDAG &DAG, SDLoc dl) const;
694 LowerCall_Darwin(SDValue Chain, SDValue Callee,
695 CallingConv::ID CallConv,
696 bool isVarArg, bool isTailCall,
697 const SmallVectorImpl<ISD::OutputArg> &Outs,
698 const SmallVectorImpl<SDValue> &OutVals,
699 const SmallVectorImpl<ISD::InputArg> &Ins,
700 SDLoc dl, SelectionDAG &DAG,
701 SmallVectorImpl<SDValue> &InVals) const;
703 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
704 CallingConv::ID CallConv,
705 bool isVarArg, bool isTailCall,
706 const SmallVectorImpl<ISD::OutputArg> &Outs,
707 const SmallVectorImpl<SDValue> &OutVals,
708 const SmallVectorImpl<ISD::InputArg> &Ins,
709 SDLoc dl, SelectionDAG &DAG,
710 SmallVectorImpl<SDValue> &InVals) const;
712 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
713 bool isVarArg, bool isTailCall,
714 const SmallVectorImpl<ISD::OutputArg> &Outs,
715 const SmallVectorImpl<SDValue> &OutVals,
716 const SmallVectorImpl<ISD::InputArg> &Ins,
717 SDLoc dl, SelectionDAG &DAG,
718 SmallVectorImpl<SDValue> &InVals) const;
720 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
721 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
723 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
724 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
726 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
727 unsigned &RefinementSteps,
728 bool &UseOneConstNR) const override;
729 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
730 unsigned &RefinementSteps) const override;
731 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
733 CCAssignFn *useFastISelCCs(unsigned Flag) const;
737 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
738 const TargetLibraryInfo *LibInfo);
741 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
742 CCValAssign::LocInfo &LocInfo,
743 ISD::ArgFlagsTy &ArgFlags,
746 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
748 CCValAssign::LocInfo &LocInfo,
749 ISD::ArgFlagsTy &ArgFlags,
752 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
754 CCValAssign::LocInfo &LocInfo,
755 ISD::ArgFlagsTy &ArgFlags,
759 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H